[llvm] [RISCV][P-ext] Use li for all ones splat_vector. (PR #191748)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

<details>
<summary>Changes</summary>

li -1 can be compressed to c.li.

---
Full diff: https://github.com/llvm/llvm-project/pull/191748.diff


3 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp (+9) 
- (modified) llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll (+20-4) 
- (modified) llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll (+30-6) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index bca51053efda1..e7be2938c2256 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2953,6 +2953,15 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
     unsigned EltSize = VT.getVectorElementType().getSizeInBits();
     APInt Val = ConstNode->getAPIntValue().trunc(EltSize);
 
+    // Use LI for all ones since it can be compressed to c.li.
+    if (Val.isAllOnes()) {
+      SDNode *NewNode = CurDAG->getMachineNode(
+          RISCV::ADDI, DL, VT, CurDAG->getRegister(RISCV::X0, VT),
+          CurDAG->getAllOnesConstant(DL, XLenVT, /*IsTarget=*/true));
+      ReplaceNode(Node, NewNode);
+      return;
+    }
+
     // Find the smallest splat.
     if (Val.getBitWidth() > 16 && Val.isSplat(16))
       Val = Val.trunc(16);
diff --git a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll b/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
index 3c03eaebeb06b..f27063f5cc89f 100644
--- a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
@@ -500,6 +500,22 @@ define <2 x i16> @test_plui_h_negative() {
   ret <2 x i16> splat (i16 u0xb640)
 }
 
+define <4 x i8> @test_allones_v4i8() {
+; CHECK-LABEL: test_allones_v4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, -1
+; CHECK-NEXT:    ret
+  ret <4 x i8> splat (i8 -1)
+}
+
+define <2 x i16> @test_allones_v2i16() {
+; CHECK-LABEL: test_allones_v2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, -1
+; CHECK-NEXT:    ret
+  ret <2 x i16> splat (i16 -1)
+}
+
 define i16 @test_extract_vector_16(<2 x i16> %a) {
 ; CHECK-LABEL: test_extract_vector_16:
 ; CHECK:       # %bb.0:
@@ -1963,10 +1979,10 @@ define <2 x i16> @test_select_v2i16(i1 %cond, <2 x i16> %a, <2 x i16> %b) {
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi a3, a0, 1
 ; CHECK-NEXT:    mv a0, a1
-; CHECK-NEXT:    bnez a3, .LBB138_2
+; CHECK-NEXT:    bnez a3, .LBB140_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    mv a0, a2
-; CHECK-NEXT:  .LBB138_2:
+; CHECK-NEXT:  .LBB140_2:
 ; CHECK-NEXT:    ret
   %res = select i1 %cond, <2 x i16> %a, <2 x i16> %b
   ret <2 x i16> %res
@@ -1977,10 +1993,10 @@ define <4 x i8> @test_select_v4i8(i1 %cond, <4 x i8> %a, <4 x i8> %b) {
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi a3, a0, 1
 ; CHECK-NEXT:    mv a0, a1
-; CHECK-NEXT:    bnez a3, .LBB139_2
+; CHECK-NEXT:    bnez a3, .LBB141_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    mv a0, a2
-; CHECK-NEXT:  .LBB139_2:
+; CHECK-NEXT:  .LBB141_2:
 ; CHECK-NEXT:    ret
   %res = select i1 %cond, <4 x i8> %a, <4 x i8> %b
   ret <4 x i8> %res
diff --git a/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll b/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
index c431d8a2a1197..5ea865aca82c8 100644
--- a/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
@@ -639,6 +639,30 @@ define <2 x i32> @test_plui_w_negative() {
   ret <2 x i32> splat (i32 u0xc9800000)
 }
 
+define <8 x i8> @test_allones_v8i8() {
+; CHECK-LABEL: test_allones_v8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, -1
+; CHECK-NEXT:    ret
+  ret <8 x i8> splat (i8 -1)
+}
+
+define <4 x i16> @test_allones_v4i16() {
+; CHECK-LABEL: test_allones_v4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, -1
+; CHECK-NEXT:    ret
+  ret <4 x i16> splat (i16 -1)
+}
+
+define <2 x i32> @test_allones_v2i32() {
+; CHECK-LABEL: test_allones_v2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, -1
+; CHECK-NEXT:    ret
+  ret <2 x i32> splat (i32 -1)
+}
+
 define i16 @test_extract_vector_16(<4 x i16> %a) {
 ; CHECK-LABEL: test_extract_vector_16:
 ; CHECK:       # %bb.0:
@@ -2507,10 +2531,10 @@ define <4 x i16> @test_select_v4i16(i1 %cond, <4 x i16> %a, <4 x i16> %b) {
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi a3, a0, 1
 ; CHECK-NEXT:    mv a0, a1
-; CHECK-NEXT:    bnez a3, .LBB202_2
+; CHECK-NEXT:    bnez a3, .LBB205_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    mv a0, a2
-; CHECK-NEXT:  .LBB202_2:
+; CHECK-NEXT:  .LBB205_2:
 ; CHECK-NEXT:    ret
   %res = select i1 %cond, <4 x i16> %a, <4 x i16> %b
   ret <4 x i16> %res
@@ -2521,10 +2545,10 @@ define <8 x i8> @test_select_v8i8(i1 %cond, <8 x i8> %a, <8 x i8> %b) {
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi a3, a0, 1
 ; CHECK-NEXT:    mv a0, a1
-; CHECK-NEXT:    bnez a3, .LBB203_2
+; CHECK-NEXT:    bnez a3, .LBB206_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    mv a0, a2
-; CHECK-NEXT:  .LBB203_2:
+; CHECK-NEXT:  .LBB206_2:
 ; CHECK-NEXT:    ret
   %res = select i1 %cond, <8 x i8> %a, <8 x i8> %b
   ret <8 x i8> %res
@@ -2535,10 +2559,10 @@ define <2 x i32> @test_select_v2i32(i1 %cond, <2 x i32> %a, <2 x i32> %b) {
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi a3, a0, 1
 ; CHECK-NEXT:    mv a0, a1
-; CHECK-NEXT:    bnez a3, .LBB204_2
+; CHECK-NEXT:    bnez a3, .LBB207_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    mv a0, a2
-; CHECK-NEXT:  .LBB204_2:
+; CHECK-NEXT:  .LBB207_2:
 ; CHECK-NEXT:    ret
   %res = select i1 %cond, <2 x i32> %a, <2 x i32> %b
   ret <2 x i32> %res

``````````

</details>


https://github.com/llvm/llvm-project/pull/191748