[llvm] [GlobalISel] Change SSUBO to do (LHS < RHS) XOR (RESULT < 0) (PR #191744)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 12 17:43:05 PDT 2026
https://github.com/SiliconA-Z created https://github.com/llvm/llvm-project/pull/191744
Refactor lowerSADDO_SSUBO in LegalizerHelper and expandSADDSUBO in TargetLowering so addition and subtraction use separate, clearly named paths.
SADDO: unchanged meaning: overflow when (result < LHS) disagrees with (RHS < 0) (signed compares).
SSUBO: use the equivalent formulation: overflow when (LHS < RHS) disagrees with (result < 0) instead of (result < LHS) vs (RHS > 0).
>From 5951ac40be4c43116bdaa7f828cdc38cfda7ae46 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sun, 12 Apr 2026 20:21:12 -0400
Subject: [PATCH] [GlobalISel] Change SSUBO to do (LHS < RHS) XOR (RESULT < 0)
Refactor lowerSADDO_SSUBO in LegalizerHelper and expandSADDSUBO in TargetLowering so addition and subtraction use separate, clearly named paths.
SADDO: unchanged meaning: overflow when (result < LHS) disagrees with (RHS < 0) (signed compares).
SSUBO: use the equivalent formulation: overflow when (LHS < RHS) disagrees with (result < 0) instead of (result < LHS) vs (RHS > 0).
---
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 30 +-
.../AMDGPU/GlobalISel/legalize-ssubo.mir | 152 +-
.../AMDGPU/GlobalISel/legalize-ssubsat.mir | 54 +-
.../test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll | 1676 ++++++++---------
llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll | 312 +--
.../legalizer/legalize-addo-subo-rv32.mir | 20 +-
.../legalizer/legalize-addo-subo-rv64.mir | 6 +-
.../legalizer/legalize-sat-rv32.mir | 20 +-
.../legalizer/legalize-sat-rv64.mir | 6 +-
.../signed_arithmetic_overflow.ll | 12 +-
10 files changed, 1094 insertions(+), 1194 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index b3a51f9fd5761..0a21dc5a74eb8 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -9665,18 +9665,24 @@ LegalizerHelper::lowerSADDO_SSUBO(MachineInstr &MI) {
auto Zero = MIRBuilder.buildConstant(Ty, 0);
- // For an addition, the result should be less than one of the operands (LHS)
- // if and only if the other operand (RHS) is negative, otherwise there will
- // be overflow.
- // For a subtraction, the result should be less than one of the operands
- // (LHS) if and only if the other operand (RHS) is (non-zero) positive,
- // otherwise there will be overflow.
- auto ResultLowerThanLHS =
- MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, NewDst0, LHS);
- auto ConditionRHS = MIRBuilder.buildICmp(
- IsAdd ? CmpInst::ICMP_SLT : CmpInst::ICMP_SGT, BoolTy, RHS, Zero);
-
- MIRBuilder.buildXor(Dst1, ConditionRHS, ResultLowerThanLHS);
+ if (IsAdd) {
+ // For an addition, the result should be less than one of the operands (LHS)
+ // if and only if the other operand (RHS) is negative, otherwise there will
+ // be overflow.
+ auto ResultLowerThanLHS =
+ MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, NewDst0, LHS);
+ auto RHSNegative =
+ MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, RHS, Zero);
+ MIRBuilder.buildXor(Dst1, RHSNegative, ResultLowerThanLHS);
+ } else {
+ // For subtraction, overflow occurs when the signed comparison of operands
+ // doesn't match the sign of the result.
+ auto LHSLessThanRHS =
+ MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, LHS, RHS);
+ auto ResultNegative =
+ MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, NewDst0, Zero);
+ MIRBuilder.buildXor(Dst1, LHSLessThanRHS, ResultNegative);
+ }
MIRBuilder.buildCopy(Dst0, NewDst0);
MI.eraseFromParent();
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
index d28edb05e1b18..ad2dd81af9dc8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
@@ -14,12 +14,12 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 7
- ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 7
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 7
+ ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 7
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
- ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 7
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG2]](s32), [[C]]
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]]
+ ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 7
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG2]](s32), [[C]]
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[ICMP1]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[XOR]](s1)
@@ -48,13 +48,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
- ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 16
- ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
+ ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
- ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
+ ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 16
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG2]](s32), [[C]]
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG2]](s32), [[C]]
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[ICMP1]]
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[XOR]](s1)
; CHECK-NEXT: $vgpr0 = COPY [[SUB]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[ZEXT]](s32)
@@ -82,9 +82,9 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB]](s32), [[COPY]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY1]](s32), [[C]]
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB]](s32), [[C]]
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[ICMP1]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[XOR]](s1)
; CHECK-NEXT: $vgpr0 = COPY [[COPY2]](s32)
@@ -114,9 +114,9 @@ body: |
; CHECK-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[MV]](s64), [[COPY]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY1]](s64), [[C]]
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[MV]](s64), [[C]]
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[ICMP1]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[XOR]](s1)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[COPY2]](s64)
@@ -155,22 +155,22 @@ body: |
; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK-NEXT: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 16
- ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST3]], 16
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
- ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB1]], 16
- ; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR2]], 16
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG2]](s32), [[SEXT_INREG3]]
; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
- ; CHECK-NEXT: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST4]], 16
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST3]], 16
+ ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST4]], 16
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
+ ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR2]], 16
+ ; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR3]], 16
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG2]](s32), [[SEXT_INREG3]]
+ ; CHECK-NEXT: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 16
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG4]](s32), [[COPY2]]
- ; CHECK-NEXT: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR3]], 16
- ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG5]](s32), [[C2]]
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP2]], [[ICMP]]
- ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP3]], [[ICMP1]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG4]](s32), [[COPY2]]
+ ; CHECK-NEXT: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB1]], 16
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG5]](s32), [[C2]]
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[ICMP2]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP3]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s1)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR1]](s1)
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s16>) = COPY [[BITCAST2]](<2 x s16>)
@@ -214,31 +214,31 @@ body: |
; CHECK-NEXT: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[UV6]](<2 x s16>)
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; CHECK-NEXT: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
- ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 16
- ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST4]], 16
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
- ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB1]], 16
- ; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR2]], 16
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG2]](s32), [[SEXT_INREG3]]
- ; CHECK-NEXT: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB2]], 16
- ; CHECK-NEXT: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST5]], 16
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG4]](s32), [[SEXT_INREG5]]
; CHECK-NEXT: [[UV9:%[0-9]+]]:_(<2 x s16>), [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<6 x s16>)
; CHECK-NEXT: [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[UV9]](<2 x s16>)
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; CHECK-NEXT: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV10]](<2 x s16>)
- ; CHECK-NEXT: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST6]], 16
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST4]], 16
+ ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST6]], 16
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
+ ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR2]], 16
+ ; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR3]], 16
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG2]](s32), [[SEXT_INREG3]]
+ ; CHECK-NEXT: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST5]], 16
+ ; CHECK-NEXT: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST7]], 16
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG4]](s32), [[SEXT_INREG5]]
+ ; CHECK-NEXT: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 16
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG6]](s32), [[COPY2]]
- ; CHECK-NEXT: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR3]], 16
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG6]](s32), [[COPY2]]
+ ; CHECK-NEXT: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB1]], 16
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG7]](s32), [[COPY3]]
- ; CHECK-NEXT: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST7]], 16
- ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG8]](s32), [[C1]]
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP3]], [[ICMP]]
- ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP4]], [[ICMP1]]
- ; CHECK-NEXT: [[XOR2:%[0-9]+]]:_(s1) = G_XOR [[ICMP5]], [[ICMP2]]
+ ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG7]](s32), [[COPY3]]
+ ; CHECK-NEXT: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB2]], 16
+ ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG8]](s32), [[C1]]
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[ICMP3]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP4]]
+ ; CHECK-NEXT: [[XOR2:%[0-9]+]]:_(s1) = G_XOR [[ICMP2]], [[ICMP5]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s1)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR1]](s1)
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR2]](s1)
@@ -318,39 +318,39 @@ body: |
; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; CHECK-NEXT: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
- ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 16
- ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST6]], 16
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
- ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB1]], 16
- ; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR4]], 16
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG2]](s32), [[SEXT_INREG3]]
- ; CHECK-NEXT: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB2]], 16
- ; CHECK-NEXT: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST7]], 16
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG4]](s32), [[SEXT_INREG5]]
- ; CHECK-NEXT: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB3]], 16
- ; CHECK-NEXT: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR5]], 16
- ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG6]](s32), [[SEXT_INREG7]]
; CHECK-NEXT: [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
; CHECK-NEXT: [[BITCAST8:%[0-9]+]]:_(s32) = G_BITCAST [[UV6]](<2 x s16>)
; CHECK-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST8]], [[C]](s32)
; CHECK-NEXT: [[BITCAST9:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; CHECK-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST9]], [[C]](s32)
- ; CHECK-NEXT: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST8]], 16
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST6]], 16
+ ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST8]], 16
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
+ ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR4]], 16
+ ; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR6]], 16
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG2]](s32), [[SEXT_INREG3]]
+ ; CHECK-NEXT: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST7]], 16
+ ; CHECK-NEXT: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST9]], 16
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG4]](s32), [[SEXT_INREG5]]
+ ; CHECK-NEXT: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR5]], 16
+ ; CHECK-NEXT: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR7]], 16
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG6]](s32), [[SEXT_INREG7]]
+ ; CHECK-NEXT: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 16
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG8]](s32), [[COPY2]]
- ; CHECK-NEXT: [[SEXT_INREG9:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR6]], 16
+ ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG8]](s32), [[COPY2]]
+ ; CHECK-NEXT: [[SEXT_INREG9:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB1]], 16
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG9]](s32), [[COPY3]]
- ; CHECK-NEXT: [[SEXT_INREG10:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST9]], 16
+ ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG9]](s32), [[COPY3]]
+ ; CHECK-NEXT: [[SEXT_INREG10:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB2]], 16
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG10]](s32), [[COPY4]]
- ; CHECK-NEXT: [[SEXT_INREG11:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR7]], 16
- ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG11]](s32), [[C2]]
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP4]], [[ICMP]]
- ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP5]], [[ICMP1]]
- ; CHECK-NEXT: [[XOR2:%[0-9]+]]:_(s1) = G_XOR [[ICMP6]], [[ICMP2]]
- ; CHECK-NEXT: [[XOR3:%[0-9]+]]:_(s1) = G_XOR [[ICMP7]], [[ICMP3]]
+ ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG10]](s32), [[COPY4]]
+ ; CHECK-NEXT: [[SEXT_INREG11:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB3]], 16
+ ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG11]](s32), [[C2]]
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[ICMP4]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP5]]
+ ; CHECK-NEXT: [[XOR2:%[0-9]+]]:_(s1) = G_XOR [[ICMP2]], [[ICMP6]]
+ ; CHECK-NEXT: [[XOR3:%[0-9]+]]:_(s1) = G_XOR [[ICMP3]], [[ICMP7]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s1)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR1]](s1)
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR2]](s1)
@@ -390,13 +390,13 @@ body: |
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SUB]](s32), [[SUB1]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB]](s32), [[UV4]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB1]](s32), [[UV5]]
; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[UV6]](s32), [[C]]
- ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[UV7]](s32), [[C]]
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP2]], [[ICMP]]
- ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP3]], [[ICMP1]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[UV4]](s32), [[UV6]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[UV5]](s32), [[UV7]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB]](s32), [[C]]
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB1]](s32), [[C]]
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[ICMP2]]
+ ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP3]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s1)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR1]](s1)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[BUILD_VECTOR]](<2 x s32>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
index dc49872c78fc3..d34946bcd8ccd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
@@ -927,9 +927,9 @@ body: |
; GFX6-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]
; GFX6-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
; GFX6-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[MV]](s64), [[COPY]]
- ; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY1]](s64), [[C]]
- ; GFX6-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]]
+ ; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
+ ; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[MV]](s64), [[C]]
+ ; GFX6-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[ICMP1]]
; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX6-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY2]], [[C1]](s32)
@@ -953,9 +953,9 @@ body: |
; GFX8-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]
; GFX8-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
; GFX8-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[MV]](s64), [[COPY]]
- ; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY1]](s64), [[C]]
- ; GFX8-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]]
+ ; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
+ ; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[MV]](s64), [[C]]
+ ; GFX8-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[ICMP1]]
; GFX8-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX8-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY2]], [[C1]](s32)
@@ -979,9 +979,9 @@ body: |
; GFX9-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]
; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[MV]](s64), [[COPY]]
- ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY1]](s64), [[C]]
- ; GFX9-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]]
+ ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
+ ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[MV]](s64), [[C]]
+ ; GFX9-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[ICMP1]]
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX9-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY2]], [[C1]](s32)
@@ -1018,9 +1018,9 @@ body: |
; GFX6-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV5]], [[UV7]], [[USUBO1]]
; GFX6-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
; GFX6-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[MV]](s64), [[UV]]
- ; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[UV2]](s64), [[C]]
- ; GFX6-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]]
+ ; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[UV]](s64), [[UV2]]
+ ; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[MV]](s64), [[C]]
+ ; GFX6-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[ICMP1]]
; GFX6-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
; GFX6-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX6-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY2]], [[C1]](s32)
@@ -1036,9 +1036,9 @@ body: |
; GFX6-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV12]], [[UV14]]
; GFX6-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV13]], [[UV15]], [[USUBO3]]
; GFX6-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32)
- ; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[MV2]](s64), [[UV1]]
- ; GFX6-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[UV3]](s64), [[C]]
- ; GFX6-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP3]], [[ICMP2]]
+ ; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[UV1]](s64), [[UV3]]
+ ; GFX6-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[MV2]](s64), [[C]]
+ ; GFX6-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP2]], [[ICMP3]]
; GFX6-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY [[MV2]](s64)
; GFX6-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[COPY3]], [[C1]](s32)
; GFX6-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR1]](s64)
@@ -1063,9 +1063,9 @@ body: |
; GFX8-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV5]], [[UV7]], [[USUBO1]]
; GFX8-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
; GFX8-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[MV]](s64), [[UV]]
- ; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[UV2]](s64), [[C]]
- ; GFX8-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]]
+ ; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[UV]](s64), [[UV2]]
+ ; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[MV]](s64), [[C]]
+ ; GFX8-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[ICMP1]]
; GFX8-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX8-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY2]], [[C1]](s32)
@@ -1081,9 +1081,9 @@ body: |
; GFX8-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV12]], [[UV14]]
; GFX8-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV13]], [[UV15]], [[USUBO3]]
; GFX8-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32)
- ; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[MV2]](s64), [[UV1]]
- ; GFX8-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[UV3]](s64), [[C]]
- ; GFX8-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP3]], [[ICMP2]]
+ ; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[UV1]](s64), [[UV3]]
+ ; GFX8-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[MV2]](s64), [[C]]
+ ; GFX8-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP2]], [[ICMP3]]
; GFX8-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY [[MV2]](s64)
; GFX8-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[COPY3]], [[C1]](s32)
; GFX8-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR1]](s64)
@@ -1108,9 +1108,9 @@ body: |
; GFX9-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV5]], [[UV7]], [[USUBO1]]
; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[MV]](s64), [[UV]]
- ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[UV2]](s64), [[C]]
- ; GFX9-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]]
+ ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[UV]](s64), [[UV2]]
+ ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[MV]](s64), [[C]]
+ ; GFX9-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[ICMP1]]
; GFX9-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
; GFX9-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX9-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY2]], [[C1]](s32)
@@ -1126,9 +1126,9 @@ body: |
; GFX9-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV12]], [[UV14]]
; GFX9-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV13]], [[UV15]], [[USUBO3]]
; GFX9-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32)
- ; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[MV2]](s64), [[UV1]]
- ; GFX9-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[UV3]](s64), [[C]]
- ; GFX9-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP3]], [[ICMP2]]
+ ; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[UV1]](s64), [[UV3]]
+ ; GFX9-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[MV2]](s64), [[C]]
+ ; GFX9-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP2]], [[ICMP3]]
; GFX9-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY [[MV2]](s64)
; GFX9-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[COPY3]], [[C1]](s32)
; GFX9-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR1]](s64)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
index 39960760a5961..38eebd4ae1c25 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
@@ -1044,14 +1044,14 @@ define i24 @v_ssubsat_i24(i24 %lhs, i24 %rhs) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v0, v1
-; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 24
; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 24
-; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v0
-; GFX8-NEXT: v_bfe_i32 v0, v1, 0, 24
-; GFX8-NEXT: v_cmp_lt_i32_e64 s[6:7], 0, v0
-; GFX8-NEXT: v_ashrrev_i32_e32 v0, 23, v3
+; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 24
+; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v0, v1
+; GFX8-NEXT: v_bfe_i32 v0, v2, 0, 24
+; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v0
+; GFX8-NEXT: v_ashrrev_i32_e32 v0, 23, v0
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0xff800000, v0
-; GFX8-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]
+; GFX8-NEXT: s_xor_b64 vcc, s[4:5], s[6:7]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
@@ -1094,15 +1094,15 @@ define amdgpu_ps i24 @s_ssubsat_i24(i24 inreg %lhs, i24 inreg %rhs) {
; GFX8-LABEL: s_ssubsat_i24:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_sub_i32 s2, s0, s1
-; GFX8-NEXT: s_bfe_i32 s3, s2, 0x180000
; GFX8-NEXT: s_bfe_i32 s0, s0, 0x180000
-; GFX8-NEXT: s_cmp_lt_i32 s3, s0
-; GFX8-NEXT: s_cselect_b32 s0, 1, 0
; GFX8-NEXT: s_bfe_i32 s1, s1, 0x180000
-; GFX8-NEXT: s_cmp_gt_i32 s1, 0
-; GFX8-NEXT: s_cselect_b32 s1, 1, 0
-; GFX8-NEXT: s_xor_b32 s0, s1, s0
-; GFX8-NEXT: s_ashr_i32 s1, s3, 23
+; GFX8-NEXT: s_cmp_lt_i32 s0, s1
+; GFX8-NEXT: s_cselect_b32 s0, 1, 0
+; GFX8-NEXT: s_bfe_i32 s1, s2, 0x180000
+; GFX8-NEXT: s_cmp_lt_i32 s1, 0
+; GFX8-NEXT: s_cselect_b32 s3, 1, 0
+; GFX8-NEXT: s_ashr_i32 s1, s1, 23
+; GFX8-NEXT: s_xor_b32 s0, s0, s3
; GFX8-NEXT: s_add_i32 s1, s1, 0xff800000
; GFX8-NEXT: s_cmp_lg_u32 s0, 0
; GFX8-NEXT: s_cselect_b32 s0, s1, s2
@@ -4173,15 +4173,15 @@ define i48 @v_ssubsat_i48(i48 %lhs, i48 %rhs) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v0, v2
; GFX6-NEXT: v_subb_u32_e32 v6, vcc, v1, v3, vcc
-; GFX6-NEXT: v_bfe_i32 v5, v6, 0, 16
; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16
-; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], v[4:5], v[0:1]
-; GFX6-NEXT: v_cmp_lt_i64_e64 s[6:7], 0, v[2:3]
+; GFX6-NEXT: v_bfe_i32 v5, v6, 0, 16
+; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], v[0:1], v[2:3]
+; GFX6-NEXT: v_cmp_gt_i64_e64 s[6:7], 0, v[4:5]
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v5
; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0xffff8000, v0
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 15, v5
-; GFX6-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]
+; GFX6-NEXT: s_xor_b64 vcc, s[4:5], s[6:7]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
@@ -4191,15 +4191,15 @@ define i48 @v_ssubsat_i48(i48 %lhs, i48 %rhs) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v0, v2
; GFX8-NEXT: v_subb_u32_e32 v6, vcc, v1, v3, vcc
-; GFX8-NEXT: v_bfe_i32 v5, v6, 0, 16
; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX8-NEXT: v_bfe_i32 v3, v3, 0, 16
-; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], v[4:5], v[0:1]
-; GFX8-NEXT: v_cmp_lt_i64_e64 s[6:7], 0, v[2:3]
+; GFX8-NEXT: v_bfe_i32 v5, v6, 0, 16
+; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], v[0:1], v[2:3]
+; GFX8-NEXT: v_cmp_gt_i64_e64 s[6:7], 0, v[4:5]
; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v5
; GFX8-NEXT: v_add_u32_e32 v2, vcc, 0xffff8000, v0
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 15, v5
-; GFX8-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]
+; GFX8-NEXT: s_xor_b64 vcc, s[4:5], s[6:7]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -4211,11 +4211,11 @@ define i48 @v_ssubsat_i48(i48 %lhs, i48 %rhs) {
; GFX9-NEXT: v_lshlrev_b64 v[2:3], 16, v[2:3]
; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v0, v2
; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v1, v3, vcc
-; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1]
-; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[2:3]
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[4:5]
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v5
; GFX9-NEXT: v_add_u32_e32 v1, 0x80000000, v0
-; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc
+; GFX9-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX9-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]
@@ -4228,9 +4228,9 @@ define i48 @v_ssubsat_i48(i48 %lhs, i48 %rhs) {
; GFX10-NEXT: v_lshlrev_b64 v[2:3], 16, v[2:3]
; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v2
; GFX10-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo
-; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[2:3]
+; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v5
-; GFX10-NEXT: v_cmp_lt_i64_e64 s4, v[4:5], v[0:1]
+; GFX10-NEXT: v_cmp_gt_i64_e64 s4, 0, v[4:5]
; GFX10-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v6
; GFX10-NEXT: s_xor_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc_lo
@@ -4245,9 +4245,9 @@ define i48 @v_ssubsat_i48(i48 %lhs, i48 %rhs) {
; GFX11-NEXT: v_lshlrev_b64 v[2:3], 16, v[2:3]
; GFX11-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v2
; GFX11-NEXT: v_sub_co_ci_u32_e64 v5, null, v1, v3, vcc_lo
-; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[2:3]
+; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-NEXT: v_ashrrev_i32_e32 v6, 31, v5
-; GFX11-NEXT: v_cmp_lt_i64_e64 s0, v[4:5], v[0:1]
+; GFX11-NEXT: v_cmp_gt_i64_e64 s0, 0, v[4:5]
; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v6
; GFX11-NEXT: s_xor_b32 vcc_lo, vcc_lo, s0
; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v6 :: v_dual_cndmask_b32 v1, v5, v1
@@ -4262,21 +4262,21 @@ define amdgpu_ps i48 @s_ssubsat_i48(i48 inreg %lhs, i48 inreg %rhs) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_sub_u32 s4, s0, s2
; GFX6-NEXT: s_subb_u32 s5, s1, s3
+; GFX6-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x300000
+; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
-; GFX6-NEXT: v_mov_b32_e32 v0, s0
-; GFX6-NEXT: s_bfe_i64 s[6:7], s[4:5], 0x300000
-; GFX6-NEXT: v_mov_b32_e32 v1, s1
-; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[6:7], v[0:1]
+; GFX6-NEXT: v_mov_b32_e32 v1, s3
+; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]
; GFX6-NEXT: s_or_b64 s[0:1], vcc, vcc
-; GFX6-NEXT: s_cselect_b32 s3, 1, 0
-; GFX6-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x300000
-; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], 0
-; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
+; GFX6-NEXT: s_cselect_b32 s6, 1, 0
+; GFX6-NEXT: s_bfe_i64 s[0:1], s[4:5], 0x300000
+; GFX6-NEXT: v_cmp_lt_i64_e64 s[2:3], s[0:1], 0
+; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
; GFX6-NEXT: s_cselect_b32 s0, 1, 0
-; GFX6-NEXT: s_ashr_i32 s1, s7, 31
-; GFX6-NEXT: s_xor_b32 s2, s0, s3
-; GFX6-NEXT: s_ashr_i32 s0, s7, 15
-; GFX6-NEXT: s_addk_i32 s1, 0x8000
+; GFX6-NEXT: s_ashr_i32 s3, s1, 31
+; GFX6-NEXT: s_xor_b32 s2, s6, s0
+; GFX6-NEXT: s_ashr_i32 s0, s1, 15
+; GFX6-NEXT: s_add_i32 s1, s3, 0xffff8000
; GFX6-NEXT: s_cmp_lg_u32 s2, 0
; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5]
; GFX6-NEXT: ; return to shader part epilog
@@ -4285,40 +4285,40 @@ define amdgpu_ps i48 @s_ssubsat_i48(i48 inreg %lhs, i48 inreg %rhs) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_sub_u32 s4, s0, s2
; GFX8-NEXT: s_subb_u32 s5, s1, s3
+; GFX8-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x300000
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: s_bfe_i64 s[6:7], s[4:5], 0x300000
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[6:7], v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]
; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX8-NEXT: s_cselect_b32 s3, 1, 0
-; GFX8-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x300000
-; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], 0
-; GFX8-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX8-NEXT: s_cselect_b32 s6, 1, 0
+; GFX8-NEXT: s_bfe_i64 s[0:1], s[4:5], 0x300000
+; GFX8-NEXT: v_cmp_lt_i64_e64 s[2:3], s[0:1], 0
+; GFX8-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8-NEXT: s_cselect_b32 s0, 1, 0
-; GFX8-NEXT: s_ashr_i32 s1, s7, 31
-; GFX8-NEXT: s_xor_b32 s2, s0, s3
-; GFX8-NEXT: s_ashr_i32 s0, s7, 15
-; GFX8-NEXT: s_addk_i32 s1, 0x8000
+; GFX8-NEXT: s_ashr_i32 s3, s1, 31
+; GFX8-NEXT: s_xor_b32 s2, s6, s0
+; GFX8-NEXT: s_ashr_i32 s0, s1, 15
+; GFX8-NEXT: s_add_i32 s1, s3, 0xffff8000
; GFX8-NEXT: s_cmp_lg_u32 s2, 0
; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5]
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_ssubsat_i48:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], 16
; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], 16
+; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], 16
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: s_sub_u32 s4, s0, s2
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]
; GFX9-NEXT: s_subb_u32 s5, s1, s3
-; GFX9-NEXT: v_mov_b32_e32 v1, s1
-; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
-; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 0
+; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], s[4:5], 0
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_cselect_b32 s6, 1, 0
+; GFX9-NEXT: s_cselect_b32 s2, 1, 0
; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX9-NEXT: s_cselect_b32 s0, 1, 0
-; GFX9-NEXT: s_xor_b32 s2, s0, s6
+; GFX9-NEXT: s_xor_b32 s2, s2, s0
; GFX9-NEXT: s_ashr_i32 s0, s5, 31
; GFX9-NEXT: s_add_i32 s1, s0, 0x80000000
; GFX9-NEXT: s_cmp_lg_u32 s2, 0
@@ -4331,15 +4331,15 @@ define amdgpu_ps i48 @s_ssubsat_i48(i48 inreg %lhs, i48 inreg %rhs) {
; GFX10PLUS-NEXT: s_lshl_b64 s[0:1], s[0:1], 16
; GFX10PLUS-NEXT: s_lshl_b64 s[2:3], s[2:3], 16
; GFX10PLUS-NEXT: s_sub_u32 s4, s0, s2
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s0, s[0:1], s[2:3]
; GFX10PLUS-NEXT: s_subb_u32 s5, s1, s3
-; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s0, s[4:5], s[0:1]
-; GFX10PLUS-NEXT: v_cmp_gt_i64_e64 s1, s[2:3], 0
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s1, s[4:5], 0
; GFX10PLUS-NEXT: s_cmp_lg_u32 s0, 0
; GFX10PLUS-NEXT: s_cselect_b32 s2, 1, 0
; GFX10PLUS-NEXT: s_cmp_lg_u32 s1, 0
; GFX10PLUS-NEXT: s_cselect_b32 s1, 1, 0
; GFX10PLUS-NEXT: s_ashr_i32 s0, s5, 31
-; GFX10PLUS-NEXT: s_xor_b32 s2, s1, s2
+; GFX10PLUS-NEXT: s_xor_b32 s2, s2, s1
; GFX10PLUS-NEXT: s_add_i32 s1, s0, 0x80000000
; GFX10PLUS-NEXT: s_cmp_lg_u32 s2, 0
; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5]
@@ -4355,15 +4355,15 @@ define amdgpu_ps <2 x float> @ssubsat_i48_sv(i48 inreg %lhs, i48 %rhs) {
; GFX6-NEXT: v_mov_b32_e32 v3, s1
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s0, v0
; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v3, v1, vcc
-; GFX6-NEXT: v_bfe_i32 v3, v4, 0, 16
; GFX6-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
-; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], v[2:3]
-; GFX6-NEXT: v_cmp_lt_i64_e64 s[2:3], 0, v[0:1]
+; GFX6-NEXT: v_bfe_i32 v3, v4, 0, 16
+; GFX6-NEXT: v_cmp_lt_i64_e64 s[0:1], s[0:1], v[0:1]
+; GFX6-NEXT: v_cmp_gt_i64_e64 s[2:3], 0, v[2:3]
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 15, v3
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0xffff8000, v0
-; GFX6-NEXT: s_xor_b64 vcc, s[2:3], s[0:1]
+; GFX6-NEXT: s_xor_b64 vcc, s[0:1], s[2:3]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -4374,15 +4374,15 @@ define amdgpu_ps <2 x float> @ssubsat_i48_sv(i48 inreg %lhs, i48 %rhs) {
; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s0, v0
; GFX8-NEXT: v_subb_u32_e32 v4, vcc, v3, v1, vcc
-; GFX8-NEXT: v_bfe_i32 v3, v4, 0, 16
; GFX8-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 16
-; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], v[2:3]
-; GFX8-NEXT: v_cmp_lt_i64_e64 s[2:3], 0, v[0:1]
+; GFX8-NEXT: v_bfe_i32 v3, v4, 0, 16
+; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], s[0:1], v[0:1]
+; GFX8-NEXT: v_cmp_gt_i64_e64 s[2:3], 0, v[2:3]
; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 15, v3
; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0xffff8000, v0
-; GFX8-NEXT: s_xor_b64 vcc, s[2:3], s[0:1]
+; GFX8-NEXT: s_xor_b64 vcc, s[0:1], s[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -4395,11 +4395,11 @@ define amdgpu_ps <2 x float> @ssubsat_i48_sv(i48 inreg %lhs, i48 %rhs) {
; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_sub_co_u32_e32 v2, vcc, s0, v0
; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v1, vcc
-; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[0:1], v[2:3]
-; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], 0, v[0:1]
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]
+; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], 0, v[2:3]
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX9-NEXT: v_add_u32_e32 v1, 0x80000000, v0
-; GFX9-NEXT: s_xor_b64 vcc, s[0:1], vcc
+; GFX9-NEXT: s_xor_b64 vcc, vcc, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX9-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]
@@ -4412,11 +4412,11 @@ define amdgpu_ps <2 x float> @ssubsat_i48_sv(i48 inreg %lhs, i48 %rhs) {
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 16
; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, s0, v0
; GFX10-NEXT: v_sub_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
+; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, s[0:1], v[0:1]
; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v3
-; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_lt_i64_e64 s0, 0, v[0:1]
+; GFX10-NEXT: v_cmp_gt_i64_e64 s0, 0, v[2:3]
; GFX10-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v4
-; GFX10-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo
+; GFX10-NEXT: s_xor_b32 vcc_lo, vcc_lo, s0
; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX10-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]
@@ -4429,11 +4429,11 @@ define amdgpu_ps <2 x float> @ssubsat_i48_sv(i48 inreg %lhs, i48 %rhs) {
; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 16
; GFX11-NEXT: v_sub_co_u32 v2, vcc_lo, s0, v0
; GFX11-NEXT: v_sub_co_ci_u32_e64 v3, null, s1, v1, vcc_lo
+; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, s[0:1], v[0:1]
; GFX11-NEXT: v_ashrrev_i32_e32 v4, 31, v3
-; GFX11-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_lt_i64_e64 s0, 0, v[0:1]
+; GFX11-NEXT: v_cmp_gt_i64_e64 s0, 0, v[2:3]
; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v4
-; GFX11-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo
+; GFX11-NEXT: s_xor_b32 vcc_lo, vcc_lo, s0
; GFX11-NEXT: v_dual_cndmask_b32 v0, v2, v4 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -4449,18 +4449,16 @@ define amdgpu_ps <2 x float> @ssubsat_i48_vs(i48 %lhs, i48 inreg %rhs) {
; GFX6: ; %bb.0:
; GFX6-NEXT: v_mov_b32_e32 v3, s1
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s0, v0
-; GFX6-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v1, v3, vcc
-; GFX6-NEXT: v_cmp_gt_i64_e64 s[2:3], s[0:1], 0
-; GFX6-NEXT: v_bfe_i32 v3, v4, 0, 16
; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
-; GFX6-NEXT: v_cmp_lt_i64_e64 s[0:1], v[2:3], v[0:1]
-; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; GFX6-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
+; GFX6-NEXT: v_bfe_i32 v3, v4, 0, 16
+; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], v[0:1]
+; GFX6-NEXT: v_cmp_gt_i64_e64 s[2:3], 0, v[2:3]
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v3
-; GFX6-NEXT: s_cselect_b64 s[2:3], exec, 0
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 15, v3
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0xffff8000, v0
-; GFX6-NEXT: s_xor_b64 vcc, s[2:3], s[0:1]
+; GFX6-NEXT: s_xor_b64 vcc, s[0:1], s[2:3]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -4470,18 +4468,16 @@ define amdgpu_ps <2 x float> @ssubsat_i48_vs(i48 %lhs, i48 inreg %rhs) {
; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s0, v0
-; GFX8-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
; GFX8-NEXT: v_subb_u32_e32 v4, vcc, v1, v3, vcc
-; GFX8-NEXT: v_cmp_gt_i64_e64 s[2:3], s[0:1], 0
-; GFX8-NEXT: v_bfe_i32 v3, v4, 0, 16
; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 16
-; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], v[2:3], v[0:1]
-; GFX8-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX8-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
+; GFX8-NEXT: v_bfe_i32 v3, v4, 0, 16
+; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], v[0:1]
+; GFX8-NEXT: v_cmp_gt_i64_e64 s[2:3], 0, v[2:3]
; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v3
-; GFX8-NEXT: s_cselect_b64 s[2:3], exec, 0
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 15, v3
; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0xffff8000, v0
-; GFX8-NEXT: s_xor_b64 vcc, s[2:3], s[0:1]
+; GFX8-NEXT: s_xor_b64 vcc, s[0:1], s[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -4493,14 +4489,12 @@ define amdgpu_ps <2 x float> @ssubsat_i48_vs(i48 %lhs, i48 inreg %rhs) {
; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], 16
; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s0, v0
-; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], 0
; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v1, v3, vcc
-; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[0:1]
-; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX9-NEXT: s_cselect_b64 s[0:1], exec, 0
+; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[0:1], v[0:1]
+; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], 0, v[2:3]
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX9-NEXT: v_add_u32_e32 v1, 0x80000000, v0
-; GFX9-NEXT: s_xor_b64 vcc, s[0:1], vcc
+; GFX9-NEXT: s_xor_b64 vcc, vcc, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX9-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]
@@ -4513,13 +4507,11 @@ define amdgpu_ps <2 x float> @ssubsat_i48_vs(i48 %lhs, i48 inreg %rhs) {
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 16
; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v0, s0
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT: v_cmp_gt_i64_e64 s0, s[0:1], 0
+; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[0:1]
; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v3
-; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]
-; GFX10-NEXT: s_cmp_lg_u32 s0, 0
-; GFX10-NEXT: s_cselect_b32 s0, exec_lo, 0
+; GFX10-NEXT: v_cmp_gt_i64_e64 s0, 0, v[2:3]
; GFX10-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v4
-; GFX10-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo
+; GFX10-NEXT: s_xor_b32 vcc_lo, vcc_lo, s0
; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX10-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]
@@ -4532,13 +4524,11 @@ define amdgpu_ps <2 x float> @ssubsat_i48_vs(i48 %lhs, i48 inreg %rhs) {
; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 16
; GFX11-NEXT: v_sub_co_u32 v2, vcc_lo, v0, s0
; GFX11-NEXT: v_subrev_co_ci_u32_e64 v3, null, s1, v1, vcc_lo
-; GFX11-NEXT: v_cmp_gt_i64_e64 s0, s[0:1], 0
+; GFX11-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[0:1]
; GFX11-NEXT: v_ashrrev_i32_e32 v4, 31, v3
-; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]
-; GFX11-NEXT: s_cmp_lg_u32 s0, 0
-; GFX11-NEXT: s_cselect_b32 s0, exec_lo, 0
+; GFX11-NEXT: v_cmp_gt_i64_e64 s0, 0, v[2:3]
; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v4
-; GFX11-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo
+; GFX11-NEXT: s_xor_b32 vcc_lo, vcc_lo, s0
; GFX11-NEXT: v_dual_cndmask_b32 v0, v2, v4 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -4555,11 +4545,11 @@ define i64 @v_ssubsat_i64(i64 %lhs, i64 %rhs) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v0, v2
; GFX6-NEXT: v_subb_u32_e32 v5, vcc, v1, v3, vcc
-; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], v[4:5], v[0:1]
-; GFX6-NEXT: v_cmp_lt_i64_e64 s[6:7], 0, v[2:3]
+; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], v[0:1], v[2:3]
+; GFX6-NEXT: v_cmp_gt_i64_e64 s[6:7], 0, v[4:5]
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v5
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0x80000000, v0
-; GFX6-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]
+; GFX6-NEXT: s_xor_b64 vcc, s[4:5], s[6:7]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
@@ -4569,11 +4559,11 @@ define i64 @v_ssubsat_i64(i64 %lhs, i64 %rhs) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v0, v2
; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v1, v3, vcc
-; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], v[4:5], v[0:1]
-; GFX8-NEXT: v_cmp_lt_i64_e64 s[6:7], 0, v[2:3]
+; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], v[0:1], v[2:3]
+; GFX8-NEXT: v_cmp_gt_i64_e64 s[6:7], 0, v[4:5]
; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v5
; GFX8-NEXT: v_add_u32_e32 v1, vcc, 0x80000000, v0
-; GFX8-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]
+; GFX8-NEXT: s_xor_b64 vcc, s[4:5], s[6:7]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -4583,11 +4573,11 @@ define i64 @v_ssubsat_i64(i64 %lhs, i64 %rhs) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v0, v2
; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v1, v3, vcc
-; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1]
-; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[2:3]
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[4:5]
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v5
; GFX9-NEXT: v_add_u32_e32 v1, 0x80000000, v0
-; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc
+; GFX9-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -4597,11 +4587,11 @@ define i64 @v_ssubsat_i64(i64 %lhs, i64 %rhs) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v2
; GFX10-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo
-; GFX10-NEXT: v_cmp_lt_i64_e64 s4, 0, v[2:3]
+; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v5
-; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1]
+; GFX10-NEXT: v_cmp_gt_i64_e64 s4, 0, v[4:5]
; GFX10-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v6
-; GFX10-NEXT: s_xor_b32 vcc_lo, s4, vcc_lo
+; GFX10-NEXT: s_xor_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -4611,11 +4601,11 @@ define i64 @v_ssubsat_i64(i64 %lhs, i64 %rhs) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v2
; GFX11-NEXT: v_sub_co_ci_u32_e64 v5, null, v1, v3, vcc_lo
-; GFX11-NEXT: v_cmp_lt_i64_e64 s0, 0, v[2:3]
+; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-NEXT: v_ashrrev_i32_e32 v6, 31, v5
-; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1]
+; GFX11-NEXT: v_cmp_gt_i64_e64 s0, 0, v[4:5]
; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v6
-; GFX11-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo
+; GFX11-NEXT: s_xor_b32 vcc_lo, vcc_lo, s0
; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v6 :: v_dual_cndmask_b32 v1, v5, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)
@@ -4625,17 +4615,17 @@ define i64 @v_ssubsat_i64(i64 %lhs, i64 %rhs) {
define amdgpu_ps i64 @s_ssubsat_i64(i64 inreg %lhs, i64 inreg %rhs) {
; GFX6-LABEL: s_ssubsat_i64:
; GFX6: ; %bb.0:
+; GFX6-NEXT: v_mov_b32_e32 v0, s2
+; GFX6-NEXT: v_mov_b32_e32 v1, s3
; GFX6-NEXT: s_sub_u32 s4, s0, s2
-; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]
; GFX6-NEXT: s_subb_u32 s5, s1, s3
-; GFX6-NEXT: v_mov_b32_e32 v1, s1
-; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
; GFX6-NEXT: s_or_b64 s[0:1], vcc, vcc
-; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 0
-; GFX6-NEXT: s_cselect_b32 s6, 1, 0
+; GFX6-NEXT: v_cmp_lt_i64_e64 s[0:1], s[4:5], 0
+; GFX6-NEXT: s_cselect_b32 s2, 1, 0
; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
; GFX6-NEXT: s_cselect_b32 s0, 1, 0
-; GFX6-NEXT: s_xor_b32 s2, s0, s6
+; GFX6-NEXT: s_xor_b32 s2, s2, s0
; GFX6-NEXT: s_ashr_i32 s0, s5, 31
; GFX6-NEXT: s_add_i32 s1, s0, 0x80000000
; GFX6-NEXT: s_cmp_lg_u32 s2, 0
@@ -4644,17 +4634,17 @@ define amdgpu_ps i64 @s_ssubsat_i64(i64 inreg %lhs, i64 inreg %rhs) {
;
; GFX8-LABEL: s_ssubsat_i64:
; GFX8: ; %bb.0:
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: s_sub_u32 s4, s0, s2
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]
; GFX8-NEXT: s_subb_u32 s5, s1, s3
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
-; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 0
+; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], s[4:5], 0
; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX8-NEXT: s_cselect_b32 s6, 1, 0
+; GFX8-NEXT: s_cselect_b32 s2, 1, 0
; GFX8-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX8-NEXT: s_cselect_b32 s0, 1, 0
-; GFX8-NEXT: s_xor_b32 s2, s0, s6
+; GFX8-NEXT: s_xor_b32 s2, s2, s0
; GFX8-NEXT: s_ashr_i32 s0, s5, 31
; GFX8-NEXT: s_add_i32 s1, s0, 0x80000000
; GFX8-NEXT: s_cmp_lg_u32 s2, 0
@@ -4663,17 +4653,17 @@ define amdgpu_ps i64 @s_ssubsat_i64(i64 inreg %lhs, i64 inreg %rhs) {
;
; GFX9-LABEL: s_ssubsat_i64:
; GFX9: ; %bb.0:
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: s_sub_u32 s4, s0, s2
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]
; GFX9-NEXT: s_subb_u32 s5, s1, s3
-; GFX9-NEXT: v_mov_b32_e32 v1, s1
-; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
-; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 0
+; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], s[4:5], 0
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_cselect_b32 s6, 1, 0
+; GFX9-NEXT: s_cselect_b32 s2, 1, 0
; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX9-NEXT: s_cselect_b32 s0, 1, 0
-; GFX9-NEXT: s_xor_b32 s2, s0, s6
+; GFX9-NEXT: s_xor_b32 s2, s2, s0
; GFX9-NEXT: s_ashr_i32 s0, s5, 31
; GFX9-NEXT: s_add_i32 s1, s0, 0x80000000
; GFX9-NEXT: s_cmp_lg_u32 s2, 0
@@ -4683,15 +4673,15 @@ define amdgpu_ps i64 @s_ssubsat_i64(i64 inreg %lhs, i64 inreg %rhs) {
; GFX10PLUS-LABEL: s_ssubsat_i64:
; GFX10PLUS: ; %bb.0:
; GFX10PLUS-NEXT: s_sub_u32 s4, s0, s2
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s0, s[0:1], s[2:3]
; GFX10PLUS-NEXT: s_subb_u32 s5, s1, s3
-; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s0, s[4:5], s[0:1]
-; GFX10PLUS-NEXT: v_cmp_gt_i64_e64 s1, s[2:3], 0
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s1, s[4:5], 0
; GFX10PLUS-NEXT: s_cmp_lg_u32 s0, 0
; GFX10PLUS-NEXT: s_cselect_b32 s2, 1, 0
; GFX10PLUS-NEXT: s_cmp_lg_u32 s1, 0
; GFX10PLUS-NEXT: s_cselect_b32 s1, 1, 0
; GFX10PLUS-NEXT: s_ashr_i32 s0, s5, 31
-; GFX10PLUS-NEXT: s_xor_b32 s2, s1, s2
+; GFX10PLUS-NEXT: s_xor_b32 s2, s2, s1
; GFX10PLUS-NEXT: s_add_i32 s1, s0, 0x80000000
; GFX10PLUS-NEXT: s_cmp_lg_u32 s2, 0
; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5]
@@ -4706,11 +4696,11 @@ define amdgpu_ps <2 x float> @ssubsat_i64_sv(i64 inreg %lhs, i64 %rhs) {
; GFX6-NEXT: v_mov_b32_e32 v3, s1
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s0, v0
; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v3, v1, vcc
-; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], v[2:3]
-; GFX6-NEXT: v_cmp_lt_i64_e64 s[2:3], 0, v[0:1]
+; GFX6-NEXT: v_cmp_lt_i64_e64 s[0:1], s[0:1], v[0:1]
+; GFX6-NEXT: v_cmp_gt_i64_e64 s[2:3], 0, v[2:3]
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0x80000000, v0
-; GFX6-NEXT: s_xor_b64 vcc, s[2:3], s[0:1]
+; GFX6-NEXT: s_xor_b64 vcc, s[0:1], s[2:3]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-NEXT: ; return to shader part epilog
@@ -4720,11 +4710,11 @@ define amdgpu_ps <2 x float> @ssubsat_i64_sv(i64 inreg %lhs, i64 %rhs) {
; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s0, v0
; GFX8-NEXT: v_subb_u32_e32 v3, vcc, v3, v1, vcc
-; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], v[2:3]
-; GFX8-NEXT: v_cmp_lt_i64_e64 s[2:3], 0, v[0:1]
+; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], s[0:1], v[0:1]
+; GFX8-NEXT: v_cmp_gt_i64_e64 s[2:3], 0, v[2:3]
; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX8-NEXT: v_add_u32_e32 v1, vcc, 0x80000000, v0
-; GFX8-NEXT: s_xor_b64 vcc, s[2:3], s[0:1]
+; GFX8-NEXT: s_xor_b64 vcc, s[0:1], s[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-NEXT: ; return to shader part epilog
@@ -4734,11 +4724,11 @@ define amdgpu_ps <2 x float> @ssubsat_i64_sv(i64 inreg %lhs, i64 %rhs) {
; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_sub_co_u32_e32 v2, vcc, s0, v0
; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v1, vcc
-; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[0:1], v[2:3]
-; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], 0, v[0:1]
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]
+; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], 0, v[2:3]
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX9-NEXT: v_add_u32_e32 v1, 0x80000000, v0
-; GFX9-NEXT: s_xor_b64 vcc, s[0:1], vcc
+; GFX9-NEXT: s_xor_b64 vcc, vcc, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX9-NEXT: ; return to shader part epilog
@@ -4747,11 +4737,11 @@ define amdgpu_ps <2 x float> @ssubsat_i64_sv(i64 inreg %lhs, i64 %rhs) {
; GFX10: ; %bb.0:
; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, s0, v0
; GFX10-NEXT: v_sub_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
+; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, s[0:1], v[0:1]
; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v3
-; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_lt_i64_e64 s0, 0, v[0:1]
+; GFX10-NEXT: v_cmp_gt_i64_e64 s0, 0, v[2:3]
; GFX10-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v4
-; GFX10-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo
+; GFX10-NEXT: s_xor_b32 vcc_lo, vcc_lo, s0
; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX10-NEXT: ; return to shader part epilog
@@ -4760,11 +4750,11 @@ define amdgpu_ps <2 x float> @ssubsat_i64_sv(i64 inreg %lhs, i64 %rhs) {
; GFX11: ; %bb.0:
; GFX11-NEXT: v_sub_co_u32 v2, vcc_lo, s0, v0
; GFX11-NEXT: v_sub_co_ci_u32_e64 v3, null, s1, v1, vcc_lo
+; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, s[0:1], v[0:1]
; GFX11-NEXT: v_ashrrev_i32_e32 v4, 31, v3
-; GFX11-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[2:3]
-; GFX11-NEXT: v_cmp_lt_i64_e64 s0, 0, v[0:1]
+; GFX11-NEXT: v_cmp_gt_i64_e64 s0, 0, v[2:3]
; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v4
-; GFX11-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo
+; GFX11-NEXT: s_xor_b32 vcc_lo, vcc_lo, s0
; GFX11-NEXT: v_dual_cndmask_b32 v0, v2, v4 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-NEXT: ; return to shader part epilog
%result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)
@@ -4777,14 +4767,12 @@ define amdgpu_ps <2 x float> @ssubsat_i64_vs(i64 %lhs, i64 inreg %rhs) {
; GFX6: ; %bb.0:
; GFX6-NEXT: v_mov_b32_e32 v3, s1
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s0, v0
-; GFX6-NEXT: v_cmp_gt_i64_e64 s[2:3], s[0:1], 0
; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v1, v3, vcc
-; GFX6-NEXT: v_cmp_lt_i64_e64 s[0:1], v[2:3], v[0:1]
-; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], v[0:1]
+; GFX6-NEXT: v_cmp_gt_i64_e64 s[2:3], 0, v[2:3]
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v3
-; GFX6-NEXT: s_cselect_b64 s[2:3], exec, 0
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0x80000000, v0
-; GFX6-NEXT: s_xor_b64 vcc, s[2:3], s[0:1]
+; GFX6-NEXT: s_xor_b64 vcc, s[0:1], s[2:3]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-NEXT: ; return to shader part epilog
@@ -4793,14 +4781,12 @@ define amdgpu_ps <2 x float> @ssubsat_i64_vs(i64 %lhs, i64 inreg %rhs) {
; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s0, v0
-; GFX8-NEXT: v_cmp_gt_i64_e64 s[2:3], s[0:1], 0
; GFX8-NEXT: v_subb_u32_e32 v3, vcc, v1, v3, vcc
-; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], v[2:3], v[0:1]
-; GFX8-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], v[0:1]
+; GFX8-NEXT: v_cmp_gt_i64_e64 s[2:3], 0, v[2:3]
; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v3
-; GFX8-NEXT: s_cselect_b64 s[2:3], exec, 0
; GFX8-NEXT: v_add_u32_e32 v1, vcc, 0x80000000, v0
-; GFX8-NEXT: s_xor_b64 vcc, s[2:3], s[0:1]
+; GFX8-NEXT: s_xor_b64 vcc, s[0:1], s[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-NEXT: ; return to shader part epilog
@@ -4809,14 +4795,12 @@ define amdgpu_ps <2 x float> @ssubsat_i64_vs(i64 %lhs, i64 inreg %rhs) {
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s0, v0
-; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], 0
; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v1, v3, vcc
-; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[0:1]
-; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX9-NEXT: s_cselect_b64 s[0:1], exec, 0
+; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[0:1], v[0:1]
+; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], 0, v[2:3]
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX9-NEXT: v_add_u32_e32 v1, 0x80000000, v0
-; GFX9-NEXT: s_xor_b64 vcc, s[0:1], vcc
+; GFX9-NEXT: s_xor_b64 vcc, vcc, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX9-NEXT: ; return to shader part epilog
@@ -4825,13 +4809,11 @@ define amdgpu_ps <2 x float> @ssubsat_i64_vs(i64 %lhs, i64 inreg %rhs) {
; GFX10: ; %bb.0:
; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v0, s0
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT: v_cmp_gt_i64_e64 s0, s[0:1], 0
+; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[0:1]
; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v3
-; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]
-; GFX10-NEXT: s_cmp_lg_u32 s0, 0
-; GFX10-NEXT: s_cselect_b32 s0, exec_lo, 0
+; GFX10-NEXT: v_cmp_gt_i64_e64 s0, 0, v[2:3]
; GFX10-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v4
-; GFX10-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo
+; GFX10-NEXT: s_xor_b32 vcc_lo, vcc_lo, s0
; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX10-NEXT: ; return to shader part epilog
@@ -4840,13 +4822,11 @@ define amdgpu_ps <2 x float> @ssubsat_i64_vs(i64 %lhs, i64 inreg %rhs) {
; GFX11: ; %bb.0:
; GFX11-NEXT: v_sub_co_u32 v2, vcc_lo, v0, s0
; GFX11-NEXT: v_subrev_co_ci_u32_e64 v3, null, s1, v1, vcc_lo
-; GFX11-NEXT: v_cmp_gt_i64_e64 s0, s[0:1], 0
+; GFX11-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[0:1]
; GFX11-NEXT: v_ashrrev_i32_e32 v4, 31, v3
-; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]
-; GFX11-NEXT: s_cmp_lg_u32 s0, 0
-; GFX11-NEXT: s_cselect_b32 s0, exec_lo, 0
+; GFX11-NEXT: v_cmp_gt_i64_e64 s0, 0, v[2:3]
; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v4
-; GFX11-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo
+; GFX11-NEXT: s_xor_b32 vcc_lo, vcc_lo, s0
; GFX11-NEXT: v_dual_cndmask_b32 v0, v2, v4 :: v_dual_cndmask_b32 v1, v3, v1
; GFX11-NEXT: ; return to shader part epilog
%result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)
@@ -4860,21 +4840,21 @@ define <2 x i64> @v_ssubsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v0, v4
; GFX6-NEXT: v_subb_u32_e32 v9, vcc, v1, v5, vcc
-; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], v[8:9], v[0:1]
-; GFX6-NEXT: v_cmp_lt_i64_e64 s[6:7], 0, v[4:5]
+; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], v[0:1], v[4:5]
+; GFX6-NEXT: v_cmp_gt_i64_e64 s[6:7], 0, v[8:9]
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v9
; GFX6-NEXT: v_bfrev_b32_e32 v1, 1
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v0, v1
-; GFX6-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]
+; GFX6-NEXT: s_xor_b64 vcc, s[4:5], s[6:7]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v2, v6
; GFX6-NEXT: v_subb_u32_e32 v5, vcc, v3, v7, vcc
-; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], v[4:5], v[2:3]
-; GFX6-NEXT: v_cmp_lt_i64_e64 s[6:7], 0, v[6:7]
+; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], v[2:3], v[6:7]
+; GFX6-NEXT: v_cmp_gt_i64_e64 s[6:7], 0, v[4:5]
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v5
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0x80000000, v2
-; GFX6-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]
+; GFX6-NEXT: s_xor_b64 vcc, s[4:5], s[6:7]
; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
@@ -4884,21 +4864,21 @@ define <2 x i64> @v_ssubsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u32_e32 v8, vcc, v0, v4
; GFX8-NEXT: v_subb_u32_e32 v9, vcc, v1, v5, vcc
-; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], v[8:9], v[0:1]
-; GFX8-NEXT: v_cmp_lt_i64_e64 s[6:7], 0, v[4:5]
+; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], v[0:1], v[4:5]
+; GFX8-NEXT: v_cmp_gt_i64_e64 s[6:7], 0, v[8:9]
; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v9
; GFX8-NEXT: v_bfrev_b32_e32 v1, 1
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v0, v1
-; GFX8-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]
+; GFX8-NEXT: s_xor_b64 vcc, s[4:5], s[6:7]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v2, v6
; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v3, v7, vcc
-; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], v[4:5], v[2:3]
-; GFX8-NEXT: v_cmp_lt_i64_e64 s[6:7], 0, v[6:7]
+; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], v[2:3], v[6:7]
+; GFX8-NEXT: v_cmp_gt_i64_e64 s[6:7], 0, v[4:5]
; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v5
; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0x80000000, v2
-; GFX8-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]
+; GFX8-NEXT: s_xor_b64 vcc, s[4:5], s[6:7]
; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -4908,20 +4888,20 @@ define <2 x i64> @v_ssubsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_sub_co_u32_e32 v8, vcc, v0, v4
; GFX9-NEXT: v_subb_co_u32_e32 v9, vcc, v1, v5, vcc
-; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[0:1]
-; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[4:5]
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[4:5]
+; GFX9-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[8:9]
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v9
; GFX9-NEXT: v_add_u32_e32 v1, 0x80000000, v0
-; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc
+; GFX9-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v2, v6
; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v3, v7, vcc
-; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[2:3]
-; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[6:7]
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[6:7]
+; GFX9-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[4:5]
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v5
; GFX9-NEXT: v_add_u32_e32 v3, 0x80000000, v2
-; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc
+; GFX9-NEXT: s_xor_b64 vcc, vcc, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -4934,17 +4914,17 @@ define <2 x i64> @v_ssubsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
; GFX10-NEXT: v_sub_co_u32 v10, vcc_lo, v2, v6
; GFX10-NEXT: v_sub_co_ci_u32_e32 v11, vcc_lo, v3, v7, vcc_lo
; GFX10-NEXT: v_ashrrev_i32_e32 v12, 31, v9
-; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[8:9], v[0:1]
-; GFX10-NEXT: v_cmp_lt_i64_e64 s4, 0, v[4:5]
+; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX10-NEXT: v_cmp_gt_i64_e64 s4, 0, v[8:9]
; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v11
-; GFX10-NEXT: v_cmp_lt_i64_e64 s5, v[10:11], v[2:3]
-; GFX10-NEXT: v_cmp_lt_i64_e64 s6, 0, v[6:7]
+; GFX10-NEXT: v_cmp_lt_i64_e64 s5, v[2:3], v[6:7]
+; GFX10-NEXT: v_cmp_gt_i64_e64 s6, 0, v[10:11]
; GFX10-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v12
; GFX10-NEXT: v_add_nc_u32_e32 v3, 0x80000000, v4
-; GFX10-NEXT: s_xor_b32 vcc_lo, s4, vcc_lo
+; GFX10-NEXT: s_xor_b32 vcc_lo, vcc_lo, s4
; GFX10-NEXT: v_cndmask_b32_e32 v0, v8, v12, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo
-; GFX10-NEXT: s_xor_b32 vcc_lo, s6, s5
+; GFX10-NEXT: s_xor_b32 vcc_lo, s5, s6
; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -4957,16 +4937,16 @@ define <2 x i64> @v_ssubsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
; GFX11-NEXT: v_sub_co_u32 v10, vcc_lo, v2, v6
; GFX11-NEXT: v_sub_co_ci_u32_e64 v11, null, v3, v7, vcc_lo
; GFX11-NEXT: v_ashrrev_i32_e32 v12, 31, v9
-; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[8:9], v[0:1]
-; GFX11-NEXT: v_cmp_lt_i64_e64 s0, 0, v[4:5]
+; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[4:5]
+; GFX11-NEXT: v_cmp_gt_i64_e64 s0, 0, v[8:9]
; GFX11-NEXT: v_ashrrev_i32_e32 v4, 31, v11
-; GFX11-NEXT: v_cmp_lt_i64_e64 s1, v[10:11], v[2:3]
-; GFX11-NEXT: v_cmp_lt_i64_e64 s2, 0, v[6:7]
+; GFX11-NEXT: v_cmp_lt_i64_e64 s1, v[2:3], v[6:7]
+; GFX11-NEXT: v_cmp_gt_i64_e64 s2, 0, v[10:11]
; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v12
; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x80000000, v4
-; GFX11-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo
+; GFX11-NEXT: s_xor_b32 vcc_lo, vcc_lo, s0
; GFX11-NEXT: v_dual_cndmask_b32 v0, v8, v12 :: v_dual_cndmask_b32 v1, v9, v1
-; GFX11-NEXT: s_xor_b32 vcc_lo, s2, s1
+; GFX11-NEXT: s_xor_b32 vcc_lo, s1, s2
; GFX11-NEXT: v_dual_cndmask_b32 v2, v10, v4 :: v_dual_cndmask_b32 v3, v11, v3
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
@@ -4976,32 +4956,32 @@ define <2 x i64> @v_ssubsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
define amdgpu_ps <2 x i64> @s_ssubsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v2i64:
; GFX6: ; %bb.0:
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: v_mov_b32_e32 v1, s5
; GFX6-NEXT: s_sub_u32 s8, s0, s4
-; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]
; GFX6-NEXT: s_subb_u32 s9, s1, s5
-; GFX6-NEXT: v_mov_b32_e32 v1, s1
-; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[8:9], v[0:1]
-; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: s_or_b64 s[0:1], vcc, vcc
-; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[4:5], 0
-; GFX6-NEXT: s_cselect_b32 s10, 1, 0
+; GFX6-NEXT: v_cmp_lt_i64_e64 s[0:1], s[8:9], 0
+; GFX6-NEXT: s_cselect_b32 s4, 1, 0
; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
; GFX6-NEXT: s_cselect_b32 s0, 1, 0
-; GFX6-NEXT: s_xor_b32 s4, s0, s10
+; GFX6-NEXT: s_xor_b32 s4, s4, s0
; GFX6-NEXT: s_ashr_i32 s0, s9, 31
; GFX6-NEXT: s_add_i32 s1, s0, 0x80000000
+; GFX6-NEXT: v_mov_b32_e32 v0, s6
; GFX6-NEXT: s_cmp_lg_u32 s4, 0
+; GFX6-NEXT: v_mov_b32_e32 v1, s7
; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9]
; GFX6-NEXT: s_sub_u32 s4, s2, s6
+; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
; GFX6-NEXT: s_subb_u32 s5, s3, s7
-; GFX6-NEXT: v_mov_b32_e32 v1, s3
-; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
; GFX6-NEXT: s_or_b64 s[2:3], vcc, vcc
-; GFX6-NEXT: v_cmp_gt_i64_e64 s[2:3], s[6:7], 0
-; GFX6-NEXT: s_cselect_b32 s8, 1, 0
+; GFX6-NEXT: v_cmp_lt_i64_e64 s[2:3], s[4:5], 0
+; GFX6-NEXT: s_cselect_b32 s6, 1, 0
; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
; GFX6-NEXT: s_cselect_b32 s2, 1, 0
-; GFX6-NEXT: s_xor_b32 s6, s2, s8
+; GFX6-NEXT: s_xor_b32 s6, s6, s2
; GFX6-NEXT: s_ashr_i32 s2, s5, 31
; GFX6-NEXT: s_add_i32 s3, s2, 0x80000000
; GFX6-NEXT: s_cmp_lg_u32 s6, 0
@@ -5010,32 +4990,32 @@ define amdgpu_ps <2 x i64> @s_ssubsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inre
;
; GFX8-LABEL: s_ssubsat_v2i64:
; GFX8: ; %bb.0:
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_sub_u32 s8, s0, s4
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]
; GFX8-NEXT: s_subb_u32 s9, s1, s5
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[8:9], v[0:1]
-; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[4:5], 0
+; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], s[8:9], 0
; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX8-NEXT: s_cselect_b32 s10, 1, 0
+; GFX8-NEXT: s_cselect_b32 s4, 1, 0
; GFX8-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX8-NEXT: s_cselect_b32 s0, 1, 0
-; GFX8-NEXT: s_xor_b32 s4, s0, s10
+; GFX8-NEXT: s_xor_b32 s4, s4, s0
; GFX8-NEXT: s_ashr_i32 s0, s9, 31
; GFX8-NEXT: s_add_i32 s1, s0, 0x80000000
; GFX8-NEXT: s_cmp_lg_u32 s4, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9]
; GFX8-NEXT: s_sub_u32 s4, s2, s6
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s7
+; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
; GFX8-NEXT: s_subb_u32 s5, s3, s7
-; GFX8-NEXT: v_mov_b32_e32 v1, s3
-; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
-; GFX8-NEXT: v_cmp_gt_i64_e64 s[2:3], s[6:7], 0
+; GFX8-NEXT: v_cmp_lt_i64_e64 s[2:3], s[4:5], 0
; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX8-NEXT: s_cselect_b32 s8, 1, 0
+; GFX8-NEXT: s_cselect_b32 s6, 1, 0
; GFX8-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8-NEXT: s_cselect_b32 s2, 1, 0
-; GFX8-NEXT: s_xor_b32 s6, s2, s8
+; GFX8-NEXT: s_xor_b32 s6, s6, s2
; GFX8-NEXT: s_ashr_i32 s2, s5, 31
; GFX8-NEXT: s_add_i32 s3, s2, 0x80000000
; GFX8-NEXT: s_cmp_lg_u32 s6, 0
@@ -5044,32 +5024,32 @@ define amdgpu_ps <2 x i64> @s_ssubsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inre
;
; GFX9-LABEL: s_ssubsat_v2i64:
; GFX9: ; %bb.0:
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: s_sub_u32 s8, s0, s4
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]
; GFX9-NEXT: s_subb_u32 s9, s1, s5
-; GFX9-NEXT: v_mov_b32_e32 v1, s1
-; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[8:9], v[0:1]
-; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[4:5], 0
+; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], s[8:9], 0
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_cselect_b32 s10, 1, 0
+; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX9-NEXT: s_cselect_b32 s0, 1, 0
-; GFX9-NEXT: s_xor_b32 s4, s0, s10
+; GFX9-NEXT: s_xor_b32 s4, s4, s0
; GFX9-NEXT: s_ashr_i32 s0, s9, 31
; GFX9-NEXT: s_add_i32 s1, s0, 0x80000000
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
+; GFX9-NEXT: v_mov_b32_e32 v0, s6
; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9]
; GFX9-NEXT: s_sub_u32 s4, s2, s6
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-NEXT: v_mov_b32_e32 v1, s7
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
; GFX9-NEXT: s_subb_u32 s5, s3, s7
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
-; GFX9-NEXT: v_cmp_gt_i64_e64 s[2:3], s[6:7], 0
+; GFX9-NEXT: v_cmp_lt_i64_e64 s[2:3], s[4:5], 0
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_cselect_b32 s8, 1, 0
+; GFX9-NEXT: s_cselect_b32 s6, 1, 0
; GFX9-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: s_xor_b32 s6, s2, s8
+; GFX9-NEXT: s_xor_b32 s6, s6, s2
; GFX9-NEXT: s_ashr_i32 s2, s5, 31
; GFX9-NEXT: s_add_i32 s3, s2, 0x80000000
; GFX9-NEXT: s_cmp_lg_u32 s6, 0
@@ -5079,28 +5059,28 @@ define amdgpu_ps <2 x i64> @s_ssubsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inre
; GFX10PLUS-LABEL: s_ssubsat_v2i64:
; GFX10PLUS: ; %bb.0:
; GFX10PLUS-NEXT: s_sub_u32 s8, s0, s4
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s0, s[0:1], s[4:5]
; GFX10PLUS-NEXT: s_subb_u32 s9, s1, s5
-; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s0, s[8:9], s[0:1]
-; GFX10PLUS-NEXT: v_cmp_gt_i64_e64 s1, s[4:5], 0
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s1, s[8:9], 0
; GFX10PLUS-NEXT: s_cmp_lg_u32 s0, 0
; GFX10PLUS-NEXT: s_cselect_b32 s4, 1, 0
; GFX10PLUS-NEXT: s_cmp_lg_u32 s1, 0
; GFX10PLUS-NEXT: s_cselect_b32 s1, 1, 0
; GFX10PLUS-NEXT: s_ashr_i32 s0, s9, 31
-; GFX10PLUS-NEXT: s_xor_b32 s4, s1, s4
+; GFX10PLUS-NEXT: s_xor_b32 s4, s4, s1
; GFX10PLUS-NEXT: s_add_i32 s1, s0, 0x80000000
; GFX10PLUS-NEXT: s_cmp_lg_u32 s4, 0
; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9]
; GFX10PLUS-NEXT: s_sub_u32 s4, s2, s6
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s2, s[2:3], s[6:7]
; GFX10PLUS-NEXT: s_subb_u32 s5, s3, s7
-; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s2, s[4:5], s[2:3]
-; GFX10PLUS-NEXT: v_cmp_gt_i64_e64 s3, s[6:7], 0
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s3, s[4:5], 0
; GFX10PLUS-NEXT: s_cmp_lg_u32 s2, 0
; GFX10PLUS-NEXT: s_cselect_b32 s6, 1, 0
; GFX10PLUS-NEXT: s_cmp_lg_u32 s3, 0
; GFX10PLUS-NEXT: s_cselect_b32 s3, 1, 0
; GFX10PLUS-NEXT: s_ashr_i32 s2, s5, 31
-; GFX10PLUS-NEXT: s_xor_b32 s6, s3, s6
+; GFX10PLUS-NEXT: s_xor_b32 s6, s6, s3
; GFX10PLUS-NEXT: s_add_i32 s3, s2, 0x80000000
; GFX10PLUS-NEXT: s_cmp_lg_u32 s6, 0
; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5]
@@ -5113,32 +5093,29 @@ define amdgpu_ps i128 @s_ssubsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX6-LABEL: s_ssubsat_i128:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_sub_u32 s8, s0, s4
-; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: s_subb_u32 s9, s1, s5
-; GFX6-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NEXT: v_mov_b32_e32 v1, s5
; GFX6-NEXT: s_subb_u32 s10, s2, s6
-; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
-; GFX6-NEXT: v_mov_b32_e32 v0, s2
+; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1]
+; GFX6-NEXT: v_mov_b32_e32 v0, s6
; GFX6-NEXT: s_subb_u32 s11, s3, s7
-; GFX6-NEXT: v_mov_b32_e32 v1, s3
+; GFX6-NEXT: v_mov_b32_e32 v1, s7
; GFX6-NEXT: s_or_b64 s[0:1], vcc, vcc
-; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[10:11], v[0:1]
-; GFX6-NEXT: s_cselect_b32 s12, 1, 0
+; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
+; GFX6-NEXT: s_cselect_b32 s4, 1, 0
; GFX6-NEXT: s_or_b64 s[0:1], vcc, vcc
-; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[10:11], v[0:1]
-; GFX6-NEXT: s_cselect_b32 s2, 1, 0
+; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[0:1]
+; GFX6-NEXT: s_cselect_b32 s5, 1, 0
; GFX6-NEXT: s_or_b64 s[0:1], vcc, vcc
-; GFX6-NEXT: v_cmp_gt_u64_e64 s[0:1], s[4:5], 0
-; GFX6-NEXT: s_cselect_b32 s2, s12, s2
+; GFX6-NEXT: v_cmp_lt_i64_e64 s[0:1], s[10:11], 0
+; GFX6-NEXT: s_cselect_b32 s2, s4, s5
; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
-; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[6:7], 0
+; GFX6-NEXT: v_cmp_eq_u64_e64 s[0:1], s[10:11], 0
; GFX6-NEXT: s_cselect_b32 s3, 1, 0
; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
-; GFX6-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], 0
-; GFX6-NEXT: s_cselect_b32 s4, 1, 0
-; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
-; GFX6-NEXT: s_cselect_b32 s0, s3, s4
-; GFX6-NEXT: s_xor_b32 s4, s0, s2
+; GFX6-NEXT: s_cselect_b32 s0, 0, s3
+; GFX6-NEXT: s_xor_b32 s4, s2, s0
; GFX6-NEXT: s_ashr_i32 s0, s11, 31
; GFX6-NEXT: s_add_i32 s3, s0, 0x80000000
; GFX6-NEXT: s_and_b32 s4, s4, 1
@@ -5152,30 +5129,27 @@ define amdgpu_ps i128 @s_ssubsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX8-LABEL: s_ssubsat_i128:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_sub_u32 s8, s0, s4
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_subb_u32 s9, s1, s5
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_subb_u32 s10, s2, s6
-; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: s_subb_u32 s11, s3, s7
-; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: v_mov_b32_e32 v1, s7
; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[10:11], v[0:1]
-; GFX8-NEXT: s_cselect_b32 s12, 1, 0
+; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
+; GFX8-NEXT: s_cselect_b32 s4, 1, 0
; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX8-NEXT: v_cmp_gt_u64_e64 s[0:1], s[4:5], 0
-; GFX8-NEXT: s_cselect_b32 s13, 1, 0
-; GFX8-NEXT: s_cmp_eq_u64 s[10:11], s[2:3]
-; GFX8-NEXT: s_cselect_b32 s2, s12, s13
-; GFX8-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[6:7], 0
-; GFX8-NEXT: s_cselect_b32 s3, 1, 0
+; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], s[10:11], 0
+; GFX8-NEXT: s_cselect_b32 s5, 1, 0
+; GFX8-NEXT: s_cmp_eq_u64 s[2:3], s[6:7]
+; GFX8-NEXT: s_cselect_b32 s2, s4, s5
; GFX8-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX8-NEXT: s_cselect_b32 s0, 1, 0
-; GFX8-NEXT: s_cmp_eq_u64 s[6:7], 0
-; GFX8-NEXT: s_cselect_b32 s0, s3, s0
-; GFX8-NEXT: s_xor_b32 s4, s0, s2
+; GFX8-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX8-NEXT: s_cselect_b32 s0, 0, s0
+; GFX8-NEXT: s_xor_b32 s4, s2, s0
; GFX8-NEXT: s_ashr_i32 s0, s11, 31
; GFX8-NEXT: s_add_i32 s3, s0, 0x80000000
; GFX8-NEXT: s_and_b32 s4, s4, 1
@@ -5189,30 +5163,27 @@ define amdgpu_ps i128 @s_ssubsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX9-LABEL: s_ssubsat_i128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_sub_u32 s8, s0, s4
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: s_subb_u32 s9, s1, s5
-; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: s_subb_u32 s10, s2, s6
-; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1]
+; GFX9-NEXT: v_mov_b32_e32 v0, s6
; GFX9-NEXT: s_subb_u32 s11, s3, s7
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-NEXT: v_mov_b32_e32 v1, s7
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[10:11], v[0:1]
-; GFX9-NEXT: s_cselect_b32 s12, 1, 0
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
+; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: v_cmp_gt_u64_e64 s[0:1], s[4:5], 0
-; GFX9-NEXT: s_cselect_b32 s13, 1, 0
-; GFX9-NEXT: s_cmp_eq_u64 s[10:11], s[2:3]
-; GFX9-NEXT: s_cselect_b32 s2, s12, s13
-; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[6:7], 0
-; GFX9-NEXT: s_cselect_b32 s3, 1, 0
+; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], s[10:11], 0
+; GFX9-NEXT: s_cselect_b32 s5, 1, 0
+; GFX9-NEXT: s_cmp_eq_u64 s[2:3], s[6:7]
+; GFX9-NEXT: s_cselect_b32 s2, s4, s5
; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX9-NEXT: s_cselect_b32 s0, 1, 0
-; GFX9-NEXT: s_cmp_eq_u64 s[6:7], 0
-; GFX9-NEXT: s_cselect_b32 s0, s3, s0
-; GFX9-NEXT: s_xor_b32 s4, s0, s2
+; GFX9-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX9-NEXT: s_cselect_b32 s0, 0, s0
+; GFX9-NEXT: s_xor_b32 s4, s2, s0
; GFX9-NEXT: s_ashr_i32 s0, s11, 31
; GFX9-NEXT: s_add_i32 s3, s0, 0x80000000
; GFX9-NEXT: s_and_b32 s4, s4, 1
@@ -5225,35 +5196,32 @@ define amdgpu_ps i128 @s_ssubsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
;
; GFX10PLUS-LABEL: s_ssubsat_i128:
; GFX10PLUS: ; %bb.0:
-; GFX10PLUS-NEXT: s_sub_u32 s8, s0, s4
-; GFX10PLUS-NEXT: s_subb_u32 s9, s1, s5
-; GFX10PLUS-NEXT: s_subb_u32 s10, s2, s6
-; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s0, s[8:9], s[0:1]
-; GFX10PLUS-NEXT: s_subb_u32 s11, s3, s7
-; GFX10PLUS-NEXT: v_cmp_gt_u64_e64 s4, s[4:5], 0
-; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s1, s[10:11], s[2:3]
-; GFX10PLUS-NEXT: s_cmp_lg_u32 s0, 0
-; GFX10PLUS-NEXT: s_cselect_b32 s0, 1, 0
-; GFX10PLUS-NEXT: s_cmp_lg_u32 s1, 0
-; GFX10PLUS-NEXT: s_cselect_b32 s1, 1, 0
-; GFX10PLUS-NEXT: s_cmp_eq_u64 s[10:11], s[2:3]
-; GFX10PLUS-NEXT: v_cmp_gt_i64_e64 s2, s[6:7], 0
-; GFX10PLUS-NEXT: s_cselect_b32 s1, s0, s1
-; GFX10PLUS-NEXT: s_cmp_lg_u32 s4, 0
-; GFX10PLUS-NEXT: s_cselect_b32 s0, 1, 0
-; GFX10PLUS-NEXT: s_cmp_lg_u32 s2, 0
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s8, s[0:1], s[4:5]
+; GFX10PLUS-NEXT: s_sub_u32 s0, s0, s4
+; GFX10PLUS-NEXT: s_subb_u32 s1, s1, s5
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s9, s[2:3], s[6:7]
+; GFX10PLUS-NEXT: s_subb_u32 s4, s2, s6
+; GFX10PLUS-NEXT: s_subb_u32 s5, s3, s7
+; GFX10PLUS-NEXT: s_cmp_lg_u32 s8, 0
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s10, s[4:5], 0
+; GFX10PLUS-NEXT: s_cselect_b32 s8, 1, 0
+; GFX10PLUS-NEXT: s_cmp_lg_u32 s9, 0
+; GFX10PLUS-NEXT: s_cselect_b32 s9, 1, 0
+; GFX10PLUS-NEXT: s_cmp_eq_u64 s[2:3], s[6:7]
+; GFX10PLUS-NEXT: s_cselect_b32 s3, s8, s9
+; GFX10PLUS-NEXT: s_cmp_lg_u32 s10, 0
; GFX10PLUS-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10PLUS-NEXT: s_cmp_eq_u64 s[6:7], 0
-; GFX10PLUS-NEXT: s_cselect_b32 s2, s0, s2
-; GFX10PLUS-NEXT: s_ashr_i32 s0, s11, 31
-; GFX10PLUS-NEXT: s_xor_b32 s2, s2, s1
-; GFX10PLUS-NEXT: s_add_i32 s3, s0, 0x80000000
-; GFX10PLUS-NEXT: s_and_b32 s4, s2, 1
-; GFX10PLUS-NEXT: s_mov_b32 s1, s0
-; GFX10PLUS-NEXT: s_mov_b32 s2, s0
-; GFX10PLUS-NEXT: s_cmp_lg_u32 s4, 0
-; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9]
-; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], s[2:3], s[10:11]
+; GFX10PLUS-NEXT: s_cmp_eq_u64 s[4:5], 0
+; GFX10PLUS-NEXT: s_cselect_b32 s6, 0, s2
+; GFX10PLUS-NEXT: s_ashr_i32 s2, s5, 31
+; GFX10PLUS-NEXT: s_xor_b32 s6, s3, s6
+; GFX10PLUS-NEXT: s_add_i32 s7, s2, 0x80000000
+; GFX10PLUS-NEXT: s_and_b32 s8, s6, 1
+; GFX10PLUS-NEXT: s_mov_b32 s3, s2
+; GFX10PLUS-NEXT: s_mov_b32 s6, s2
+; GFX10PLUS-NEXT: s_cmp_lg_u32 s8, 0
+; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1]
+; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], s[6:7], s[4:5]
; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call i128 @llvm.ssub.sat.i128(i128 %lhs, i128 %rhs)
ret i128 %result
@@ -5262,150 +5230,140 @@ define amdgpu_ps i128 @s_ssubsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
define amdgpu_ps <4 x float> @ssubsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
; GFX6-LABEL: ssubsat_i128_sv:
; GFX6: ; %bb.0:
-; GFX6-NEXT: v_mov_b32_e32 v5, s1
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s0, v0
-; GFX6-NEXT: v_subb_u32_e32 v5, vcc, v5, v1, vcc
-; GFX6-NEXT: v_mov_b32_e32 v6, s2
-; GFX6-NEXT: v_mov_b32_e32 v7, s3
-; GFX6-NEXT: v_subb_u32_e32 v6, vcc, v6, v2, vcc
-; GFX6-NEXT: v_subb_u32_e32 v7, vcc, v7, v3, vcc
-; GFX6-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[4:5]
-; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; GFX6-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[6:7]
-; GFX6-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[6:7]
-; GFX6-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc
-; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[0:1]
+; GFX6-NEXT: v_mov_b32_e32 v4, s1
+; GFX6-NEXT: v_sub_i32_e32 v6, vcc, s0, v0
+; GFX6-NEXT: v_subb_u32_e32 v7, vcc, v4, v1, vcc
+; GFX6-NEXT: v_mov_b32_e32 v4, s2
+; GFX6-NEXT: v_mov_b32_e32 v5, s3
+; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v4, v2, vcc
+; GFX6-NEXT: v_subb_u32_e32 v5, vcc, v5, v3, vcc
+; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1]
; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[2:3]
+; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[2:3]
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
-; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v7
+; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[2:3]
+; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v5
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GFX6-NEXT: v_xor_b32_e32 v0, v0, v8
+; GFX6-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX6-NEXT: v_xor_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0x80000000, v2
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v7, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: ssubsat_i128_sv:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_mov_b32_e32 v5, s1
-; GFX8-NEXT: v_sub_u32_e32 v4, vcc, s0, v0
-; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v5, v1, vcc
-; GFX8-NEXT: v_mov_b32_e32 v6, s2
-; GFX8-NEXT: v_mov_b32_e32 v7, s3
-; GFX8-NEXT: v_subb_u32_e32 v6, vcc, v6, v2, vcc
-; GFX8-NEXT: v_subb_u32_e32 v7, vcc, v7, v3, vcc
-; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[6:7]
-; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[6:7]
-; GFX8-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc
-; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v4, s1
+; GFX8-NEXT: v_sub_u32_e32 v6, vcc, s0, v0
+; GFX8-NEXT: v_subb_u32_e32 v7, vcc, v4, v1, vcc
+; GFX8-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NEXT: v_subb_u32_e32 v4, vcc, v4, v2, vcc
+; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v5, v3, vcc
+; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[2:3]
+; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
-; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v7
+; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[2:3]
+; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v5
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GFX8-NEXT: v_xor_b32_e32 v0, v0, v8
+; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX8-NEXT: v_xor_b32_e32 v0, v0, v1
; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0x80000000, v2
; GFX8-NEXT: v_cmp_ne_u16_e32 vcc, 0, v0
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v2, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: ssubsat_i128_sv:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_mov_b32_e32 v5, s1
-; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, s0, v0
-; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v5, v1, vcc
-; GFX9-NEXT: v_mov_b32_e32 v6, s2
-; GFX9-NEXT: v_mov_b32_e32 v7, s3
-; GFX9-NEXT: v_subb_co_u32_e32 v6, vcc, v6, v2, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, v7, v3, vcc
-; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[6:7]
-; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[6:7]
-; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc
-; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[0:1]
+; GFX9-NEXT: v_mov_b32_e32 v4, s1
+; GFX9-NEXT: v_sub_co_u32_e32 v6, vcc, s0, v0
+; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, v4, v1, vcc
+; GFX9-NEXT: v_mov_b32_e32 v4, s2
+; GFX9-NEXT: v_mov_b32_e32 v5, s3
+; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, v4, v2, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v5, v3, vcc
+; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[2:3]
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
-; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v7
+; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[2:3]
+; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v5
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GFX9-NEXT: v_xor_b32_e32 v0, v0, v8
+; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[4:5]
; GFX9-NEXT: v_add_u32_e32 v3, 0x80000000, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1
; GFX9-NEXT: v_cmp_ne_u16_e32 vcc, 0, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: ssubsat_i128_sv:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, s0, v0
-; GFX10-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT: v_sub_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
-; GFX10-NEXT: v_sub_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
-; GFX10-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[4:5]
-; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[6:7]
-; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, 0, v[0:1]
+; GFX10-NEXT: v_sub_co_u32 v6, vcc_lo, s0, v0
+; GFX10-NEXT: v_sub_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo
+; GFX10-NEXT: v_sub_co_ci_u32_e32 v4, vcc_lo, s2, v2, vcc_lo
+; GFX10-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
+; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, s[0:1], v[0:1]
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[2:3]
+; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, s[2:3], v[2:3]
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[6:7]
-; GFX10-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
-; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v7
+; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[4:5]
+; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]
+; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v5
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
; GFX10-NEXT: v_add_nc_u32_e32 v3, 0x80000000, v2
-; GFX10-NEXT: v_xor_b32_e32 v0, v0, v8
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v8, 0, vcc_lo
+; GFX10-NEXT: v_xor_b32_e32 v0, v0, v1
; GFX10-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc_lo
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: ssubsat_i128_sv:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_sub_co_u32 v4, vcc_lo, s0, v0
-; GFX11-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
-; GFX11-NEXT: v_sub_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
-; GFX11-NEXT: v_sub_co_ci_u32_e64 v7, null, s3, v3, vcc_lo
-; GFX11-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[4:5]
-; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; GFX11-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[6:7]
-; GFX11-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
-; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, 0, v[0:1]
+; GFX11-NEXT: v_sub_co_u32 v6, vcc_lo, s0, v0
+; GFX11-NEXT: v_sub_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo
+; GFX11-NEXT: v_sub_co_ci_u32_e32 v4, vcc_lo, s2, v2, vcc_lo
+; GFX11-NEXT: v_sub_co_ci_u32_e64 v5, null, s3, v3, vcc_lo
+; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, s[0:1], v[0:1]
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[2:3]
+; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, s[2:3], v[2:3]
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[6:7]
-; GFX11-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
-; GFX11-NEXT: v_ashrrev_i32_e32 v2, 31, v7
+; GFX11-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[4:5]
+; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]
+; GFX11-NEXT: v_ashrrev_i32_e32 v2, 31, v5
; GFX11-NEXT: v_dual_cndmask_b32 v0, v1, v0 :: v_dual_add_nc_u32 v3, 0x80000000, v2
-; GFX11-NEXT: v_xor_b32_e32 v0, v0, v8
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v8, 0, vcc_lo
+; GFX11-NEXT: v_xor_b32_e32 v0, v0, v1
; GFX11-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v0
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc_lo
-; GFX11-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v3
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v6, v2 :: v_dual_cndmask_b32 v3, v5, v3
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v7, v2, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
; GFX11-NEXT: ; return to shader part epilog
%result = call i128 @llvm.ssub.sat.i128(i128 %lhs, i128 %rhs)
%cast = bitcast i128 %result to <4 x float>
@@ -5415,161 +5373,140 @@ define amdgpu_ps <4 x float> @ssubsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
define amdgpu_ps <4 x float> @ssubsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
; GFX6-LABEL: ssubsat_i128_vs:
; GFX6: ; %bb.0:
-; GFX6-NEXT: v_mov_b32_e32 v5, s1
-; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s0, v0
-; GFX6-NEXT: v_subb_u32_e32 v5, vcc, v1, v5, vcc
-; GFX6-NEXT: v_mov_b32_e32 v6, s2
-; GFX6-NEXT: v_cmp_gt_u64_e64 s[0:1], s[0:1], 0
-; GFX6-NEXT: v_mov_b32_e32 v7, s3
-; GFX6-NEXT: v_subb_u32_e32 v6, vcc, v2, v6, vcc
-; GFX6-NEXT: v_subb_u32_e32 v7, vcc, v3, v7, vcc
-; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
-; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[0:1]
-; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 0
+; GFX6-NEXT: v_mov_b32_e32 v4, s1
+; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, s0, v0
+; GFX6-NEXT: v_subb_u32_e32 v7, vcc, v1, v4, vcc
+; GFX6-NEXT: v_mov_b32_e32 v4, s2
+; GFX6-NEXT: v_mov_b32_e32 v5, s3
+; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v2, v4, vcc
+; GFX6-NEXT: v_subb_u32_e32 v5, vcc, v3, v5, vcc
+; GFX6-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[0:1]
; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
-; GFX6-NEXT: s_cselect_b32 s4, 1, 0
-; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
-; GFX6-NEXT: v_cmp_eq_u64_e64 s[0:1], s[2:3], 0
+; GFX6-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[6:7], v[2:3]
-; GFX6-NEXT: s_cselect_b32 s5, 1, 0
-; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
+; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[2:3]
+; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v5
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GFX6-NEXT: s_cselect_b32 s0, s4, s5
-; GFX6-NEXT: v_xor_b32_e32 v0, s0, v0
-; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v7
+; GFX6-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX6-NEXT: v_xor_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0x80000000, v2
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v7, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: ssubsat_i128_vs:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_mov_b32_e32 v5, s1
-; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s0, v0
-; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v1, v5, vcc
-; GFX8-NEXT: v_mov_b32_e32 v6, s2
-; GFX8-NEXT: v_mov_b32_e32 v7, s3
-; GFX8-NEXT: v_subb_u32_e32 v6, vcc, v2, v6, vcc
-; GFX8-NEXT: v_subb_u32_e32 v7, vcc, v3, v7, vcc
-; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[0:1]
-; GFX8-NEXT: v_cmp_gt_u64_e64 s[0:1], s[0:1], 0
+; GFX8-NEXT: v_mov_b32_e32 v4, s1
+; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, s0, v0
+; GFX8-NEXT: v_subb_u32_e32 v7, vcc, v1, v4, vcc
+; GFX8-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NEXT: v_subb_u32_e32 v4, vcc, v2, v4, vcc
+; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v3, v5, vcc
+; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
-; GFX8-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 0
+; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[6:7], v[2:3]
-; GFX8-NEXT: s_cselect_b32 s4, 1, 0
-; GFX8-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX8-NEXT: s_cselect_b32 s0, 1, 0
-; GFX8-NEXT: s_cmp_eq_u64 s[2:3], 0
+; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[2:3]
+; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v5
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GFX8-NEXT: s_cselect_b32 s0, s4, s0
-; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v7
-; GFX8-NEXT: v_xor_b32_e32 v0, s0, v0
+; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX8-NEXT: v_xor_b32_e32 v0, v0, v1
; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0x80000000, v2
; GFX8-NEXT: v_cmp_ne_u16_e32 vcc, 0, v0
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v2, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: ssubsat_i128_vs:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_mov_b32_e32 v5, s1
-; GFX9-NEXT: v_subrev_co_u32_e32 v4, vcc, s0, v0
-; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v1, v5, vcc
-; GFX9-NEXT: v_mov_b32_e32 v6, s2
-; GFX9-NEXT: v_mov_b32_e32 v7, s3
-; GFX9-NEXT: v_subb_co_u32_e32 v6, vcc, v2, v6, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, v3, v7, vcc
-; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[0:1]
-; GFX9-NEXT: v_cmp_gt_u64_e64 s[0:1], s[0:1], 0
+; GFX9-NEXT: v_mov_b32_e32 v4, s1
+; GFX9-NEXT: v_subrev_co_u32_e32 v6, vcc, s0, v0
+; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, v1, v4, vcc
+; GFX9-NEXT: v_mov_b32_e32 v4, s2
+; GFX9-NEXT: v_mov_b32_e32 v5, s3
+; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, v2, v4, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v3, v5, vcc
+; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
-; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 0
+; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[6:7], v[2:3]
-; GFX9-NEXT: s_cselect_b32 s4, 1, 0
-; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX9-NEXT: s_cselect_b32 s0, 1, 0
-; GFX9-NEXT: s_cmp_eq_u64 s[2:3], 0
+; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[2:3]
+; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v5
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GFX9-NEXT: s_cselect_b32 s0, s4, s0
-; GFX9-NEXT: v_xor_b32_e32 v0, s0, v0
-; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v7
+; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[4:5]
; GFX9-NEXT: v_add_u32_e32 v3, 0x80000000, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1
; GFX9-NEXT: v_cmp_ne_u16_e32 vcc, 0, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: ssubsat_i128_vs:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v0, s0
-; GFX10-NEXT: v_subrev_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
-; GFX10-NEXT: v_subrev_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
-; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
-; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[0:1]
-; GFX10-NEXT: v_cmp_gt_u64_e64 s0, s[0:1], 0
-; GFX10-NEXT: v_cmp_gt_i64_e64 s1, s[2:3], 0
+; GFX10-NEXT: v_sub_co_u32 v6, vcc_lo, v0, s0
+; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo
+; GFX10-NEXT: v_subrev_co_ci_u32_e32 v4, vcc_lo, s2, v2, vcc_lo
+; GFX10-NEXT: v_subrev_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
+; GFX10-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[2:3]
-; GFX10-NEXT: s_cmp_lg_u32 s0, 0
-; GFX10-NEXT: s_cselect_b32 s0, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s1, 0
+; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[2:3]
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
-; GFX10-NEXT: s_cselect_b32 s1, 1, 0
-; GFX10-NEXT: s_cmp_eq_u64 s[2:3], 0
-; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v7
-; GFX10-NEXT: s_cselect_b32 s0, s0, s1
+; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[4:5]
+; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]
+; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v5
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
; GFX10-NEXT: v_add_nc_u32_e32 v3, 0x80000000, v2
-; GFX10-NEXT: v_xor_b32_e32 v0, s0, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v8, 0, vcc_lo
+; GFX10-NEXT: v_xor_b32_e32 v0, v0, v1
; GFX10-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc_lo
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: ssubsat_i128_vs:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_sub_co_u32 v4, vcc_lo, v0, s0
-; GFX11-NEXT: v_subrev_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
-; GFX11-NEXT: v_subrev_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
-; GFX11-NEXT: v_subrev_co_ci_u32_e64 v7, null, s3, v3, vcc_lo
-; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[0:1]
-; GFX11-NEXT: v_cmp_gt_u64_e64 s0, s[0:1], 0
-; GFX11-NEXT: v_cmp_gt_i64_e64 s1, s[2:3], 0
+; GFX11-NEXT: v_sub_co_u32 v6, vcc_lo, v0, s0
+; GFX11-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo
+; GFX11-NEXT: v_subrev_co_ci_u32_e32 v4, vcc_lo, s2, v2, vcc_lo
+; GFX11-NEXT: v_subrev_co_ci_u32_e64 v5, null, s3, v3, vcc_lo
+; GFX11-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[2:3]
-; GFX11-NEXT: s_cmp_lg_u32 s0, 0
-; GFX11-NEXT: s_cselect_b32 s0, 1, 0
-; GFX11-NEXT: s_cmp_lg_u32 s1, 0
+; GFX11-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[2:3]
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
-; GFX11-NEXT: v_ashrrev_i32_e32 v2, 31, v7
-; GFX11-NEXT: s_cselect_b32 s1, 1, 0
-; GFX11-NEXT: s_cmp_eq_u64 s[2:3], 0
-; GFX11-NEXT: s_cselect_b32 s0, s0, s1
+; GFX11-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[4:5]
+; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]
+; GFX11-NEXT: v_ashrrev_i32_e32 v2, 31, v5
; GFX11-NEXT: v_dual_cndmask_b32 v0, v1, v0 :: v_dual_add_nc_u32 v3, 0x80000000, v2
-; GFX11-NEXT: v_xor_b32_e32 v0, s0, v0
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v8, 0, vcc_lo
+; GFX11-NEXT: v_xor_b32_e32 v0, v0, v1
; GFX11-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v0
-; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v2 :: v_dual_cndmask_b32 v3, v7, v3
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v6, v2 :: v_dual_cndmask_b32 v3, v5, v3
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v7, v2, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
; GFX11-NEXT: ; return to shader part epilog
%result = call i128 @llvm.ssub.sat.i128(i128 %lhs, i128 %rhs)
%cast = bitcast i128 %result to <4 x float>
@@ -5580,268 +5517,249 @@ define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX6-LABEL: v_ssubsat_v2i128:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_sub_i32_e32 v16, vcc, v0, v8
-; GFX6-NEXT: v_subb_u32_e32 v17, vcc, v1, v9, vcc
-; GFX6-NEXT: v_subb_u32_e32 v18, vcc, v2, v10, vcc
-; GFX6-NEXT: v_subb_u32_e32 v19, vcc, v3, v11, vcc
-; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[0:1]
+; GFX6-NEXT: v_sub_i32_e32 v18, vcc, v0, v8
+; GFX6-NEXT: v_subb_u32_e32 v19, vcc, v1, v9, vcc
+; GFX6-NEXT: v_subb_u32_e32 v16, vcc, v2, v10, vcc
+; GFX6-NEXT: v_subb_u32_e32 v17, vcc, v3, v11, vcc
+; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[8:9]
; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[18:19], v[2:3]
+; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[10:11]
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[18:19], v[2:3]
+; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[10:11]
+; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v17
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[8:9]
+; GFX6-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[16:17]
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[10:11]
-; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0
-; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v19
+; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[16:17]
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX6-NEXT: v_xor_b32_e32 v0, v0, v1
; GFX6-NEXT: v_bfrev_b32_e32 v1, 1
; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v2, v1
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v16, v2, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v17, v2, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
-; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v4, v12
-; GFX6-NEXT: v_subb_u32_e32 v9, vcc, v5, v13, vcc
-; GFX6-NEXT: v_subb_u32_e32 v10, vcc, v6, v14, vcc
-; GFX6-NEXT: v_subb_u32_e32 v11, vcc, v7, v15, vcc
-; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v18, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v19, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v16, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v17, v3, vcc
+; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v4, v12
+; GFX6-NEXT: v_subb_u32_e32 v11, vcc, v5, v13, vcc
+; GFX6-NEXT: v_subb_u32_e32 v8, vcc, v6, v14, vcc
+; GFX6-NEXT: v_subb_u32_e32 v9, vcc, v7, v15, vcc
+; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[12:13]
; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7]
+; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[14:15]
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7]
+; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[6:7], v[14:15]
+; GFX6-NEXT: v_ashrrev_i32_e32 v6, 31, v9
; GFX6-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
-; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13]
+; GFX6-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[8:9]
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[14:15]
-; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]
-; GFX6-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
-; GFX6-NEXT: v_xor_b32_e32 v4, v5, v4
-; GFX6-NEXT: v_ashrrev_i32_e32 v6, 31, v11
+; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9]
+; GFX6-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
+; GFX6-NEXT: v_xor_b32_e32 v4, v4, v5
; GFX6-NEXT: v_and_b32_e32 v4, 1, v4
; GFX6-NEXT: v_add_i32_e32 v7, vcc, 0x80000000, v6
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
-; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v5, v9, v6, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v10, v6, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v5, v11, v6, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_ssubsat_v2i128:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_sub_u32_e32 v16, vcc, v0, v8
-; GFX8-NEXT: v_subb_u32_e32 v17, vcc, v1, v9, vcc
-; GFX8-NEXT: v_subb_u32_e32 v18, vcc, v2, v10, vcc
-; GFX8-NEXT: v_subb_u32_e32 v19, vcc, v3, v11, vcc
-; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[0:1]
+; GFX8-NEXT: v_sub_u32_e32 v18, vcc, v0, v8
+; GFX8-NEXT: v_subb_u32_e32 v19, vcc, v1, v9, vcc
+; GFX8-NEXT: v_subb_u32_e32 v16, vcc, v2, v10, vcc
+; GFX8-NEXT: v_subb_u32_e32 v17, vcc, v3, v11, vcc
+; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[8:9]
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[18:19], v[2:3]
+; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[10:11]
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[18:19], v[2:3]
+; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[10:11]
+; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v17
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[8:9]
+; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[16:17]
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[10:11]
-; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0
-; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v19
+; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[16:17]
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX8-NEXT: v_xor_b32_e32 v0, v0, v1
; GFX8-NEXT: v_bfrev_b32_e32 v1, 1
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v2, v1
; GFX8-NEXT: v_cmp_ne_u16_e32 vcc, 0, v0
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v16, v2, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v2, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
-; GFX8-NEXT: v_sub_u32_e32 v8, vcc, v4, v12
-; GFX8-NEXT: v_subb_u32_e32 v9, vcc, v5, v13, vcc
-; GFX8-NEXT: v_subb_u32_e32 v10, vcc, v6, v14, vcc
-; GFX8-NEXT: v_subb_u32_e32 v11, vcc, v7, v15, vcc
-; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v18, v2, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v19, v2, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v16, v2, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v17, v3, vcc
+; GFX8-NEXT: v_sub_u32_e32 v10, vcc, v4, v12
+; GFX8-NEXT: v_subb_u32_e32 v11, vcc, v5, v13, vcc
+; GFX8-NEXT: v_subb_u32_e32 v8, vcc, v6, v14, vcc
+; GFX8-NEXT: v_subb_u32_e32 v9, vcc, v7, v15, vcc
+; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[12:13]
; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7]
+; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[14:15]
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7]
+; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[6:7], v[14:15]
+; GFX8-NEXT: v_ashrrev_i32_e32 v6, 31, v9
; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
-; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13]
+; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[8:9]
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[14:15]
-; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]
-; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
-; GFX8-NEXT: v_ashrrev_i32_e32 v6, 31, v11
-; GFX8-NEXT: v_xor_b32_e32 v4, v5, v4
+; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
+; GFX8-NEXT: v_xor_b32_e32 v4, v4, v5
; GFX8-NEXT: v_add_u32_e32 v7, vcc, 0x80000000, v6
; GFX8-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v6, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v10, v6, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v11, v6, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ssubsat_v2i128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_sub_co_u32_e32 v16, vcc, v0, v8
-; GFX9-NEXT: v_subb_co_u32_e32 v17, vcc, v1, v9, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v18, vcc, v2, v10, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v19, vcc, v3, v11, vcc
-; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[0:1]
+; GFX9-NEXT: v_sub_co_u32_e32 v18, vcc, v0, v8
+; GFX9-NEXT: v_subb_co_u32_e32 v19, vcc, v1, v9, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v16, vcc, v2, v10, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v17, vcc, v3, v11, vcc
+; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[8:9]
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[18:19], v[2:3]
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[10:11]
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[18:19], v[2:3]
+; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[2:3], v[10:11]
+; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v17
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[8:9]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[10:11]
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0
-; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v19
+; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[16:17]
; GFX9-NEXT: v_add_u32_e32 v3, 0x80000000, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[16:17]
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1
; GFX9-NEXT: v_cmp_ne_u16_e32 vcc, 0, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v16, v2, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v2, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
-; GFX9-NEXT: v_sub_co_u32_e32 v8, vcc, v4, v12
-; GFX9-NEXT: v_subb_co_u32_e32 v9, vcc, v5, v13, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v10, vcc, v6, v14, vcc
-; GFX9-NEXT: v_subb_co_u32_e32 v11, vcc, v7, v15, vcc
-; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v18, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v19, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v16, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v17, v3, vcc
+; GFX9-NEXT: v_sub_co_u32_e32 v10, vcc, v4, v12
+; GFX9-NEXT: v_subb_co_u32_e32 v11, vcc, v5, v13, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v8, vcc, v6, v14, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v9, vcc, v7, v15, vcc
+; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[12:13]
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7]
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[14:15]
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7]
+; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[6:7], v[14:15]
+; GFX9-NEXT: v_ashrrev_i32_e32 v6, 31, v9
; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
-; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13]
-; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[14:15]
-; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
-; GFX9-NEXT: v_xor_b32_e32 v4, v5, v4
-; GFX9-NEXT: v_ashrrev_i32_e32 v6, 31, v11
+; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[8:9]
; GFX9-NEXT: v_add_u32_e32 v7, 0x80000000, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9]
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
+; GFX9-NEXT: v_xor_b32_e32 v4, v4, v5
; GFX9-NEXT: v_cmp_ne_u16_e32 vcc, 0, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v6, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v10, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v11, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_v2i128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_sub_co_u32 v16, vcc_lo, v0, v8
-; GFX10-NEXT: v_sub_co_ci_u32_e32 v17, vcc_lo, v1, v9, vcc_lo
-; GFX10-NEXT: v_sub_co_ci_u32_e32 v18, vcc_lo, v2, v10, vcc_lo
-; GFX10-NEXT: v_sub_co_ci_u32_e32 v19, vcc_lo, v3, v11, vcc_lo
-; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[16:17], v[0:1]
+; GFX10-NEXT: v_sub_co_u32 v18, vcc_lo, v0, v8
+; GFX10-NEXT: v_sub_co_ci_u32_e32 v19, vcc_lo, v1, v9, vcc_lo
+; GFX10-NEXT: v_sub_co_ci_u32_e32 v16, vcc_lo, v2, v10, vcc_lo
+; GFX10-NEXT: v_sub_co_ci_u32_e32 v17, vcc_lo, v3, v11, vcc_lo
+; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[8:9]
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[18:19], v[2:3]
+; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[10:11]
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[2:3]
+; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[16:17]
+; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[10:11]
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, 0, v[8:9]
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[10:11]
+; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[16:17]
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v8, 0, vcc_lo
+; GFX10-NEXT: v_sub_co_u32 v10, vcc_lo, v4, v12
+; GFX10-NEXT: v_sub_co_ci_u32_e32 v11, vcc_lo, v5, v13, vcc_lo
+; GFX10-NEXT: v_sub_co_ci_u32_e32 v8, vcc_lo, v6, v14, vcc_lo
+; GFX10-NEXT: v_sub_co_ci_u32_e32 v9, vcc_lo, v7, v15, vcc_lo
+; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX10-NEXT: v_xor_b32_e32 v0, v0, v1
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX10-NEXT: v_sub_co_u32 v8, vcc_lo, v4, v12
-; GFX10-NEXT: v_sub_co_ci_u32_e32 v9, vcc_lo, v5, v13, vcc_lo
-; GFX10-NEXT: v_sub_co_ci_u32_e32 v20, vcc_lo, v6, v14, vcc_lo
-; GFX10-NEXT: v_sub_co_ci_u32_e32 v21, vcc_lo, v7, v15, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
-; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[8:9], v[4:5]
-; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[20:21], v[6:7]
+; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[14:15]
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, 0, v[12:13]
+; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[8:9]
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[14:15]
-; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[20:21], v[6:7]
-; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v21
+; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v9
; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15]
-; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v19
+; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9]
+; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v17
; GFX10-NEXT: v_add_nc_u32_e32 v7, 0x80000000, v6
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
; GFX10-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v0
; GFX10-NEXT: v_add_nc_u32_e32 v4, 0x80000000, v3
-; GFX10-NEXT: v_xor_b32_e32 v2, v2, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v16, v3, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v17, v3, vcc_lo
+; GFX10-NEXT: v_xor_b32_e32 v2, v1, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v18, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v19, v3, vcc_lo
; GFX10-NEXT: v_cmp_ne_u16_e64 s4, 0, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v18, v3, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v3, v19, v4, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, v6, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v9, v6, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v20, v6, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v21, v7, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v16, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v17, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v10, v6, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v11, v6, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v8, v6, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v9, v7, s4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_ssubsat_v2i128:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_sub_co_u32 v16, vcc_lo, v0, v8
-; GFX11-NEXT: v_sub_co_ci_u32_e32 v17, vcc_lo, v1, v9, vcc_lo
-; GFX11-NEXT: v_sub_co_ci_u32_e32 v18, vcc_lo, v2, v10, vcc_lo
-; GFX11-NEXT: v_sub_co_ci_u32_e64 v19, null, v3, v11, vcc_lo
-; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[16:17], v[0:1]
+; GFX11-NEXT: v_sub_co_u32 v18, vcc_lo, v0, v8
+; GFX11-NEXT: v_sub_co_ci_u32_e32 v19, vcc_lo, v1, v9, vcc_lo
+; GFX11-NEXT: v_sub_co_ci_u32_e32 v16, vcc_lo, v2, v10, vcc_lo
+; GFX11-NEXT: v_sub_co_ci_u32_e64 v17, null, v3, v11, vcc_lo
+; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[8:9]
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[18:19], v[2:3]
+; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[10:11]
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[2:3]
+; GFX11-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[16:17]
+; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[10:11]
; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, 0, v[8:9]
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[10:11]
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX11-NEXT: v_sub_co_u32 v8, vcc_lo, v4, v12
-; GFX11-NEXT: v_sub_co_ci_u32_e32 v9, vcc_lo, v5, v13, vcc_lo
-; GFX11-NEXT: v_sub_co_ci_u32_e32 v20, vcc_lo, v6, v14, vcc_lo
-; GFX11-NEXT: v_sub_co_ci_u32_e64 v21, null, v7, v15, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
-; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[8:9], v[4:5]
-; GFX11-NEXT: v_xor_b32_e32 v0, v1, v0
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[16:17]
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v8, 0, vcc_lo
+; GFX11-NEXT: v_sub_co_u32 v10, vcc_lo, v4, v12
+; GFX11-NEXT: v_sub_co_ci_u32_e32 v11, vcc_lo, v5, v13, vcc_lo
+; GFX11-NEXT: v_sub_co_ci_u32_e32 v8, vcc_lo, v6, v14, vcc_lo
+; GFX11-NEXT: v_sub_co_ci_u32_e64 v9, null, v7, v15, vcc_lo
+; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[12:13]
+; GFX11-NEXT: v_xor_b32_e32 v0, v0, v1
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[20:21], v[6:7]
+; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[14:15]
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
-; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, 0, v[12:13]
+; GFX11-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[8:9]
; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[14:15]
-; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[20:21], v[6:7]
-; GFX11-NEXT: v_ashrrev_i32_e32 v6, 31, v21
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[14:15]
+; GFX11-NEXT: v_ashrrev_i32_e32 v6, 31, v9
; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15]
-; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v19
-; GFX11-NEXT: v_dual_cndmask_b32 v2, v5, v4 :: v_dual_add_nc_u32 v7, 0x80000000, v6
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9]
+; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v17
+; GFX11-NEXT: v_add_nc_u32_e32 v7, 0x80000000, v6
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, 0, vcc_lo
; GFX11-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v0
; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x80000000, v3
-; GFX11-NEXT: v_xor_b32_e32 v2, v2, v1
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v16, v3, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v17, v3, vcc_lo
+; GFX11-NEXT: v_xor_b32_e32 v2, v1, v2
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v18, v3, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v19, v3, vcc_lo
; GFX11-NEXT: v_cmp_ne_u16_e64 s0, 0, v2
-; GFX11-NEXT: v_dual_cndmask_b32 v2, v18, v3 :: v_dual_cndmask_b32 v3, v19, v4
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v8, v6, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v5, v9, v6, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v20, v6, s0
-; GFX11-NEXT: v_cndmask_b32_e64 v7, v21, v7, s0
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v16, v3 :: v_dual_cndmask_b32 v3, v17, v4
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v10, v6, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v11, v6, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v8, v6, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v9, v7, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
ret <2 x i128> %result
@@ -5851,32 +5769,29 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX6-LABEL: s_ssubsat_v2i128:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_sub_u32 s16, s0, s8
-; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v0, s8
; GFX6-NEXT: s_subb_u32 s17, s1, s9
-; GFX6-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NEXT: v_mov_b32_e32 v1, s9
; GFX6-NEXT: s_subb_u32 s18, s2, s10
-; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[16:17], v[0:1]
-; GFX6-NEXT: v_mov_b32_e32 v0, s2
+; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1]
+; GFX6-NEXT: v_mov_b32_e32 v0, s10
; GFX6-NEXT: s_subb_u32 s19, s3, s11
-; GFX6-NEXT: v_mov_b32_e32 v1, s3
+; GFX6-NEXT: v_mov_b32_e32 v1, s11
; GFX6-NEXT: s_or_b64 s[0:1], vcc, vcc
-; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[18:19], v[0:1]
-; GFX6-NEXT: s_cselect_b32 s20, 1, 0
+; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
+; GFX6-NEXT: s_cselect_b32 s8, 1, 0
; GFX6-NEXT: s_or_b64 s[0:1], vcc, vcc
-; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[18:19], v[0:1]
-; GFX6-NEXT: s_cselect_b32 s2, 1, 0
+; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[0:1]
+; GFX6-NEXT: s_cselect_b32 s9, 1, 0
; GFX6-NEXT: s_or_b64 s[0:1], vcc, vcc
-; GFX6-NEXT: v_cmp_gt_u64_e64 s[0:1], s[8:9], 0
-; GFX6-NEXT: s_cselect_b32 s2, s20, s2
+; GFX6-NEXT: v_cmp_lt_i64_e64 s[0:1], s[18:19], 0
+; GFX6-NEXT: s_cselect_b32 s2, s8, s9
; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
-; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[10:11], 0
+; GFX6-NEXT: v_cmp_eq_u64_e64 s[0:1], s[18:19], 0
; GFX6-NEXT: s_cselect_b32 s3, 1, 0
; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
-; GFX6-NEXT: v_cmp_eq_u64_e64 s[0:1], s[10:11], 0
-; GFX6-NEXT: s_cselect_b32 s8, 1, 0
-; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
-; GFX6-NEXT: s_cselect_b32 s0, s3, s8
-; GFX6-NEXT: s_xor_b32 s8, s0, s2
+; GFX6-NEXT: s_cselect_b32 s0, 0, s3
+; GFX6-NEXT: s_xor_b32 s8, s2, s0
; GFX6-NEXT: s_ashr_i32 s0, s19, 31
; GFX6-NEXT: s_add_i32 s3, s0, 0x80000000
; GFX6-NEXT: s_and_b32 s8, s8, 1
@@ -5886,32 +5801,29 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[16:17]
; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], s[18:19]
; GFX6-NEXT: s_sub_u32 s8, s4, s12
-; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: v_mov_b32_e32 v0, s12
; GFX6-NEXT: s_subb_u32 s9, s5, s13
-; GFX6-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NEXT: v_mov_b32_e32 v1, s13
; GFX6-NEXT: s_subb_u32 s10, s6, s14
-; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
-; GFX6-NEXT: v_mov_b32_e32 v0, s6
+; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[0:1]
+; GFX6-NEXT: v_mov_b32_e32 v0, s14
; GFX6-NEXT: s_subb_u32 s11, s7, s15
-; GFX6-NEXT: v_mov_b32_e32 v1, s7
+; GFX6-NEXT: v_mov_b32_e32 v1, s15
; GFX6-NEXT: s_or_b64 s[4:5], vcc, vcc
-; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[10:11], v[0:1]
-; GFX6-NEXT: s_cselect_b32 s16, 1, 0
+; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[6:7], v[0:1]
+; GFX6-NEXT: s_cselect_b32 s12, 1, 0
; GFX6-NEXT: s_or_b64 s[4:5], vcc, vcc
-; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[10:11], v[0:1]
-; GFX6-NEXT: s_cselect_b32 s6, 1, 0
+; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[6:7], v[0:1]
+; GFX6-NEXT: s_cselect_b32 s13, 1, 0
; GFX6-NEXT: s_or_b64 s[4:5], vcc, vcc
-; GFX6-NEXT: v_cmp_gt_u64_e64 s[4:5], s[12:13], 0
-; GFX6-NEXT: s_cselect_b32 s6, s16, s6
+; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], s[10:11], 0
+; GFX6-NEXT: s_cselect_b32 s6, s12, s13
; GFX6-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
-; GFX6-NEXT: v_cmp_gt_i64_e64 s[4:5], s[14:15], 0
+; GFX6-NEXT: v_cmp_eq_u64_e64 s[4:5], s[10:11], 0
; GFX6-NEXT: s_cselect_b32 s7, 1, 0
; GFX6-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
-; GFX6-NEXT: v_cmp_eq_u64_e64 s[4:5], s[14:15], 0
-; GFX6-NEXT: s_cselect_b32 s12, 1, 0
-; GFX6-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
-; GFX6-NEXT: s_cselect_b32 s4, s7, s12
-; GFX6-NEXT: s_xor_b32 s12, s4, s6
+; GFX6-NEXT: s_cselect_b32 s4, 0, s7
+; GFX6-NEXT: s_xor_b32 s12, s6, s4
; GFX6-NEXT: s_ashr_i32 s4, s11, 31
; GFX6-NEXT: s_add_i32 s7, s4, 0x80000000
; GFX6-NEXT: s_and_b32 s12, s12, 1
@@ -5925,30 +5837,27 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX8-LABEL: s_ssubsat_v2i128:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_sub_u32 s16, s0, s8
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v0, s8
; GFX8-NEXT: s_subb_u32 s17, s1, s9
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v1, s9
; GFX8-NEXT: s_subb_u32 s18, s2, s10
-; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[16:17], v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v0, s10
; GFX8-NEXT: s_subb_u32 s19, s3, s11
-; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: v_mov_b32_e32 v1, s11
; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[18:19], v[0:1]
-; GFX8-NEXT: s_cselect_b32 s20, 1, 0
+; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
+; GFX8-NEXT: s_cselect_b32 s8, 1, 0
; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX8-NEXT: v_cmp_gt_u64_e64 s[0:1], s[8:9], 0
-; GFX8-NEXT: s_cselect_b32 s21, 1, 0
-; GFX8-NEXT: s_cmp_eq_u64 s[18:19], s[2:3]
-; GFX8-NEXT: s_cselect_b32 s2, s20, s21
-; GFX8-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[10:11], 0
-; GFX8-NEXT: s_cselect_b32 s3, 1, 0
+; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], s[18:19], 0
+; GFX8-NEXT: s_cselect_b32 s9, 1, 0
+; GFX8-NEXT: s_cmp_eq_u64 s[2:3], s[10:11]
+; GFX8-NEXT: s_cselect_b32 s2, s8, s9
; GFX8-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX8-NEXT: s_cselect_b32 s0, 1, 0
-; GFX8-NEXT: s_cmp_eq_u64 s[10:11], 0
-; GFX8-NEXT: s_cselect_b32 s0, s3, s0
-; GFX8-NEXT: s_xor_b32 s8, s0, s2
+; GFX8-NEXT: s_cmp_eq_u64 s[18:19], 0
+; GFX8-NEXT: s_cselect_b32 s0, 0, s0
+; GFX8-NEXT: s_xor_b32 s8, s2, s0
; GFX8-NEXT: s_ashr_i32 s0, s19, 31
; GFX8-NEXT: s_add_i32 s3, s0, 0x80000000
; GFX8-NEXT: s_and_b32 s8, s8, 1
@@ -5958,30 +5867,27 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[16:17]
; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], s[18:19]
; GFX8-NEXT: s_sub_u32 s8, s4, s12
-; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_mov_b32_e32 v0, s12
; GFX8-NEXT: s_subb_u32 s9, s5, s13
-; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: v_mov_b32_e32 v1, s13
; GFX8-NEXT: s_subb_u32 s10, s6, s14
-; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v0, s6
+; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v0, s14
; GFX8-NEXT: s_subb_u32 s11, s7, s15
-; GFX8-NEXT: v_mov_b32_e32 v1, s7
+; GFX8-NEXT: v_mov_b32_e32 v1, s15
; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[10:11], v[0:1]
-; GFX8-NEXT: s_cselect_b32 s16, 1, 0
+; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[6:7], v[0:1]
+; GFX8-NEXT: s_cselect_b32 s12, 1, 0
; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX8-NEXT: v_cmp_gt_u64_e64 s[4:5], s[12:13], 0
-; GFX8-NEXT: s_cselect_b32 s17, 1, 0
-; GFX8-NEXT: s_cmp_eq_u64 s[10:11], s[6:7]
-; GFX8-NEXT: s_cselect_b32 s6, s16, s17
-; GFX8-NEXT: s_cmp_lg_u64 s[4:5], 0
-; GFX8-NEXT: v_cmp_gt_i64_e64 s[4:5], s[14:15], 0
-; GFX8-NEXT: s_cselect_b32 s7, 1, 0
+; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], s[10:11], 0
+; GFX8-NEXT: s_cselect_b32 s13, 1, 0
+; GFX8-NEXT: s_cmp_eq_u64 s[6:7], s[14:15]
+; GFX8-NEXT: s_cselect_b32 s6, s12, s13
; GFX8-NEXT: s_cmp_lg_u64 s[4:5], 0
; GFX8-NEXT: s_cselect_b32 s4, 1, 0
-; GFX8-NEXT: s_cmp_eq_u64 s[14:15], 0
-; GFX8-NEXT: s_cselect_b32 s4, s7, s4
-; GFX8-NEXT: s_xor_b32 s12, s4, s6
+; GFX8-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX8-NEXT: s_cselect_b32 s4, 0, s4
+; GFX8-NEXT: s_xor_b32 s12, s6, s4
; GFX8-NEXT: s_ashr_i32 s4, s11, 31
; GFX8-NEXT: s_add_i32 s7, s4, 0x80000000
; GFX8-NEXT: s_and_b32 s12, s12, 1
@@ -5995,30 +5901,27 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX9-LABEL: s_ssubsat_v2i128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_sub_u32 s16, s0, s8
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v0, s8
; GFX9-NEXT: s_subb_u32 s17, s1, s9
-; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: v_mov_b32_e32 v1, s9
; GFX9-NEXT: s_subb_u32 s18, s2, s10
-; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[16:17], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1]
+; GFX9-NEXT: v_mov_b32_e32 v0, s10
; GFX9-NEXT: s_subb_u32 s19, s3, s11
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-NEXT: v_mov_b32_e32 v1, s11
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[18:19], v[0:1]
-; GFX9-NEXT: s_cselect_b32 s20, 1, 0
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
+; GFX9-NEXT: s_cselect_b32 s8, 1, 0
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: v_cmp_gt_u64_e64 s[0:1], s[8:9], 0
-; GFX9-NEXT: s_cselect_b32 s21, 1, 0
-; GFX9-NEXT: s_cmp_eq_u64 s[18:19], s[2:3]
-; GFX9-NEXT: s_cselect_b32 s2, s20, s21
-; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[10:11], 0
-; GFX9-NEXT: s_cselect_b32 s3, 1, 0
+; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], s[18:19], 0
+; GFX9-NEXT: s_cselect_b32 s9, 1, 0
+; GFX9-NEXT: s_cmp_eq_u64 s[2:3], s[10:11]
+; GFX9-NEXT: s_cselect_b32 s2, s8, s9
; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX9-NEXT: s_cselect_b32 s0, 1, 0
-; GFX9-NEXT: s_cmp_eq_u64 s[10:11], 0
-; GFX9-NEXT: s_cselect_b32 s0, s3, s0
-; GFX9-NEXT: s_xor_b32 s8, s0, s2
+; GFX9-NEXT: s_cmp_eq_u64 s[18:19], 0
+; GFX9-NEXT: s_cselect_b32 s0, 0, s0
+; GFX9-NEXT: s_xor_b32 s8, s2, s0
; GFX9-NEXT: s_ashr_i32 s0, s19, 31
; GFX9-NEXT: s_add_i32 s3, s0, 0x80000000
; GFX9-NEXT: s_and_b32 s8, s8, 1
@@ -6028,30 +5931,27 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], s[16:17]
; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], s[18:19]
; GFX9-NEXT: s_sub_u32 s8, s4, s12
-; GFX9-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-NEXT: v_mov_b32_e32 v0, s12
; GFX9-NEXT: s_subb_u32 s9, s5, s13
-; GFX9-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-NEXT: v_mov_b32_e32 v1, s13
; GFX9-NEXT: s_subb_u32 s10, s6, s14
-; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s6
+; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[0:1]
+; GFX9-NEXT: v_mov_b32_e32 v0, s14
; GFX9-NEXT: s_subb_u32 s11, s7, s15
-; GFX9-NEXT: v_mov_b32_e32 v1, s7
+; GFX9-NEXT: v_mov_b32_e32 v1, s15
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[10:11], v[0:1]
-; GFX9-NEXT: s_cselect_b32 s16, 1, 0
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[6:7], v[0:1]
+; GFX9-NEXT: s_cselect_b32 s12, 1, 0
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: v_cmp_gt_u64_e64 s[4:5], s[12:13], 0
-; GFX9-NEXT: s_cselect_b32 s17, 1, 0
-; GFX9-NEXT: s_cmp_eq_u64 s[10:11], s[6:7]
-; GFX9-NEXT: s_cselect_b32 s6, s16, s17
-; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0
-; GFX9-NEXT: v_cmp_gt_i64_e64 s[4:5], s[14:15], 0
-; GFX9-NEXT: s_cselect_b32 s7, 1, 0
+; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], s[10:11], 0
+; GFX9-NEXT: s_cselect_b32 s13, 1, 0
+; GFX9-NEXT: s_cmp_eq_u64 s[6:7], s[14:15]
+; GFX9-NEXT: s_cselect_b32 s6, s12, s13
; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
-; GFX9-NEXT: s_cmp_eq_u64 s[14:15], 0
-; GFX9-NEXT: s_cselect_b32 s4, s7, s4
-; GFX9-NEXT: s_xor_b32 s12, s4, s6
+; GFX9-NEXT: s_cmp_eq_u64 s[10:11], 0
+; GFX9-NEXT: s_cselect_b32 s4, 0, s4
+; GFX9-NEXT: s_xor_b32 s12, s6, s4
; GFX9-NEXT: s_ashr_i32 s4, s11, 31
; GFX9-NEXT: s_add_i32 s7, s4, 0x80000000
; GFX9-NEXT: s_and_b32 s12, s12, 1
@@ -6064,64 +5964,58 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
;
; GFX10PLUS-LABEL: s_ssubsat_v2i128:
; GFX10PLUS: ; %bb.0:
-; GFX10PLUS-NEXT: s_sub_u32 s16, s0, s8
-; GFX10PLUS-NEXT: s_subb_u32 s17, s1, s9
-; GFX10PLUS-NEXT: s_subb_u32 s18, s2, s10
-; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s0, s[16:17], s[0:1]
-; GFX10PLUS-NEXT: s_subb_u32 s19, s3, s11
-; GFX10PLUS-NEXT: v_cmp_gt_u64_e64 s8, s[8:9], 0
-; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s1, s[18:19], s[2:3]
-; GFX10PLUS-NEXT: s_cmp_lg_u32 s0, 0
-; GFX10PLUS-NEXT: s_cselect_b32 s0, 1, 0
-; GFX10PLUS-NEXT: s_cmp_lg_u32 s1, 0
-; GFX10PLUS-NEXT: s_cselect_b32 s1, 1, 0
-; GFX10PLUS-NEXT: s_cmp_eq_u64 s[18:19], s[2:3]
-; GFX10PLUS-NEXT: v_cmp_gt_i64_e64 s2, s[10:11], 0
-; GFX10PLUS-NEXT: s_cselect_b32 s1, s0, s1
-; GFX10PLUS-NEXT: s_cmp_lg_u32 s8, 0
-; GFX10PLUS-NEXT: s_cselect_b32 s0, 1, 0
-; GFX10PLUS-NEXT: s_cmp_lg_u32 s2, 0
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s16, s[0:1], s[8:9]
+; GFX10PLUS-NEXT: s_sub_u32 s0, s0, s8
+; GFX10PLUS-NEXT: s_subb_u32 s1, s1, s9
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s17, s[2:3], s[10:11]
+; GFX10PLUS-NEXT: s_subb_u32 s8, s2, s10
+; GFX10PLUS-NEXT: s_subb_u32 s9, s3, s11
+; GFX10PLUS-NEXT: s_cmp_lg_u32 s16, 0
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s18, s[8:9], 0
+; GFX10PLUS-NEXT: s_cselect_b32 s16, 1, 0
+; GFX10PLUS-NEXT: s_cmp_lg_u32 s17, 0
+; GFX10PLUS-NEXT: s_cselect_b32 s17, 1, 0
+; GFX10PLUS-NEXT: s_cmp_eq_u64 s[2:3], s[10:11]
+; GFX10PLUS-NEXT: s_cselect_b32 s3, s16, s17
+; GFX10PLUS-NEXT: s_cmp_lg_u32 s18, 0
; GFX10PLUS-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10PLUS-NEXT: s_cmp_eq_u64 s[10:11], 0
-; GFX10PLUS-NEXT: s_cselect_b32 s2, s0, s2
-; GFX10PLUS-NEXT: s_ashr_i32 s0, s19, 31
-; GFX10PLUS-NEXT: s_xor_b32 s2, s2, s1
-; GFX10PLUS-NEXT: s_add_i32 s3, s0, 0x80000000
-; GFX10PLUS-NEXT: s_and_b32 s8, s2, 1
-; GFX10PLUS-NEXT: s_mov_b32 s1, s0
-; GFX10PLUS-NEXT: s_mov_b32 s2, s0
-; GFX10PLUS-NEXT: s_cmp_lg_u32 s8, 0
-; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[0:1], s[16:17]
-; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], s[2:3], s[18:19]
-; GFX10PLUS-NEXT: s_sub_u32 s8, s4, s12
-; GFX10PLUS-NEXT: s_subb_u32 s9, s5, s13
-; GFX10PLUS-NEXT: s_subb_u32 s10, s6, s14
-; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s4, s[8:9], s[4:5]
-; GFX10PLUS-NEXT: s_subb_u32 s11, s7, s15
-; GFX10PLUS-NEXT: v_cmp_gt_u64_e64 s12, s[12:13], 0
-; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s5, s[10:11], s[6:7]
-; GFX10PLUS-NEXT: s_cmp_lg_u32 s4, 0
-; GFX10PLUS-NEXT: s_cselect_b32 s4, 1, 0
-; GFX10PLUS-NEXT: s_cmp_lg_u32 s5, 0
-; GFX10PLUS-NEXT: s_cselect_b32 s5, 1, 0
-; GFX10PLUS-NEXT: s_cmp_eq_u64 s[10:11], s[6:7]
-; GFX10PLUS-NEXT: v_cmp_gt_i64_e64 s6, s[14:15], 0
-; GFX10PLUS-NEXT: s_cselect_b32 s5, s4, s5
+; GFX10PLUS-NEXT: s_cmp_eq_u64 s[8:9], 0
+; GFX10PLUS-NEXT: s_cselect_b32 s10, 0, s2
+; GFX10PLUS-NEXT: s_ashr_i32 s2, s9, 31
+; GFX10PLUS-NEXT: s_xor_b32 s10, s3, s10
+; GFX10PLUS-NEXT: s_add_i32 s11, s2, 0x80000000
+; GFX10PLUS-NEXT: s_and_b32 s16, s10, 1
+; GFX10PLUS-NEXT: s_mov_b32 s3, s2
+; GFX10PLUS-NEXT: s_mov_b32 s10, s2
+; GFX10PLUS-NEXT: s_cmp_lg_u32 s16, 0
+; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1]
+; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], s[10:11], s[8:9]
+; GFX10PLUS-NEXT: v_cmp_lt_u64_e64 s10, s[4:5], s[12:13]
+; GFX10PLUS-NEXT: s_sub_u32 s4, s4, s12
+; GFX10PLUS-NEXT: s_subb_u32 s5, s5, s13
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s11, s[6:7], s[14:15]
+; GFX10PLUS-NEXT: s_subb_u32 s8, s6, s14
+; GFX10PLUS-NEXT: s_subb_u32 s9, s7, s15
+; GFX10PLUS-NEXT: s_cmp_lg_u32 s10, 0
+; GFX10PLUS-NEXT: v_cmp_lt_i64_e64 s12, s[8:9], 0
+; GFX10PLUS-NEXT: s_cselect_b32 s10, 1, 0
+; GFX10PLUS-NEXT: s_cmp_lg_u32 s11, 0
+; GFX10PLUS-NEXT: s_cselect_b32 s11, 1, 0
+; GFX10PLUS-NEXT: s_cmp_eq_u64 s[6:7], s[14:15]
+; GFX10PLUS-NEXT: s_cselect_b32 s7, s10, s11
; GFX10PLUS-NEXT: s_cmp_lg_u32 s12, 0
-; GFX10PLUS-NEXT: s_cselect_b32 s4, 1, 0
-; GFX10PLUS-NEXT: s_cmp_lg_u32 s6, 0
; GFX10PLUS-NEXT: s_cselect_b32 s6, 1, 0
-; GFX10PLUS-NEXT: s_cmp_eq_u64 s[14:15], 0
-; GFX10PLUS-NEXT: s_cselect_b32 s6, s4, s6
-; GFX10PLUS-NEXT: s_ashr_i32 s4, s11, 31
-; GFX10PLUS-NEXT: s_xor_b32 s6, s6, s5
-; GFX10PLUS-NEXT: s_add_i32 s7, s4, 0x80000000
-; GFX10PLUS-NEXT: s_and_b32 s12, s6, 1
-; GFX10PLUS-NEXT: s_mov_b32 s5, s4
-; GFX10PLUS-NEXT: s_mov_b32 s6, s4
+; GFX10PLUS-NEXT: s_cmp_eq_u64 s[8:9], 0
+; GFX10PLUS-NEXT: s_cselect_b32 s10, 0, s6
+; GFX10PLUS-NEXT: s_ashr_i32 s6, s9, 31
+; GFX10PLUS-NEXT: s_xor_b32 s10, s7, s10
+; GFX10PLUS-NEXT: s_add_i32 s11, s6, 0x80000000
+; GFX10PLUS-NEXT: s_and_b32 s12, s10, 1
+; GFX10PLUS-NEXT: s_mov_b32 s7, s6
+; GFX10PLUS-NEXT: s_mov_b32 s10, s6
; GFX10PLUS-NEXT: s_cmp_lg_u32 s12, 0
-; GFX10PLUS-NEXT: s_cselect_b64 s[4:5], s[4:5], s[8:9]
-; GFX10PLUS-NEXT: s_cselect_b64 s[6:7], s[6:7], s[10:11]
+; GFX10PLUS-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5]
+; GFX10PLUS-NEXT: s_cselect_b64 s[6:7], s[10:11], s[8:9]
; GFX10PLUS-NEXT: ; return to shader part epilog
%result = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
ret <2 x i128> %result
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
index fa1f5472c3083..2ced6e05b0f93 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
@@ -204,9 +204,9 @@ define i32 @v_ssubo_i32(i32 %a, i32 %b) {
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_sub_i32_e32 v2, vcc, v0, v1
-; GFX7-NEXT: v_cmp_lt_i32_e32 vcc, v2, v0
-; GFX7-NEXT: v_cmp_lt_i32_e64 s[4:5], 0, v1
-; GFX7-NEXT: s_xor_b64 s[4:5], s[4:5], vcc
+; GFX7-NEXT: v_cmp_lt_i32_e32 vcc, v0, v1
+; GFX7-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v2
+; GFX7-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v2, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
@@ -215,9 +215,9 @@ define i32 @v_ssubo_i32(i32 %a, i32 %b) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v0, v1
-; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, v2, v0
-; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], 0, v1
-; GFX8-NEXT: s_xor_b64 s[4:5], s[4:5], vcc
+; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, v0, v1
+; GFX8-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v2
+; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v2, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -226,9 +226,9 @@ define i32 @v_ssubo_i32(i32 %a, i32 %b) {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_sub_u32_e32 v2, v0, v1
-; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, v2, v0
-; GFX9-NEXT: v_cmp_lt_i32_e64 s[4:5], 0, v1
-; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], vcc
+; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, v0, v1
+; GFX9-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v2
+; GFX9-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX9-NEXT: v_sub_u32_e32 v0, v2, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -246,9 +246,9 @@ define i64 @v_ssubo_i64(i64 %a, i64 %b) {
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_sub_i32_e32 v4, vcc, v0, v2
; GFX7-NEXT: v_subb_u32_e32 v5, vcc, v1, v3, vcc
-; GFX7-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1]
-; GFX7-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[2:3]
-; GFX7-NEXT: s_xor_b64 s[4:5], s[4:5], vcc
+; GFX7-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
+; GFX7-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[4:5]
+; GFX7-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v4, v0
; GFX7-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v5, vcc
@@ -259,9 +259,9 @@ define i64 @v_ssubo_i64(i64 %a, i64 %b) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v0, v2
; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v1, v3, vcc
-; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1]
-; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[2:3]
-; GFX8-NEXT: s_xor_b64 s[4:5], s[4:5], vcc
+; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
+; GFX8-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[4:5]
+; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v4, v0
; GFX8-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v5, vcc
@@ -272,9 +272,9 @@ define i64 @v_ssubo_i64(i64 %a, i64 %b) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v0, v2
; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v1, v3, vcc
-; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1]
-; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[2:3]
-; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], vcc
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
+; GFX9-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[4:5]
+; GFX9-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v4, v0
; GFX9-NEXT: v_subbrev_co_u32_e32 v1, vcc, 0, v5, vcc
@@ -293,12 +293,12 @@ define <2 x i32> @v_ssubo_v2i32(<2 x i32> %a, <2 x i32> %b) {
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_sub_i32_e32 v4, vcc, v0, v2
; GFX7-NEXT: v_sub_i32_e32 v5, vcc, v1, v3
-; GFX7-NEXT: v_cmp_lt_i32_e32 vcc, v4, v0
-; GFX7-NEXT: v_cmp_lt_i32_e64 s[4:5], v5, v1
-; GFX7-NEXT: v_cmp_lt_i32_e64 s[6:7], 0, v2
-; GFX7-NEXT: v_cmp_lt_i32_e64 s[8:9], 0, v3
-; GFX7-NEXT: s_xor_b64 s[6:7], s[6:7], vcc
-; GFX7-NEXT: s_xor_b64 s[4:5], s[8:9], s[4:5]
+; GFX7-NEXT: v_cmp_lt_i32_e32 vcc, v0, v2
+; GFX7-NEXT: v_cmp_lt_i32_e64 s[4:5], v1, v3
+; GFX7-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v4
+; GFX7-NEXT: v_cmp_gt_i32_e64 s[8:9], 0, v5
+; GFX7-NEXT: s_xor_b64 s[6:7], vcc, s[6:7]
+; GFX7-NEXT: s_xor_b64 s[4:5], s[4:5], s[8:9]
; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[6:7]
; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v4, v0
@@ -310,12 +310,12 @@ define <2 x i32> @v_ssubo_v2i32(<2 x i32> %a, <2 x i32> %b) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v0, v2
; GFX8-NEXT: v_sub_u32_e32 v5, vcc, v1, v3
-; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, v4, v0
-; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v5, v1
-; GFX8-NEXT: v_cmp_lt_i32_e64 s[6:7], 0, v2
-; GFX8-NEXT: v_cmp_lt_i32_e64 s[8:9], 0, v3
-; GFX8-NEXT: s_xor_b64 s[6:7], s[6:7], vcc
-; GFX8-NEXT: s_xor_b64 s[4:5], s[8:9], s[4:5]
+; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, v0, v2
+; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v1, v3
+; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v4
+; GFX8-NEXT: v_cmp_gt_i32_e64 s[8:9], 0, v5
+; GFX8-NEXT: s_xor_b64 s[6:7], vcc, s[6:7]
+; GFX8-NEXT: s_xor_b64 s[4:5], s[4:5], s[8:9]
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[6:7]
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v4, v0
@@ -327,12 +327,12 @@ define <2 x i32> @v_ssubo_v2i32(<2 x i32> %a, <2 x i32> %b) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_sub_u32_e32 v4, v0, v2
; GFX9-NEXT: v_sub_u32_e32 v5, v1, v3
-; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, v4, v0
-; GFX9-NEXT: v_cmp_lt_i32_e64 s[4:5], v5, v1
-; GFX9-NEXT: v_cmp_lt_i32_e64 s[6:7], 0, v2
-; GFX9-NEXT: v_cmp_lt_i32_e64 s[8:9], 0, v3
-; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], vcc
-; GFX9-NEXT: s_xor_b64 s[4:5], s[8:9], s[4:5]
+; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, v0, v2
+; GFX9-NEXT: v_cmp_lt_i32_e64 s[4:5], v1, v3
+; GFX9-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v4
+; GFX9-NEXT: v_cmp_gt_i32_e64 s[8:9], 0, v5
+; GFX9-NEXT: s_xor_b64 s[6:7], vcc, s[6:7]
+; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], s[8:9]
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[6:7]
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
; GFX9-NEXT: v_sub_u32_e32 v0, v4, v0
@@ -351,12 +351,12 @@ define i8 @v_ssubo_i8(i8 %a, i8 %b) {
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_sub_i32_e32 v2, vcc, v0, v1
-; GFX7-NEXT: v_bfe_i32 v3, v2, 0, 8
; GFX7-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX7-NEXT: v_cmp_lt_i32_e32 vcc, v3, v0
-; GFX7-NEXT: v_bfe_i32 v0, v1, 0, 8
-; GFX7-NEXT: v_cmp_lt_i32_e64 s[4:5], 0, v0
-; GFX7-NEXT: s_xor_b64 s[4:5], s[4:5], vcc
+; GFX7-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX7-NEXT: v_cmp_lt_i32_e32 vcc, v0, v1
+; GFX7-NEXT: v_bfe_i32 v0, v2, 0, 8
+; GFX7-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v0
+; GFX7-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v2, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
@@ -365,12 +365,12 @@ define i8 @v_ssubo_i8(i8 %a, i8 %b) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u16_e32 v2, v0, v1
-; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 8
; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, v3, v0
-; GFX8-NEXT: v_bfe_i32 v0, v1, 0, 8
-; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], 0, v0
-; GFX8-NEXT: s_xor_b64 s[4:5], s[4:5], vcc
+; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, v0, v1
+; GFX8-NEXT: v_bfe_i32 v0, v2, 0, 8
+; GFX8-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v0
+; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX8-NEXT: v_sub_u16_e32 v0, v2, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -379,10 +379,10 @@ define i8 @v_ssubo_i8(i8 %a, i8 %b) {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_sub_u16_e32 v2, v0, v1
-; GFX9-NEXT: v_cmp_lt_i32_sdwa s[4:5], sext(v2), sext(v0) src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-NEXT: v_cmp_lt_i32_sdwa s[4:5], sext(v0), sext(v1) src0_sel:BYTE_0 src1_sel:BYTE_0
; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_cmp_gt_i32_sdwa s[6:7], sext(v1), v0 src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: s_xor_b64 s[4:5], s[6:7], s[4:5]
+; GFX9-NEXT: v_cmp_lt_i32_sdwa s[6:7], sext(v2), v0 src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7]
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX9-NEXT: v_sub_u16_e32 v0, v2, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -399,12 +399,12 @@ define i7 @v_ssubo_i7(i7 %a, i7 %b) {
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_sub_i32_e32 v2, vcc, v0, v1
-; GFX7-NEXT: v_bfe_i32 v3, v2, 0, 7
; GFX7-NEXT: v_bfe_i32 v0, v0, 0, 7
-; GFX7-NEXT: v_cmp_lt_i32_e32 vcc, v3, v0
-; GFX7-NEXT: v_bfe_i32 v0, v1, 0, 7
-; GFX7-NEXT: v_cmp_lt_i32_e64 s[4:5], 0, v0
-; GFX7-NEXT: s_xor_b64 s[4:5], s[4:5], vcc
+; GFX7-NEXT: v_bfe_i32 v1, v1, 0, 7
+; GFX7-NEXT: v_cmp_lt_i32_e32 vcc, v0, v1
+; GFX7-NEXT: v_bfe_i32 v0, v2, 0, 7
+; GFX7-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v0
+; GFX7-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v2, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
@@ -413,12 +413,12 @@ define i7 @v_ssubo_i7(i7 %a, i7 %b) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u16_e32 v2, v0, v1
-; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 7
; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 7
-; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, v3, v0
-; GFX8-NEXT: v_bfe_i32 v0, v1, 0, 7
-; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], 0, v0
-; GFX8-NEXT: s_xor_b64 s[4:5], s[4:5], vcc
+; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 7
+; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, v0, v1
+; GFX8-NEXT: v_bfe_i32 v0, v2, 0, 7
+; GFX8-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v0
+; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX8-NEXT: v_sub_u16_e32 v0, v2, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -427,12 +427,12 @@ define i7 @v_ssubo_i7(i7 %a, i7 %b) {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_sub_u16_e32 v2, v0, v1
-; GFX9-NEXT: v_bfe_i32 v3, v2, 0, 7
; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 7
-; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, v3, v0
-; GFX9-NEXT: v_bfe_i32 v0, v1, 0, 7
-; GFX9-NEXT: v_cmp_lt_i32_e64 s[4:5], 0, v0
-; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], vcc
+; GFX9-NEXT: v_bfe_i32 v1, v1, 0, 7
+; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, v0, v1
+; GFX9-NEXT: v_bfe_i32 v0, v2, 0, 7
+; GFX9-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v0
+; GFX9-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX9-NEXT: v_sub_u16_e32 v0, v2, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -647,11 +647,11 @@ define amdgpu_ps i32 @s_ssubo_i32(i32 inreg %a, i32 inreg %b) {
; GFX7-LABEL: s_ssubo_i32:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_sub_i32 s2, s0, s1
-; GFX7-NEXT: s_cmp_lt_i32 s2, s0
+; GFX7-NEXT: s_cmp_lt_i32 s0, s1
; GFX7-NEXT: s_cselect_b32 s0, 1, 0
-; GFX7-NEXT: s_cmp_gt_i32 s1, 0
+; GFX7-NEXT: s_cmp_lt_i32 s2, 0
; GFX7-NEXT: s_cselect_b32 s1, 1, 0
-; GFX7-NEXT: s_xor_b32 s0, s1, s0
+; GFX7-NEXT: s_xor_b32 s0, s0, s1
; GFX7-NEXT: s_cmp_lg_u32 s0, 0
; GFX7-NEXT: s_cselect_b32 s0, 1, 0
; GFX7-NEXT: s_sub_i32 s0, s2, s0
@@ -660,11 +660,11 @@ define amdgpu_ps i32 @s_ssubo_i32(i32 inreg %a, i32 inreg %b) {
; GFX8-LABEL: s_ssubo_i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_sub_i32 s2, s0, s1
-; GFX8-NEXT: s_cmp_lt_i32 s2, s0
+; GFX8-NEXT: s_cmp_lt_i32 s0, s1
; GFX8-NEXT: s_cselect_b32 s0, 1, 0
-; GFX8-NEXT: s_cmp_gt_i32 s1, 0
+; GFX8-NEXT: s_cmp_lt_i32 s2, 0
; GFX8-NEXT: s_cselect_b32 s1, 1, 0
-; GFX8-NEXT: s_xor_b32 s0, s1, s0
+; GFX8-NEXT: s_xor_b32 s0, s0, s1
; GFX8-NEXT: s_cmp_lg_u32 s0, 0
; GFX8-NEXT: s_cselect_b32 s0, 1, 0
; GFX8-NEXT: s_sub_i32 s0, s2, s0
@@ -673,11 +673,11 @@ define amdgpu_ps i32 @s_ssubo_i32(i32 inreg %a, i32 inreg %b) {
; GFX9-LABEL: s_ssubo_i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_sub_i32 s2, s0, s1
-; GFX9-NEXT: s_cmp_lt_i32 s2, s0
+; GFX9-NEXT: s_cmp_lt_i32 s0, s1
; GFX9-NEXT: s_cselect_b32 s0, 1, 0
-; GFX9-NEXT: s_cmp_gt_i32 s1, 0
+; GFX9-NEXT: s_cmp_lt_i32 s2, 0
; GFX9-NEXT: s_cselect_b32 s1, 1, 0
-; GFX9-NEXT: s_xor_b32 s0, s1, s0
+; GFX9-NEXT: s_xor_b32 s0, s0, s1
; GFX9-NEXT: s_cmp_lg_u32 s0, 0
; GFX9-NEXT: s_cselect_b32 s0, 1, 0
; GFX9-NEXT: s_sub_i32 s0, s2, s0
@@ -693,17 +693,17 @@ define amdgpu_ps i32 @s_ssubo_i32(i32 inreg %a, i32 inreg %b) {
define amdgpu_ps i64 @s_ssubo_i64(i64 inreg %a, i64 inreg %b) {
; GFX7-LABEL: s_ssubo_i64:
; GFX7: ; %bb.0:
+; GFX7-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-NEXT: v_mov_b32_e32 v1, s3
; GFX7-NEXT: s_sub_u32 s4, s0, s2
-; GFX7-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]
; GFX7-NEXT: s_subb_u32 s5, s1, s3
-; GFX7-NEXT: v_mov_b32_e32 v1, s1
-; GFX7-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
; GFX7-NEXT: s_or_b64 s[0:1], vcc, vcc
-; GFX7-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 0
-; GFX7-NEXT: s_cselect_b32 s6, 1, 0
+; GFX7-NEXT: v_cmp_lt_i64_e64 s[0:1], s[4:5], 0
+; GFX7-NEXT: s_cselect_b32 s2, 1, 0
; GFX7-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
; GFX7-NEXT: s_cselect_b32 s0, 1, 0
-; GFX7-NEXT: s_xor_b32 s0, s0, s6
+; GFX7-NEXT: s_xor_b32 s0, s2, s0
; GFX7-NEXT: s_cmp_lg_u32 s0, 0
; GFX7-NEXT: s_cselect_b32 s0, 1, 0
; GFX7-NEXT: s_sub_u32 s0, s4, s0
@@ -712,17 +712,17 @@ define amdgpu_ps i64 @s_ssubo_i64(i64 inreg %a, i64 inreg %b) {
;
; GFX8-LABEL: s_ssubo_i64:
; GFX8: ; %bb.0:
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: s_sub_u32 s4, s0, s2
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]
; GFX8-NEXT: s_subb_u32 s5, s1, s3
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
-; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 0
+; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], s[4:5], 0
; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX8-NEXT: s_cselect_b32 s6, 1, 0
+; GFX8-NEXT: s_cselect_b32 s2, 1, 0
; GFX8-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX8-NEXT: s_cselect_b32 s0, 1, 0
-; GFX8-NEXT: s_xor_b32 s0, s0, s6
+; GFX8-NEXT: s_xor_b32 s0, s2, s0
; GFX8-NEXT: s_cmp_lg_u32 s0, 0
; GFX8-NEXT: s_cselect_b32 s0, 1, 0
; GFX8-NEXT: s_sub_u32 s0, s4, s0
@@ -731,17 +731,17 @@ define amdgpu_ps i64 @s_ssubo_i64(i64 inreg %a, i64 inreg %b) {
;
; GFX9-LABEL: s_ssubo_i64:
; GFX9: ; %bb.0:
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: s_sub_u32 s4, s0, s2
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]
; GFX9-NEXT: s_subb_u32 s5, s1, s3
-; GFX9-NEXT: v_mov_b32_e32 v1, s1
-; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
-; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 0
+; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], s[4:5], 0
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_cselect_b32 s6, 1, 0
+; GFX9-NEXT: s_cselect_b32 s2, 1, 0
; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX9-NEXT: s_cselect_b32 s0, 1, 0
-; GFX9-NEXT: s_xor_b32 s0, s0, s6
+; GFX9-NEXT: s_xor_b32 s0, s2, s0
; GFX9-NEXT: s_cmp_lg_u32 s0, 0
; GFX9-NEXT: s_cselect_b32 s0, 1, 0
; GFX9-NEXT: s_sub_u32 s0, s4, s0
@@ -760,16 +760,16 @@ define amdgpu_ps <2 x i32> @s_ssubo_v2i32(<2 x i32> inreg %a, <2 x i32> inreg %b
; GFX7: ; %bb.0:
; GFX7-NEXT: s_sub_i32 s4, s0, s2
; GFX7-NEXT: s_sub_i32 s5, s1, s3
-; GFX7-NEXT: s_cmp_lt_i32 s4, s0
+; GFX7-NEXT: s_cmp_lt_i32 s0, s2
; GFX7-NEXT: s_cselect_b32 s0, 1, 0
-; GFX7-NEXT: s_cmp_lt_i32 s5, s1
+; GFX7-NEXT: s_cmp_lt_i32 s1, s3
; GFX7-NEXT: s_cselect_b32 s1, 1, 0
-; GFX7-NEXT: s_cmp_gt_i32 s2, 0
+; GFX7-NEXT: s_cmp_lt_i32 s4, 0
; GFX7-NEXT: s_cselect_b32 s2, 1, 0
-; GFX7-NEXT: s_cmp_gt_i32 s3, 0
+; GFX7-NEXT: s_cmp_lt_i32 s5, 0
; GFX7-NEXT: s_cselect_b32 s3, 1, 0
-; GFX7-NEXT: s_xor_b32 s0, s2, s0
-; GFX7-NEXT: s_xor_b32 s1, s3, s1
+; GFX7-NEXT: s_xor_b32 s0, s0, s2
+; GFX7-NEXT: s_xor_b32 s1, s1, s3
; GFX7-NEXT: s_cmp_lg_u32 s0, 0
; GFX7-NEXT: s_cselect_b32 s0, 1, 0
; GFX7-NEXT: s_cmp_lg_u32 s1, 0
@@ -782,16 +782,16 @@ define amdgpu_ps <2 x i32> @s_ssubo_v2i32(<2 x i32> inreg %a, <2 x i32> inreg %b
; GFX8: ; %bb.0:
; GFX8-NEXT: s_sub_i32 s4, s0, s2
; GFX8-NEXT: s_sub_i32 s5, s1, s3
-; GFX8-NEXT: s_cmp_lt_i32 s4, s0
+; GFX8-NEXT: s_cmp_lt_i32 s0, s2
; GFX8-NEXT: s_cselect_b32 s0, 1, 0
-; GFX8-NEXT: s_cmp_lt_i32 s5, s1
+; GFX8-NEXT: s_cmp_lt_i32 s1, s3
; GFX8-NEXT: s_cselect_b32 s1, 1, 0
-; GFX8-NEXT: s_cmp_gt_i32 s2, 0
+; GFX8-NEXT: s_cmp_lt_i32 s4, 0
; GFX8-NEXT: s_cselect_b32 s2, 1, 0
-; GFX8-NEXT: s_cmp_gt_i32 s3, 0
+; GFX8-NEXT: s_cmp_lt_i32 s5, 0
; GFX8-NEXT: s_cselect_b32 s3, 1, 0
-; GFX8-NEXT: s_xor_b32 s0, s2, s0
-; GFX8-NEXT: s_xor_b32 s1, s3, s1
+; GFX8-NEXT: s_xor_b32 s0, s0, s2
+; GFX8-NEXT: s_xor_b32 s1, s1, s3
; GFX8-NEXT: s_cmp_lg_u32 s0, 0
; GFX8-NEXT: s_cselect_b32 s0, 1, 0
; GFX8-NEXT: s_cmp_lg_u32 s1, 0
@@ -804,16 +804,16 @@ define amdgpu_ps <2 x i32> @s_ssubo_v2i32(<2 x i32> inreg %a, <2 x i32> inreg %b
; GFX9: ; %bb.0:
; GFX9-NEXT: s_sub_i32 s4, s0, s2
; GFX9-NEXT: s_sub_i32 s5, s1, s3
-; GFX9-NEXT: s_cmp_lt_i32 s4, s0
+; GFX9-NEXT: s_cmp_lt_i32 s0, s2
; GFX9-NEXT: s_cselect_b32 s0, 1, 0
-; GFX9-NEXT: s_cmp_lt_i32 s5, s1
+; GFX9-NEXT: s_cmp_lt_i32 s1, s3
; GFX9-NEXT: s_cselect_b32 s1, 1, 0
-; GFX9-NEXT: s_cmp_gt_i32 s2, 0
+; GFX9-NEXT: s_cmp_lt_i32 s4, 0
; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: s_cmp_gt_i32 s3, 0
+; GFX9-NEXT: s_cmp_lt_i32 s5, 0
; GFX9-NEXT: s_cselect_b32 s3, 1, 0
-; GFX9-NEXT: s_xor_b32 s0, s2, s0
-; GFX9-NEXT: s_xor_b32 s1, s3, s1
+; GFX9-NEXT: s_xor_b32 s0, s0, s2
+; GFX9-NEXT: s_xor_b32 s1, s1, s3
; GFX9-NEXT: s_cmp_lg_u32 s0, 0
; GFX9-NEXT: s_cselect_b32 s0, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s1, 0
@@ -834,12 +834,12 @@ define i8 @s_ssubo_i8(i8 %a, i8 %b) {
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_sub_i32_e32 v2, vcc, v0, v1
-; GFX7-NEXT: v_bfe_i32 v3, v2, 0, 8
; GFX7-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX7-NEXT: v_cmp_lt_i32_e32 vcc, v3, v0
-; GFX7-NEXT: v_bfe_i32 v0, v1, 0, 8
-; GFX7-NEXT: v_cmp_lt_i32_e64 s[4:5], 0, v0
-; GFX7-NEXT: s_xor_b64 s[4:5], s[4:5], vcc
+; GFX7-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX7-NEXT: v_cmp_lt_i32_e32 vcc, v0, v1
+; GFX7-NEXT: v_bfe_i32 v0, v2, 0, 8
+; GFX7-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v0
+; GFX7-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v2, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
@@ -848,12 +848,12 @@ define i8 @s_ssubo_i8(i8 %a, i8 %b) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u16_e32 v2, v0, v1
-; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 8
; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, v3, v0
-; GFX8-NEXT: v_bfe_i32 v0, v1, 0, 8
-; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], 0, v0
-; GFX8-NEXT: s_xor_b64 s[4:5], s[4:5], vcc
+; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, v0, v1
+; GFX8-NEXT: v_bfe_i32 v0, v2, 0, 8
+; GFX8-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v0
+; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX8-NEXT: v_sub_u16_e32 v0, v2, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -862,10 +862,10 @@ define i8 @s_ssubo_i8(i8 %a, i8 %b) {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_sub_u16_e32 v2, v0, v1
-; GFX9-NEXT: v_cmp_lt_i32_sdwa s[4:5], sext(v2), sext(v0) src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX9-NEXT: v_cmp_lt_i32_sdwa s[4:5], sext(v0), sext(v1) src0_sel:BYTE_0 src1_sel:BYTE_0
; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_cmp_gt_i32_sdwa s[6:7], sext(v1), v0 src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: s_xor_b64 s[4:5], s[6:7], s[4:5]
+; GFX9-NEXT: v_cmp_lt_i32_sdwa s[6:7], sext(v2), v0 src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7]
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX9-NEXT: v_sub_u16_e32 v0, v2, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -882,12 +882,12 @@ define i7 @s_ssubo_i7(i7 %a, i7 %b) {
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_sub_i32_e32 v2, vcc, v0, v1
-; GFX7-NEXT: v_bfe_i32 v3, v2, 0, 7
; GFX7-NEXT: v_bfe_i32 v0, v0, 0, 7
-; GFX7-NEXT: v_cmp_lt_i32_e32 vcc, v3, v0
-; GFX7-NEXT: v_bfe_i32 v0, v1, 0, 7
-; GFX7-NEXT: v_cmp_lt_i32_e64 s[4:5], 0, v0
-; GFX7-NEXT: s_xor_b64 s[4:5], s[4:5], vcc
+; GFX7-NEXT: v_bfe_i32 v1, v1, 0, 7
+; GFX7-NEXT: v_cmp_lt_i32_e32 vcc, v0, v1
+; GFX7-NEXT: v_bfe_i32 v0, v2, 0, 7
+; GFX7-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v0
+; GFX7-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v2, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
@@ -896,12 +896,12 @@ define i7 @s_ssubo_i7(i7 %a, i7 %b) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u16_e32 v2, v0, v1
-; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 7
; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 7
-; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, v3, v0
-; GFX8-NEXT: v_bfe_i32 v0, v1, 0, 7
-; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], 0, v0
-; GFX8-NEXT: s_xor_b64 s[4:5], s[4:5], vcc
+; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 7
+; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, v0, v1
+; GFX8-NEXT: v_bfe_i32 v0, v2, 0, 7
+; GFX8-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v0
+; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX8-NEXT: v_sub_u16_e32 v0, v2, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -910,12 +910,12 @@ define i7 @s_ssubo_i7(i7 %a, i7 %b) {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_sub_u16_e32 v2, v0, v1
-; GFX9-NEXT: v_bfe_i32 v3, v2, 0, 7
; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 7
-; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, v3, v0
-; GFX9-NEXT: v_bfe_i32 v0, v1, 0, 7
-; GFX9-NEXT: v_cmp_lt_i32_e64 s[4:5], 0, v0
-; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], vcc
+; GFX9-NEXT: v_bfe_i32 v1, v1, 0, 7
+; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, v0, v1
+; GFX9-NEXT: v_bfe_i32 v0, v2, 0, 7
+; GFX9-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v0
+; GFX9-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX9-NEXT: v_sub_u16_e32 v0, v2, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -1005,9 +1005,9 @@ define amdgpu_ps i32 @ssubo_i32_sv(i32 inreg %a, i32 %b) {
; GFX7-LABEL: ssubo_i32_sv:
; GFX7: ; %bb.0:
; GFX7-NEXT: v_sub_i32_e32 v1, vcc, s0, v0
-; GFX7-NEXT: v_cmp_gt_i32_e32 vcc, s0, v1
-; GFX7-NEXT: v_cmp_lt_i32_e64 s[0:1], 0, v0
-; GFX7-NEXT: s_xor_b64 s[0:1], s[0:1], vcc
+; GFX7-NEXT: v_cmp_lt_i32_e32 vcc, s0, v0
+; GFX7-NEXT: v_cmp_gt_i32_e64 s[0:1], 0, v1
+; GFX7-NEXT: s_xor_b64 s[0:1], vcc, s[0:1]
; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v1, v0
; GFX7-NEXT: v_readfirstlane_b32 s0, v0
@@ -1016,9 +1016,9 @@ define amdgpu_ps i32 @ssubo_i32_sv(i32 inreg %a, i32 %b) {
; GFX8-LABEL: ssubo_i32_sv:
; GFX8: ; %bb.0:
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s0, v0
-; GFX8-NEXT: v_cmp_gt_i32_e32 vcc, s0, v1
-; GFX8-NEXT: v_cmp_lt_i32_e64 s[0:1], 0, v0
-; GFX8-NEXT: s_xor_b64 s[0:1], s[0:1], vcc
+; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, s0, v0
+; GFX8-NEXT: v_cmp_gt_i32_e64 s[0:1], 0, v1
+; GFX8-NEXT: s_xor_b64 s[0:1], vcc, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v1, v0
; GFX8-NEXT: v_readfirstlane_b32 s0, v0
@@ -1027,9 +1027,9 @@ define amdgpu_ps i32 @ssubo_i32_sv(i32 inreg %a, i32 %b) {
; GFX9-LABEL: ssubo_i32_sv:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_sub_u32_e32 v1, s0, v0
-; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, s0, v1
-; GFX9-NEXT: v_cmp_lt_i32_e64 s[0:1], 0, v0
-; GFX9-NEXT: s_xor_b64 s[0:1], s[0:1], vcc
+; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, s0, v0
+; GFX9-NEXT: v_cmp_gt_i32_e64 s[0:1], 0, v1
+; GFX9-NEXT: s_xor_b64 s[0:1], vcc, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GFX9-NEXT: v_sub_u32_e32 v0, v1, v0
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
@@ -1046,12 +1046,12 @@ define amdgpu_ps i16 @ssubo_i16_sv(i16 inreg %a, i16 %b) {
; GFX7-LABEL: ssubo_i16_sv:
; GFX7: ; %bb.0:
; GFX7-NEXT: v_sub_i32_e32 v1, vcc, s0, v0
-; GFX7-NEXT: v_bfe_i32 v2, v1, 0, 16
; GFX7-NEXT: s_sext_i32_i16 s0, s0
; GFX7-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX7-NEXT: v_cmp_gt_i32_e32 vcc, s0, v2
-; GFX7-NEXT: v_cmp_lt_i32_e64 s[0:1], 0, v0
-; GFX7-NEXT: s_xor_b64 s[0:1], s[0:1], vcc
+; GFX7-NEXT: v_cmp_lt_i32_e32 vcc, s0, v0
+; GFX7-NEXT: v_bfe_i32 v0, v1, 0, 16
+; GFX7-NEXT: v_cmp_gt_i32_e64 s[0:1], 0, v0
+; GFX7-NEXT: s_xor_b64 s[0:1], vcc, s[0:1]
; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v1, v0
; GFX7-NEXT: v_readfirstlane_b32 s0, v0
@@ -1060,9 +1060,9 @@ define amdgpu_ps i16 @ssubo_i16_sv(i16 inreg %a, i16 %b) {
; GFX8-LABEL: ssubo_i16_sv:
; GFX8: ; %bb.0:
; GFX8-NEXT: v_sub_u16_e32 v1, s0, v0
-; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, s0, v1
-; GFX8-NEXT: v_cmp_lt_i16_e64 s[0:1], 0, v0
-; GFX8-NEXT: s_xor_b64 s[0:1], s[0:1], vcc
+; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, s0, v0
+; GFX8-NEXT: v_cmp_gt_i16_e64 s[0:1], 0, v1
+; GFX8-NEXT: s_xor_b64 s[0:1], vcc, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GFX8-NEXT: v_sub_u16_e32 v0, v1, v0
; GFX8-NEXT: v_readfirstlane_b32 s0, v0
@@ -1071,9 +1071,9 @@ define amdgpu_ps i16 @ssubo_i16_sv(i16 inreg %a, i16 %b) {
; GFX9-LABEL: ssubo_i16_sv:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_sub_u16_e32 v1, s0, v0
-; GFX9-NEXT: v_cmp_gt_i16_e32 vcc, s0, v1
-; GFX9-NEXT: v_cmp_lt_i16_e64 s[0:1], 0, v0
-; GFX9-NEXT: s_xor_b64 s[0:1], s[0:1], vcc
+; GFX9-NEXT: v_cmp_lt_i16_e32 vcc, s0, v0
+; GFX9-NEXT: v_cmp_gt_i16_e64 s[0:1], 0, v1
+; GFX9-NEXT: s_xor_b64 s[0:1], vcc, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GFX9-NEXT: v_sub_u16_e32 v0, v1, v0
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv32.mir
index 5288bb5e87011..35f20117b26cd 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv32.mir
@@ -232,9 +232,9 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[SUB]](s32), [[COPY]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY1]](s32), [[C]]
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ICMP1]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[SUB]](s32), [[C]]
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ICMP]], [[ICMP1]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK-NEXT: $x10 = COPY [[COPY2]](s32)
; CHECK-NEXT: $x11 = COPY [[XOR]](s32)
@@ -266,15 +266,15 @@ body: |
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY3]]
; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP]]
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB]](s32), [[COPY]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[SUB2]](s32), [[COPY1]]
- ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB2]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY1]](s32), [[COPY3]]
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), [[ICMP1]], [[ICMP2]]
- ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY2]](s32), [[C]]
- ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY3]](s32), [[C]]
- ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]]
+ ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB]](s32), [[C]]
+ ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[SUB2]](s32), [[C]]
+ ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB2]](s32), [[C]]
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s32), [[ICMP4]], [[ICMP5]]
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SELECT1]], [[SELECT]]
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SELECT]], [[SELECT1]]
; CHECK-NEXT: $x10 = COPY [[SUB]](s32)
; CHECK-NEXT: $x11 = COPY [[SUB2]](s32)
; CHECK-NEXT: $x12 = COPY [[XOR]](s32)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv64.mir
index eed1aac8f6c13..22fe335b3ee35 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv64.mir
@@ -246,9 +246,9 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]]
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[SUB]](s64), [[COPY]]
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[COPY1]](s64), [[C]]
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ICMP1]], [[ICMP]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[SUB]](s64), [[C]]
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ICMP]], [[ICMP1]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[SUB]](s64)
; CHECK-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-NEXT: $x11 = COPY [[XOR]](s64)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv32.mir
index 6e6a47cc91623..d7b1fac22de74 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv32.mir
@@ -272,9 +272,9 @@ body: |
; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[SUB]](s32), [[COPY]]
- ; RV32I-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY1]](s32), [[C]]
- ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ICMP1]], [[ICMP]]
+ ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
+ ; RV32I-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[SUB]](s32), [[C]]
+ ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ICMP]], [[ICMP1]]
; RV32I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; RV32I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY2]], [[C1]](s32)
@@ -325,15 +325,15 @@ body: |
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY3]]
; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP]]
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB]](s32), [[COPY]]
- ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[SUB2]](s32), [[COPY1]]
- ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB2]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY1]](s32), [[COPY3]]
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), [[ICMP1]], [[ICMP2]]
- ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY2]](s32), [[C]]
- ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY3]](s32), [[C]]
- ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]]
+ ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SUB]](s32), [[C]]
+ ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[SUB2]](s32), [[C]]
+ ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SUB2]](s32), [[C]]
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s32), [[ICMP4]], [[ICMP5]]
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SELECT1]], [[SELECT]]
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SELECT]], [[SELECT1]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SUB2]], [[C1]](s32)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv64.mir
index fa7da8243e6b7..bd891ccc26b03 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv64.mir
@@ -281,9 +281,9 @@ body: |
; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]]
; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[SUB]](s64), [[COPY]]
- ; RV64I-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[COPY1]](s64), [[C]]
- ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ICMP1]], [[ICMP]]
+ ; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
+ ; RV64I-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[SUB]](s64), [[C]]
+ ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ICMP]], [[ICMP1]]
; RV64I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[SUB]](s64)
; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY2]], [[C1]](s64)
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/signed_arithmetic_overflow.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/signed_arithmetic_overflow.ll
index 2dcc1f2ae6c2f..ae721ba6ce269 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/signed_arithmetic_overflow.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/signed_arithmetic_overflow.ll
@@ -33,9 +33,9 @@ entry:
; CHECK: %[[#A2:]] = OpFunctionParameter %[[#Int]]
; CHECK: %[[#B2:]] = OpFunctionParameter %[[#Int]]
; CHECK: %[[#Res2:]] = OpISub %[[#Int]] %[[#A2]] %[[#B2]]
-; CHECK: %[[#ResLtA2:]] = OpSLessThan %[[#Bool]] %[[#Res2]] %[[#A2]]
-; CHECK: %[[#BGt0:]] = OpSGreaterThan %[[#Bool]] %[[#B2]] %[[#NullInt]]
-; CHECK: %[[#Overflow2:]] = OpLogicalNotEqual %[[#Bool]] %[[#BGt0]] %[[#ResLtA2]]
+; CHECK: %[[#CmpAB2:]] = OpSLessThan %[[#Bool]] %[[#A2]] %[[#B2]]
+; CHECK: %[[#ResLt02:]] = OpSLessThan %[[#Bool]] %[[#Res2]] %[[#NullInt]]
+; CHECK: %[[#Overflow2:]] = OpLogicalNotEqual %[[#Bool]] %[[#CmpAB2]] %[[#ResLt02]]
; CHECK: OpReturn
define spir_func void @test_ssub_overflow(ptr %out_result, ptr %out_overflow, i32 %a, i32 %b) {
entry:
@@ -71,9 +71,9 @@ entry:
; CHECK: %[[#A4:]] = OpFunctionParameter %[[#V2Int]]
; CHECK: %[[#B4:]] = OpFunctionParameter %[[#V2Int]]
; CHECK: %[[#Res4:]] = OpISub %[[#V2Int]] %[[#A4]] %[[#B4]]
-; CHECK: %[[#ResLtA4:]] = OpSLessThan %[[#V2Bool]] %[[#Res4]] %[[#A4]]
-; CHECK: %[[#BGt04:]] = OpSGreaterThan %[[#V2Bool]] %[[#B4]] %[[#NullV2Int]]
-; CHECK: %[[#Overflow4:]] = OpLogicalNotEqual %[[#V2Bool]] %[[#BGt04]] %[[#ResLtA4]]
+; CHECK: %[[#CmpAB4:]] = OpSLessThan %[[#V2Bool]] %[[#A4]] %[[#B4]]
+; CHECK: %[[#ResLt04:]] = OpSLessThan %[[#V2Bool]] %[[#Res4]] %[[#NullV2Int]]
+; CHECK: %[[#Overflow4:]] = OpLogicalNotEqual %[[#V2Bool]] %[[#CmpAB4]] %[[#ResLt04]]
; CHECK: OpReturn
define spir_func void @test_ssub_overflow_v2i32(ptr %out_result, ptr %out_overflow, <2 x i32> %a, <2 x i32> %b) {
entry:
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