[llvm] [AMDGPU] Use WriteSALUDummy for v_div_scale* (PR #191670)
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Sat Apr 11 14:54:05 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Jeffrey Byrnes (jrbyrnes)
<details>
<summary>Changes</summary>
This uses the new HWWriteRes for v_div_scale*
For an explanation of why we want to do this , see https://github.com/llvm/llvm-project/pull/190095 . In short, the scheduler will not try to cover the full latency of the instructions without this new modelling.
For a clear example of this, see the changes to llvm/test/CodeGen/AMDGPU/schedmodel-dummywrite.mir in the git log of this PR.
---
Patch is 206.67 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/191670.diff
17 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/VOP3Instructions.td (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll (+196-196)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll (+120-120)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll (+198-198)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/bf16.ll (+4-5)
- (modified) llvm/test/CodeGen/AMDGPU/dagcombine-select.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/fdiv.f16.ll (+13-13)
- (modified) llvm/test/CodeGen/AMDGPU/fdiv.ll (+263-263)
- (modified) llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll (+45-157)
- (modified) llvm/test/CodeGen/AMDGPU/freeze-binary.ll (+88-88)
- (modified) llvm/test/CodeGen/AMDGPU/repeated-divisor.ll (+43-43)
- (modified) llvm/test/CodeGen/AMDGPU/rsq.f32-safe.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/rsq.f64.ll (+33-33)
- (added) llvm/test/CodeGen/AMDGPU/schedmodel-dummywrite.mir (+59)
- (modified) llvm/test/tools/llvm-mca/AMDGPU/gfx10-double.s (+5-5)
- (modified) llvm/test/tools/llvm-mca/AMDGPU/gfx11-double.s (+5-5)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index e157fe888cf7a..41e76063386ec 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -356,11 +356,11 @@ def : GCNPat <
>;
let mayRaiseFPException = 0 in { // Seems suspicious but manual doesn't say it does.
- let SchedRW = [WriteFloatFMA, WriteSALU] in
+ let SchedRW = [WriteFloatFMA, WriteSALUDummy] in
defm V_DIV_SCALE_F32 : VOP3Inst_Pseudo_Wrapper <"v_div_scale_f32", VOP3b_F32_I1_F32_F32_F32> ;
// Double precision division pre-scale.
- let SchedRW = [WriteDouble, WriteSALU], FPDPRounding = 1, IsDPMACCInstruction = 1 in
+ let SchedRW = [WriteDouble, WriteSALUDummy], FPDPRounding = 1, IsDPMACCInstruction = 1 in
defm V_DIV_SCALE_F64 : VOP3Inst <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64>;
} // End mayRaiseFPException = 0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
index bb888fe614ce8..8b91c21e27286 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
@@ -759,18 +759,18 @@ define <2 x half> @v_fdiv_v2f16(<2 x half> %a, <2 x half> %b) {
; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6
; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v5, v7
; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6
+; GFX6-IEEE-NEXT: v_div_scale_f32 v6, s[4:5], v1, v1, v0
+; GFX6-IEEE-NEXT: v_rcp_f32_e32 v8, v6
; GFX6-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7
-; GFX6-IEEE-NEXT: v_div_scale_f32 v5, s[4:5], v1, v1, v0
-; GFX6-IEEE-NEXT: v_rcp_f32_e32 v6, v5
; GFX6-IEEE-NEXT: v_div_fixup_f32 v2, v4, v3, v2
; GFX6-IEEE-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
-; GFX6-IEEE-NEXT: v_fma_f32 v4, -v5, v6, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v4, v4, v6, v6
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v3, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v7, -v5, v6, v3
-; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6
-; GFX6-IEEE-NEXT: v_fma_f32 v3, -v5, v6, v3
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX6-IEEE-NEXT: v_fma_f32 v4, -v6, v8, 1.0
+; GFX6-IEEE-NEXT: v_fma_f32 v4, v4, v8, v8
+; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-IEEE-NEXT: v_fma_f32 v7, -v6, v5, v3
+; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v4, v5
+; GFX6-IEEE-NEXT: v_fma_f32 v3, -v6, v5, v3
+; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v5
; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v3, v1, v0
; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v2
@@ -1144,18 +1144,18 @@ define <2 x half> @v_fdiv_v2f16_ulp25(<2 x half> %a, <2 x half> %b) {
; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6
; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v5, v7
; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6
+; GFX6-IEEE-NEXT: v_div_scale_f32 v6, s[4:5], v1, v1, v0
+; GFX6-IEEE-NEXT: v_rcp_f32_e32 v8, v6
; GFX6-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7
-; GFX6-IEEE-NEXT: v_div_scale_f32 v5, s[4:5], v1, v1, v0
-; GFX6-IEEE-NEXT: v_rcp_f32_e32 v6, v5
; GFX6-IEEE-NEXT: v_div_fixup_f32 v2, v4, v3, v2
; GFX6-IEEE-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
-; GFX6-IEEE-NEXT: v_fma_f32 v4, -v5, v6, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v4, v4, v6, v6
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v3, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v7, -v5, v6, v3
-; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6
-; GFX6-IEEE-NEXT: v_fma_f32 v3, -v5, v6, v3
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX6-IEEE-NEXT: v_fma_f32 v4, -v6, v8, 1.0
+; GFX6-IEEE-NEXT: v_fma_f32 v4, v4, v8, v8
+; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-IEEE-NEXT: v_fma_f32 v7, -v6, v5, v3
+; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v4, v5
+; GFX6-IEEE-NEXT: v_fma_f32 v3, -v6, v5, v3
+; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v5
; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v3, v1, v0
; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v2
@@ -1454,24 +1454,24 @@ define <2 x half> @v_rcp_v2f16(<2 x half> %x) {
; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, 1.0
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, 1.0, v1, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
-; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5
-; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
-; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v0, v0, 1.0
-; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3
+; GFX6-IEEE-NEXT: v_div_scale_f32 v5, s[4:5], v0, v0, 1.0
+; GFX6-IEEE-NEXT: v_rcp_f32_e32 v6, v5
+; GFX6-IEEE-NEXT: v_fma_f32 v7, -v2, v3, 1.0
+; GFX6-IEEE-NEXT: v_fma_f32 v3, v7, v3, v3
+; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v4, v3
+; GFX6-IEEE-NEXT: v_fma_f32 v8, -v2, v7, v4
+; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v3, v7
+; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v7, v4
+; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v7
+; GFX6-IEEE-NEXT: v_fma_f32 v3, -v5, v6, 1.0
; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
; GFX6-IEEE-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v5, -v3, v4, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v2, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v5, v2
-; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v4, v5
-; GFX6-IEEE-NEXT: v_fma_f32 v2, -v3, v5, v2
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-IEEE-NEXT: v_fma_f32 v3, v3, v6, v6
+; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX6-IEEE-NEXT: v_fma_f32 v6, -v5, v4, v2
+; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v3, v4
+; GFX6-IEEE-NEXT: v_fma_f32 v2, -v5, v4, v2
+; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v4
; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v1
@@ -1741,24 +1741,24 @@ define <2 x half> @v_neg_rcp_v2f16(<2 x half> %x) {
; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -1.0
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, -1.0, v1, -1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
-; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5
-; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
-; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v0, v0, -1.0
-; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3
+; GFX6-IEEE-NEXT: v_div_scale_f32 v5, s[4:5], v0, v0, -1.0
+; GFX6-IEEE-NEXT: v_rcp_f32_e32 v6, v5
+; GFX6-IEEE-NEXT: v_fma_f32 v7, -v2, v3, 1.0
+; GFX6-IEEE-NEXT: v_fma_f32 v3, v7, v3, v3
+; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v4, v3
+; GFX6-IEEE-NEXT: v_fma_f32 v8, -v2, v7, v4
+; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v3, v7
+; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v7, v4
+; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v7
+; GFX6-IEEE-NEXT: v_fma_f32 v3, -v5, v6, 1.0
; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v1, -1.0
; GFX6-IEEE-NEXT: v_div_scale_f32 v2, vcc, -1.0, v0, -1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v5, -v3, v4, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v2, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v5, v2
-; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v4, v5
-; GFX6-IEEE-NEXT: v_fma_f32 v2, -v3, v5, v2
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-IEEE-NEXT: v_fma_f32 v3, v3, v6, v6
+; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX6-IEEE-NEXT: v_fma_f32 v6, -v5, v4, v2
+; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v3, v4
+; GFX6-IEEE-NEXT: v_fma_f32 v2, -v5, v4, v2
+; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v4
; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, -1.0
; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v1
@@ -2029,24 +2029,24 @@ define <2 x half> @v_rcp_v2f16_fabs(<2 x half> %x) {
; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, 1.0
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, 1.0, v1, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
-; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5
-; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
-; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v0, v0, 1.0
-; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3
+; GFX6-IEEE-NEXT: v_div_scale_f32 v5, s[4:5], v0, v0, 1.0
+; GFX6-IEEE-NEXT: v_rcp_f32_e32 v6, v5
+; GFX6-IEEE-NEXT: v_fma_f32 v7, -v2, v3, 1.0
+; GFX6-IEEE-NEXT: v_fma_f32 v3, v7, v3, v3
+; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v4, v3
+; GFX6-IEEE-NEXT: v_fma_f32 v8, -v2, v7, v4
+; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v3, v7
+; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v7, v4
+; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v7
+; GFX6-IEEE-NEXT: v_fma_f32 v3, -v5, v6, 1.0
; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
; GFX6-IEEE-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v5, -v3, v4, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v2, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v5, v2
-; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v4, v5
-; GFX6-IEEE-NEXT: v_fma_f32 v2, -v3, v5, v2
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-IEEE-NEXT: v_fma_f32 v3, v3, v6, v6
+; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX6-IEEE-NEXT: v_fma_f32 v6, -v5, v4, v2
+; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v3, v4
+; GFX6-IEEE-NEXT: v_fma_f32 v2, -v5, v4, v2
+; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v4
; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v1
@@ -2329,24 +2329,24 @@ define <2 x half> @v_neg_rcp_v2f16_fabs(<2 x half> %x) {
; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -1.0
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, -1.0, v1, -1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
-; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5
-; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
-; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v0, v0, -1.0
-; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3
+; GFX6-IEEE-NEXT: v_div_scale_f32 v5, s[4:5], v0, v0, -1.0
+; GFX6-IEEE-NEXT: v_rcp_f32_e32 v6, v5
+; GFX6-IEEE-NEXT: v_fma_f32 v7, -v2, v3, 1.0
+; GFX6-IEEE-NEXT: v_fma_f32 v3, v7, v3, v3
+; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v4, v3
+; GFX6-IEEE-NEXT: v_fma_f32 v8, -v2, v7, v4
+; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v3, v7
+; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v7, v4
+; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v7
+; GFX6-IEEE-NEXT: v_fma_f32 v3, -v5, v6, 1.0
; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v1, -1.0
; GFX6-IEEE-NEXT: v_div_scale_f32 v2, vcc, -1.0, v0, -1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v5, -v3, v4, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v2, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v5, v2
-; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v4, v5
-; GFX6-IEEE-NEXT: v_fma_f32 v2, -v3, v5, v2
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-IEEE-NEXT: v_fma_f32 v3, v3, v6, v6
+; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX6-IEEE-NEXT: v_fma_f32 v6, -v5, v4, v2
+; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v3, v4
+; GFX6-IEEE-NEXT: v_fma_f32 v2, -v5, v4, v2
+; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v4
; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, -1.0
; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v1
@@ -2628,24 +2628,24 @@ define <2 x half> @v_rcp_v2f16_arcp(<2 x half> %x) {
; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, 1.0
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, 1.0, v1, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
-; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5
-; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
-; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v0, v0, 1.0
-; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3
+; GFX6-IEEE-NEXT: v_div_scale_f32 v5, s[4:5], v0, v0, 1.0
+; GFX6-IEEE-NEXT: v_rcp_f32_e32 v6, v5
+; GFX6-IEEE-NEXT: v_fma_f32 v7, -v2, v3, 1.0
+; GFX6-IEEE-NEXT: v_fma_f32 v3, v7, v3, v3
+; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v4, v3
+; GFX6-IEEE-NEXT: v_fma_f32 v8, -v2, v7, v4
+; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v3, v7
+; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v7, v4
+; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v7
+; GFX6-IEEE-NEXT: v_fma_f32 v3, -v5, v6, 1.0
; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
; GFX6-IEEE-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v5, -v3, v4, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v2, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v5, v2
-; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v4, v5
-; GFX6-IEEE-NEXT: v_fma_f32 v2, -v3, v5, v2
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-IEEE-NEXT: v_fma_f32 v3, v3, v6, v6
+; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX6-IEEE-NEXT: v_fma_f32 v6, -v5, v4, v2
+; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v3, v4
+; GFX6-IEEE-NEXT: v_fma_f32 v2, -v5, v4, v2
+; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v4
; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v1
@@ -2791,24 +2791,24 @@ define <2 x half> @v_rcp_v2f16_ulp25(<2 x half> %x) {
; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, 1.0
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2
; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, 1.0, v1, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
-; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5
-; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
-; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v0, v0, 1.0
-; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3
+; GFX6-IEEE-NEXT: v_div_scale_f32 v5, s[4:5], v0, v0, 1.0
+; GFX6-IEEE-NEXT: v_rcp_f32_e32 v6, v5
+; GFX6-IEEE-NEXT: v_fma_f32 v7, -v2, v3, 1.0
+; GFX6-IEEE-NEXT: v_fma_f32 v3, v7, v3, v3
+; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v4, v3
+; GFX6-IEEE-NEXT: v_fma_f32 v8, -v2, v7, v4
+; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v3, v7
+; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v7, v4
+; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v7
+; GFX6-IEEE-NEXT: v_fma_f32 v3, -v5, v6, 1.0
; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
; GFX6-IEEE-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v5, -v3, v4, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v2, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v5, v2
-; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v4, v5
-; GFX6-IEEE-NEXT: v_fma_f32 v2, -v3, v5, v2
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-IEEE-NEXT: v_fma_f32 v3, v3, v6, v6
+; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX6-IEEE-NEXT: v_fma_f32 v6, -v5, v4, v2
+; GFX6-IEEE-NEXT: v_fma_f32 v4, v6, v3, v4
+; GFX6-IEEE-NEXT: v_fma_f32 v2, -v5, v4, v2
+; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v4
; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v1
@@ -3153,18 +3153,18 @@ define <2 x half> @v_fdiv_v2f16_arcp_ulp25(<2 x half> %a, <2 x half> %b) {
; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6
; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v5, v7
; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6
+; GFX6-IEEE-NEXT: v_div_scale_f32 v6, s[4:5], v1, v1, v0
+; GFX6-IEEE-NEXT: v_rcp_f32_e32 v8, v6
; GFX6-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7
-; GFX6-IEEE-NEXT: v_div_scale_f32 v5, s[4:5], v1, v1, v0
-; GFX6-IEEE-NEXT: v_rcp_f32_e32 v6, v5
; GFX6-IEEE-NEXT: v_div_fixup_f32 v2, v4, v3, v2
; GFX6-IEEE-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
-; GFX6-IEEE-NEXT: v_fma_f32 v4, -v5, v6, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v4, v4, v6, v6
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v3, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v7, -v5, v6, v3
-; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6
-; GFX6-IEEE-NEXT: v_fma_f32 v3, -v5, v6, v3
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX6-IEEE-NEXT: v_fma_f32 v4, -v6, v8, 1.0
+; GFX6-IEEE-NEXT: v_fma_f32 v4, v4, v8, v8
+; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-IEEE-NEXT: v_fma_f32 v7, -v6, v5, v3
+; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v4, v5
+; GFX6-IEEE-NEXT: v_fma_f32 v3, -v6, v5, v3
+; GFX6-IEEE-NEXT: v_div_fmas_f32 v3, v3, v4, v5
; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v3, v1, v0
; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v2
@@ -3620,32 +3620,32 @@ define amdgpu_ps i32 @s_fdiv_v2f16(i32 inreg %a.arg, i32 inreg %b.arg) {
; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v1, s1
; GFX6-IEEE-NEXT: s_lshr_b32 s0, s0, 16
; GFX6-IEEE-NEXT: s_lshr_b32 s1, s1, 16
+; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v4, s0
; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[2:3], v1, v1, v0
; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2
-; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
-; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
-; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5
-; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
-; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v4, s0
-; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v6, s1
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-IEEE-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0
+; GFX6-IEEE-NEXT: v_cvt_f32_f16_e32 v7, s1
+; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v3, 1.0
+; GFX6-IEEE-NEXT: v_fma_f32 v3, v6, v3, v3
+; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v5, v3
+; GFX6-IEEE-NEXT: v_fma_f32 v8, -v2, v6, v5
+; GFX6-IEEE-NEXT: v_fma_f32 v6, v8, v3, v6
+; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v6, v5
+; GFX6-IEEE-NEXT: v_div_scale_f32 v5, s[0:1], v7, v7, v4
+; GFX6-IEEE-NEXT: v_rcp_f32_e32 v8, v5
+; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v6
; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0
-; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[0:1], v6, v6, v4
-; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v3
-; GFX6-IEEE-NEXT: v_div_scale_f32 v1, vcc, v4, v6, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v2, -v3, v5, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v2, v2, v5, v5
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v1, v2
-; GFX6-IEEE-NEXT: v_fma_f32 v7, -v3, v5, v1
-; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v2, v5
-; GFX6-IEEE-NEXT: v_fma_f32 v1, -v3, v5, v1
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v5
-; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v1, v6, v4
+; GFX6-IEEE-NEXT: v_div_scale_f32 v1, vcc, v4, v7, v4
+; GFX6-IEEE-NEXT: v_fma_f32 v2, -v5, v8, 1.0
+; GFX6-IEEE-NEXT: v_fma_f32 v2, v2, v8, v8
+; GFX6-IEEE-NEXT: v_mul_f32_e32 v3, v1, v2
+; GFX6-IEEE-NEXT: v_fma_f32 v6, -v5, v3, v1
+; GFX6-IEEE-NEXT: v_fma_f32 v3, v6, v2, v3
+; GFX6-IEEE-NEXT: v_fma_f32 v1, -v5, v3, v1
+; GFX6-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v3
+; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v1, v7, v4
; GFX6-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX6-IEEE-NEXT: v_cvt_f16_f32_...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/191670
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