[llvm] [X86] Convert VPABSQ NonVLX patterns to use avx512_unary_lowering helper (PR #191648)

[Simon Pilgrim via llvm-commits]

https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/191648

Move avx512_unary_lowering so we can avoid manually writing the XMM/YMM->ZMM widening for NonVLX targets

Adds some missing comments for instruction classes as well

>From 684bec19106721a6bf016ec5b9dc5fbc78e96c6c Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Sat, 11 Apr 2026 18:13:41 +0100
Subject: [PATCH] [X86] Convert VPABSQ NonVLX patterns to use
 avx512_unary_lowering helper

Move avx512_unary_lowering so we can avoid manually writing the XMM/YMM->ZMM widening for NonVLX targets

Adds some missing comments for instruction classes as well
---
 llvm/lib/Target/X86/X86InstrAVX512.td | 39 ++++++++++++++-------------
 1 file changed, 20 insertions(+), 19 deletions(-)

diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index 400cdcb9251de..82c36b6adcc42 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -11312,23 +11312,6 @@ multiclass avx512_unary_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
                                     HasBWI>;
 }
 
-defm VPABS : avx512_unary_rm_vl_all<0x1C, 0x1D, 0x1E, 0x1F, "vpabs", abs,
-                                    SchedWriteVecALU>;
-
-// VPABS: Use 512bit version to implement 128/256 bit in case NoVLX.
-let Predicates = [HasAVX512, NoVLX] in {
-  def : Pat<(v4i64 (abs VR256X:$src)),
-            (EXTRACT_SUBREG
-                (VPABSQZrr
-                    (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)),
-             sub_ymm)>;
-  def : Pat<(v2i64 (abs VR128X:$src)),
-            (EXTRACT_SUBREG
-                (VPABSQZrr
-                    (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm)),
-             sub_xmm)>;
-}
-
 // Use 512bit version to implement 128/256 bit.
 multiclass avx512_unary_lowering<string InstrStr, SDNode OpNode,
                                  AVX512VLVectorVTInfo _, Predicate prd> {
@@ -11351,13 +11334,31 @@ multiclass avx512_unary_lowering<string InstrStr, SDNode OpNode,
   }
 }
 
-defm VPLZCNT    : avx512_unary_rm_vl_dq<0x44, 0x44, "vplzcnt", ctlz,
-                                        SchedWriteVecIMul, HasCDI>;
+//===---------------------------------------------------------------------===//
+// Integer Absolute - VPABSQ
+//===---------------------------------------------------------------------===//
+
+defm VPABS : avx512_unary_rm_vl_all<0x1C, 0x1D, 0x1E, 0x1F, "vpabs", abs,
+                                    SchedWriteVecALU>;
+
+// VPABS: Use 512bit version to implement 128/256 bit in case NoVLX.
+defm : avx512_unary_lowering<"VPABSQ", abs, avx512vl_i64_info, HasAVX512>;
+
+//===---------------------------------------------------------------------===//
+// Test elements for earlier matching elements - VPCONFLICTD and VPCONFLICTQ
+//===---------------------------------------------------------------------===//
 
 // FIXME: Is there a better scheduler class for VPCONFLICT?
 defm VPCONFLICT : avx512_unary_rm_vl_dq<0xC4, 0xC4, "vpconflict", X86Conflict,
                                         SchedWriteVecALU, HasCDI>;
 
+//===---------------------------------------------------------------------===//
+// Counts number of leading zeros - VPLZCNTD and VPLZCNTQ
+//===---------------------------------------------------------------------===//
+
+defm VPLZCNT    : avx512_unary_rm_vl_dq<0x44, 0x44, "vplzcnt", ctlz,
+                                        SchedWriteVecIMul, HasCDI>;
+
 // VPLZCNT: Use 512bit version to implement 128/256 bit in case NoVLX.
 defm : avx512_unary_lowering<"VPLZCNTQ", ctlz, avx512vl_i64_info, HasCDI>;
 defm : avx512_unary_lowering<"VPLZCNTD", ctlz, avx512vl_i32_info, HasCDI>;