[llvm] [RISCV] Add missing Zvfbfa isel patterns for VFSLIDE1UP/DOWN. (PR #191578)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 10 17:15:08 PDT 2026
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/191578
None
>From 8c548a511063c8507462e9921f5529de1cd9ee95 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 10 Apr 2026 17:14:14 -0700
Subject: [PATCH] [RISCV] Add missing Zvfbfa isel patterns for VFSLIDE1UP/DOWN.
---
.../Target/RISCV/RISCVInstrInfoVVLPatterns.td | 6 ++-
.../rvv/fixed-vectors-fp-buildvec-bf16.ll | 53 +++++++++++++++++++
2 files changed, 57 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 0d5ba476cc88a..2a99492bc5596 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -1943,12 +1943,14 @@ multiclass VPatSlide1VL_VX<SDNode vop, string instruction_name> {
}
multiclass VPatSlide1VL_VF<SDNode vop, string instruction_name> {
- foreach vti = AllFloatVectors in {
+ foreach vti = AllFloatAndBF16Vectors in {
let Predicates = GetVTypePredicates<vti>.Predicates in {
def : Pat<(vti.Vector (vop (vti.Vector vti.RegClass:$rs3),
(vti.Vector vti.RegClass:$rs1),
vti.Scalar:$rs2, (vti.Mask VMV0:$vm), VLOpFrag)),
- (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_MASK")
+ (!cast<Instruction>(instruction_name#
+ !if(!eq(vti.Scalar, bf16), "_ALT", "")#
+ "_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_MASK")
vti.RegClass:$rs3, vti.RegClass:$rs1, vti.Scalar:$rs2,
(vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TU_MU)>;
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec-bf16.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec-bf16.ll
index 9bb3f4a976ab0..85f9fc990ec2c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec-bf16.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec-bf16.ll
@@ -3,6 +3,8 @@
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVFBFMIN,RV64-NO-ZFBFMIN
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfbfmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVFBFMIN,RV32-ZFBFMIN
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfbfmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVFBFMIN,RV64-ZFBFMIN
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+experimental-zvfbfa -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVFBFA
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+experimental-zvfbfa -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVFBFA
define <4 x bfloat> @splat_idx_v4bf16(<4 x bfloat> %v, i64 %idx) {
; RV32-NO-ZFBFMIN-LABEL: splat_idx_v4bf16:
@@ -34,6 +36,13 @@ define <4 x bfloat> @splat_idx_v4bf16(<4 x bfloat> %v, i64 %idx) {
; RV64-ZFBFMIN-NEXT: vmv.x.s a0, v8
; RV64-ZFBFMIN-NEXT: vmv.v.x v8, a0
; RV64-ZFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: splat_idx_v4bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFBFA-NEXT: vrgather.vx v9, v8, a0
+; ZVFBFA-NEXT: vmv1r.v v8, v9
+; ZVFBFA-NEXT: ret
%x = extractelement <4 x bfloat> %v, i64 %idx
%ins = insertelement <4 x bfloat> poison, bfloat %x, i32 0
%splat = shufflevector <4 x bfloat> %ins, <4 x bfloat> poison, <4 x i32> zeroinitializer
@@ -76,6 +85,13 @@ define <2 x bfloat> @buildvec_v2bf16(bfloat %a, bfloat %b) {
; RV64-ZFBFMIN-NEXT: vmv.v.x v8, a1
; RV64-ZFBFMIN-NEXT: vslide1down.vx v8, v8, a0
; RV64-ZFBFMIN-NEXT: ret
+;
+; ZVFBFA-LABEL: buildvec_v2bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 2, e16alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfmv.v.f v8, fa0
+; ZVFBFA-NEXT: vfslide1down.vf v8, v8, fa1
+; ZVFBFA-NEXT: ret
%v1 = insertelement <2 x bfloat> poison, bfloat %a, i64 0
%v2 = insertelement <2 x bfloat> %v1, bfloat %b, i64 1
ret <2 x bfloat> %v2
@@ -88,6 +104,15 @@ define <2 x bfloat> @vid_v2bf16() {
; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret
+;
+; ZVFBFA-LABEL: vid_v2bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFBFA-NEXT: vid.v v8
+; ZVFBFA-NEXT: vfwcvt.f.x.v v9, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v9
+; ZVFBFA-NEXT: ret
ret <2 x bfloat> <bfloat 0.0, bfloat 1.0>
}
@@ -101,6 +126,16 @@ define <2 x bfloat> @vid_addend1_v2bf16() {
; CHECK-NEXT: addi a0, a0, -128
; CHECK-NEXT: vadd.vx v8, v8, a0
; CHECK-NEXT: ret
+;
+; ZVFBFA-LABEL: vid_addend1_v2bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFBFA-NEXT: vid.v v8
+; ZVFBFA-NEXT: vadd.vi v8, v8, 1
+; ZVFBFA-NEXT: vfwcvt.f.x.v v9, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v9
+; ZVFBFA-NEXT: ret
ret <2 x bfloat> <bfloat 1.0, bfloat 2.0>
}
@@ -114,6 +149,14 @@ define <2 x bfloat> @vid_denominator2_v2bf16() {
; CHECK-NEXT: addi a0, a0, -256
; CHECK-NEXT: vadd.vx v8, v8, a0
; CHECK-NEXT: ret
+;
+; ZVFBFA-LABEL: vid_denominator2_v2bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: lui a0, %hi(.LCPI4_0)
+; ZVFBFA-NEXT: addi a0, a0, %lo(.LCPI4_0)
+; ZVFBFA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFBFA-NEXT: vle16.v v8, (a0)
+; ZVFBFA-NEXT: ret
ret <2 x bfloat> <bfloat 0.5, bfloat 1.0>
}
@@ -124,6 +167,16 @@ define <2 x bfloat> @vid_step2_v2bf16() {
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vsll.vi v8, v8, 14
; CHECK-NEXT: ret
+;
+; ZVFBFA-LABEL: vid_step2_v2bf16:
+; ZVFBFA: # %bb.0:
+; ZVFBFA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFBFA-NEXT: vid.v v8
+; ZVFBFA-NEXT: vadd.vv v8, v8, v8
+; ZVFBFA-NEXT: vfwcvt.f.x.v v9, v8
+; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, mf4, ta, ma
+; ZVFBFA-NEXT: vfncvt.f.f.w v8, v9
+; ZVFBFA-NEXT: ret
ret <2 x bfloat> <bfloat 0.0, bfloat 2.0>
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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