[llvm] [AMDGPU] Break v2i32 and/or/xor ops into i32 pairs when followed by t… (PR #191422)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/AMDGPU/SIISelLowering.cpp --diff_from_common_commit
``````````

:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index ffbc8e31f..05117eb5a 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -14947,7 +14947,7 @@ SDValue SITargetLowering::performOrCombine(SDNode *N,
       }
     }
   }
-  
+
   if (DCI.isAfterLegalizeDAG() && VT == MVT::v2i32) {
     if (SDValue RV = performAndOrXorv2i32Combine(N, DAG))
       return RV;
@@ -15047,7 +15047,7 @@ SDValue SITargetLowering::performXorCombine(SDNode *N,
       return DAG.getNode(ISD::BITCAST, DL, VT, NewSelect);
     }
   }
-  
+
   if (DCI.isAfterLegalizeDAG() && VT == MVT::v2i32) {
     if (SDValue RV = performAndOrXorv2i32Combine(N, DAG))
       return RV;

``````````

</details>


https://github.com/llvm/llvm-project/pull/191422