[llvm] [AMDGPU] Change *-DAG to *-SDAG in check prefixes (PR #191411)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 10 06:04:14 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Jay Foad (jayfoad)
<details>
<summary>Changes</summary>
In some cases the use of *-DAG seemed to confuse the update scripts
because of the clash with FileCheck's built-in -DAG suffix.
---
Full diff: https://github.com/llvm/llvm-project/pull/191411.diff
2 Files Affected:
- (modified) llvm/test/CodeGen/AMDGPU/fptrunc.ll (+25-25)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll (+139-139)
``````````diff
diff --git a/llvm/test/CodeGen/AMDGPU/fptrunc.ll b/llvm/test/CodeGen/AMDGPU/fptrunc.ll
index 0a2c59668714d..3e344af903a1e 100644
--- a/llvm/test/CodeGen/AMDGPU/fptrunc.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptrunc.ll
@@ -8,8 +8,8 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -global-isel=0 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX10-SDAG,GFX10-UNSAFE-SDAG %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX11-SDAG,GFX11-SAFE-SDAG %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX11-GISEL,GFX11-SAFE-GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=-flat-for-global,+real-true16 < %s | FileCheck -check-prefixes=GFX11-SDAG,GFX11-UNSAFE-DAG-TRUE16 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=-flat-for-global,-real-true16 < %s | FileCheck -check-prefixes=GFX11-SDAG,GFX11-UNSAFE-DAG-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=-flat-for-global,+real-true16 < %s | FileCheck -check-prefixes=GFX11-SDAG,GFX11-UNSAFE-SDAG-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=-flat-for-global,-real-true16 < %s | FileCheck -check-prefixes=GFX11-SDAG,GFX11-UNSAFE-SDAG-FAKE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=-flat-for-global,+real-true16 < %s | FileCheck -check-prefixes=GFX11-GISEL,GFX11-UNSAFE-GISEL-TRUE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=-flat-for-global,-real-true16 < %s | FileCheck -check-prefixes=GFX11-GISEL,GFX11-UNSAFE-GISEL-FAKE16 %s
@@ -745,29 +745,29 @@ define amdgpu_kernel void @fptrunc_f64_to_f16_afn(ptr addrspace(1) %out, double
; GFX11-SAFE-GISEL-NEXT: buffer_store_b16 v0, off, s[0:3], 0
; GFX11-SAFE-GISEL-NEXT: s_endpgm
;
-; GFX11-UNSAFE-DAG-TRUE16-LABEL: fptrunc_f64_to_f16_afn:
-; GFX11-UNSAFE-DAG-TRUE16: ; %bb.0:
-; GFX11-UNSAFE-DAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-UNSAFE-DAG-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-UNSAFE-DAG-TRUE16-NEXT: v_cvt_f32_f64_e32 v0, s[2:3]
-; GFX11-UNSAFE-DAG-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
-; GFX11-UNSAFE-DAG-TRUE16-NEXT: s_mov_b32 s2, -1
-; GFX11-UNSAFE-DAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-UNSAFE-DAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-UNSAFE-DAG-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0
-; GFX11-UNSAFE-DAG-TRUE16-NEXT: s_endpgm
-;
-; GFX11-UNSAFE-DAG-FAKE16-LABEL: fptrunc_f64_to_f16_afn:
-; GFX11-UNSAFE-DAG-FAKE16: ; %bb.0:
-; GFX11-UNSAFE-DAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-UNSAFE-DAG-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-UNSAFE-DAG-FAKE16-NEXT: v_cvt_f32_f64_e32 v0, s[2:3]
-; GFX11-UNSAFE-DAG-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
-; GFX11-UNSAFE-DAG-FAKE16-NEXT: s_mov_b32 s2, -1
-; GFX11-UNSAFE-DAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-UNSAFE-DAG-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX11-UNSAFE-DAG-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0
-; GFX11-UNSAFE-DAG-FAKE16-NEXT: s_endpgm
+; GFX11-UNSAFE-SDAG-TRUE16-LABEL: fptrunc_f64_to_f16_afn:
+; GFX11-UNSAFE-SDAG-TRUE16: ; %bb.0:
+; GFX11-UNSAFE-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-UNSAFE-SDAG-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_cvt_f32_f64_e32 v0, s[2:3]
+; GFX11-UNSAFE-SDAG-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX11-UNSAFE-SDAG-TRUE16-NEXT: s_mov_b32 s2, -1
+; GFX11-UNSAFE-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-UNSAFE-SDAG-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0
+; GFX11-UNSAFE-SDAG-TRUE16-NEXT: s_endpgm
+;
+; GFX11-UNSAFE-SDAG-FAKE16-LABEL: fptrunc_f64_to_f16_afn:
+; GFX11-UNSAFE-SDAG-FAKE16: ; %bb.0:
+; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_cvt_f32_f64_e32 v0, s[2:3]
+; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_mov_b32 s2, -1
+; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-UNSAFE-SDAG-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0
+; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_endpgm
;
; GFX11-UNSAFE-GISEL-TRUE16-LABEL: fptrunc_f64_to_f16_afn:
; GFX11-UNSAFE-GISEL-TRUE16: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
index 09e6bb4ce7752..c2ca5522d0cd9 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
@@ -1,33 +1,33 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=ASM-DAG %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=ASM-DAG %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=ASM-SDAG %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=ASM-SDAG %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=ASM-GISEL-TRUE16 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=ASM-GISEL-FAKE16 %s
; Test that we can use v0 for temporaries in the if.then block.
define i32 @dead_i32(i1 %cond, i32 %x, ptr addrspace(1) %ptr1) #0 {
-; ASM-DAG-LABEL: dead_i32:
-; ASM-DAG: ; %bb.0: ; %entry
-; ASM-DAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; ASM-DAG-NEXT: s_wait_expcnt 0x0
-; ASM-DAG-NEXT: s_wait_samplecnt 0x0
-; ASM-DAG-NEXT: s_wait_bvhcnt 0x0
-; ASM-DAG-NEXT: s_wait_kmcnt 0x0
-; ASM-DAG-NEXT: v_mov_b32_e32 v4, v0
-; ASM-DAG-NEXT: v_mov_b32_e32 v0, v1
-; ASM-DAG-NEXT: s_mov_b32 s0, exec_lo
-; ASM-DAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; ASM-DAG-NEXT: v_and_b32_e32 v1, 1, v4
-; ASM-DAG-NEXT: v_cmpx_eq_u32_e32 1, v1
-; ASM-DAG-NEXT: s_cbranch_execz .LBB0_2
-; ASM-DAG-NEXT: ; %bb.1: ; %if.then
-; ASM-DAG-NEXT: v_add_nc_u32_e32 v0, 1, v0
-; ASM-DAG-NEXT: global_store_b32 v[2:3], v0, off
-; ASM-DAG-NEXT: ; implicit-def: $vgpr0
-; ASM-DAG-NEXT: .LBB0_2: ; %if.end
-; ASM-DAG-NEXT: s_wait_alu depctr_sa_sdst(0)
-; ASM-DAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; ASM-DAG-NEXT: s_setpc_b64 s[30:31]
+; ASM-SDAG-LABEL: dead_i32:
+; ASM-SDAG: ; %bb.0: ; %entry
+; ASM-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; ASM-SDAG-NEXT: s_wait_expcnt 0x0
+; ASM-SDAG-NEXT: s_wait_samplecnt 0x0
+; ASM-SDAG-NEXT: s_wait_bvhcnt 0x0
+; ASM-SDAG-NEXT: s_wait_kmcnt 0x0
+; ASM-SDAG-NEXT: v_mov_b32_e32 v4, v0
+; ASM-SDAG-NEXT: v_mov_b32_e32 v0, v1
+; ASM-SDAG-NEXT: s_mov_b32 s0, exec_lo
+; ASM-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; ASM-SDAG-NEXT: v_and_b32_e32 v1, 1, v4
+; ASM-SDAG-NEXT: v_cmpx_eq_u32_e32 1, v1
+; ASM-SDAG-NEXT: s_cbranch_execz .LBB0_2
+; ASM-SDAG-NEXT: ; %bb.1: ; %if.then
+; ASM-SDAG-NEXT: v_add_nc_u32_e32 v0, 1, v0
+; ASM-SDAG-NEXT: global_store_b32 v[2:3], v0, off
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr0
+; ASM-SDAG-NEXT: .LBB0_2: ; %if.end
+; ASM-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
+; ASM-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; ASM-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; ASM-GISEL-TRUE16-LABEL: dead_i32:
; ASM-GISEL-TRUE16: ; %bb.0: ; %entry
@@ -91,46 +91,46 @@ if.end:
%trivial_types = type { i32, float, <3 x i32>, i64, ptr addrspace(5), ptr addrspace(1), <4 x float>, { float, <2 x i16> } }
define %trivial_types @dead_struct(i1 %cond, %trivial_types %x, ptr addrspace(1) %ptr1, i32 %v) #0 {
-; ASM-DAG-LABEL: dead_struct:
-; ASM-DAG: ; %bb.0: ; %entry
-; ASM-DAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; ASM-DAG-NEXT: s_wait_expcnt 0x0
-; ASM-DAG-NEXT: s_wait_samplecnt 0x0
-; ASM-DAG-NEXT: s_wait_bvhcnt 0x0
-; ASM-DAG-NEXT: s_wait_kmcnt 0x0
-; ASM-DAG-NEXT: v_mov_b32_e32 v20, v0
-; ASM-DAG-NEXT: v_mov_b32_e32 v0, v1
-; ASM-DAG-NEXT: s_mov_b32 s0, exec_lo
-; ASM-DAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; ASM-DAG-NEXT: v_and_b32_e32 v1, 1, v20
-; ASM-DAG-NEXT: v_cmpx_eq_u32_e32 1, v1
-; ASM-DAG-NEXT: s_cbranch_execz .LBB1_2
-; ASM-DAG-NEXT: ; %bb.1: ; %if.then
-; ASM-DAG-NEXT: v_dual_mov_b32 v11, 0 :: v_dual_add_nc_u32 v0, 15, v19
-; ASM-DAG-NEXT: v_mov_b32_e32 v2, 0x3fc00000
-; ASM-DAG-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5
-; ASM-DAG-NEXT: ; implicit-def: $vgpr6_vgpr7
-; ASM-DAG-NEXT: ; implicit-def: $vgpr8
-; ASM-DAG-NEXT: ; implicit-def: $vgpr9_vgpr10
-; ASM-DAG-NEXT: ; implicit-def: $vgpr15
-; ASM-DAG-NEXT: ; implicit-def: $vgpr16
-; ASM-DAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; ASM-DAG-NEXT: v_dual_mov_b32 v12, v11 :: v_dual_mov_b32 v13, v11
-; ASM-DAG-NEXT: v_mov_b32_e32 v14, v11
-; ASM-DAG-NEXT: global_store_b32 v[17:18], v0, off
-; ASM-DAG-NEXT: ; implicit-def: $vgpr0
-; ASM-DAG-NEXT: .LBB1_2: ; %if.end
-; ASM-DAG-NEXT: s_wait_alu depctr_sa_sdst(0)
-; ASM-DAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; ASM-DAG-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v3
-; ASM-DAG-NEXT: v_dual_mov_b32 v3, v4 :: v_dual_mov_b32 v4, v5
-; ASM-DAG-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
-; ASM-DAG-NEXT: v_dual_mov_b32 v7, v8 :: v_dual_mov_b32 v8, v9
-; ASM-DAG-NEXT: v_dual_mov_b32 v9, v10 :: v_dual_mov_b32 v10, v11
-; ASM-DAG-NEXT: v_dual_mov_b32 v11, v12 :: v_dual_mov_b32 v12, v13
-; ASM-DAG-NEXT: v_dual_mov_b32 v13, v14 :: v_dual_mov_b32 v14, v15
-; ASM-DAG-NEXT: v_mov_b32_e32 v15, v16
-; ASM-DAG-NEXT: s_setpc_b64 s[30:31]
+; ASM-SDAG-LABEL: dead_struct:
+; ASM-SDAG: ; %bb.0: ; %entry
+; ASM-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; ASM-SDAG-NEXT: s_wait_expcnt 0x0
+; ASM-SDAG-NEXT: s_wait_samplecnt 0x0
+; ASM-SDAG-NEXT: s_wait_bvhcnt 0x0
+; ASM-SDAG-NEXT: s_wait_kmcnt 0x0
+; ASM-SDAG-NEXT: v_mov_b32_e32 v20, v0
+; ASM-SDAG-NEXT: v_mov_b32_e32 v0, v1
+; ASM-SDAG-NEXT: s_mov_b32 s0, exec_lo
+; ASM-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; ASM-SDAG-NEXT: v_and_b32_e32 v1, 1, v20
+; ASM-SDAG-NEXT: v_cmpx_eq_u32_e32 1, v1
+; ASM-SDAG-NEXT: s_cbranch_execz .LBB1_2
+; ASM-SDAG-NEXT: ; %bb.1: ; %if.then
+; ASM-SDAG-NEXT: v_dual_mov_b32 v11, 0 :: v_dual_add_nc_u32 v0, 15, v19
+; ASM-SDAG-NEXT: v_mov_b32_e32 v2, 0x3fc00000
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr6_vgpr7
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr8
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr9_vgpr10
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr15
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr16
+; ASM-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; ASM-SDAG-NEXT: v_dual_mov_b32 v12, v11 :: v_dual_mov_b32 v13, v11
+; ASM-SDAG-NEXT: v_mov_b32_e32 v14, v11
+; ASM-SDAG-NEXT: global_store_b32 v[17:18], v0, off
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr0
+; ASM-SDAG-NEXT: .LBB1_2: ; %if.end
+; ASM-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
+; ASM-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; ASM-SDAG-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v3
+; ASM-SDAG-NEXT: v_dual_mov_b32 v3, v4 :: v_dual_mov_b32 v4, v5
+; ASM-SDAG-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
+; ASM-SDAG-NEXT: v_dual_mov_b32 v7, v8 :: v_dual_mov_b32 v8, v9
+; ASM-SDAG-NEXT: v_dual_mov_b32 v9, v10 :: v_dual_mov_b32 v10, v11
+; ASM-SDAG-NEXT: v_dual_mov_b32 v11, v12 :: v_dual_mov_b32 v12, v13
+; ASM-SDAG-NEXT: v_dual_mov_b32 v13, v14 :: v_dual_mov_b32 v14, v15
+; ASM-SDAG-NEXT: v_mov_b32_e32 v15, v16
+; ASM-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; ASM-GISEL-TRUE16-LABEL: dead_struct:
; ASM-GISEL-TRUE16: ; %bb.0: ; %entry
@@ -284,81 +284,81 @@ if.end:
}
define [32 x i32] @dead_array(i1 %cond, [32 x i32] %x, ptr addrspace(1) %ptr1, i32 %v) #0 {
-; ASM-DAG-LABEL: dead_array:
-; ASM-DAG: ; %bb.0: ; %entry
-; ASM-DAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; ASM-DAG-NEXT: s_wait_expcnt 0x0
-; ASM-DAG-NEXT: s_wait_samplecnt 0x0
-; ASM-DAG-NEXT: s_wait_bvhcnt 0x0
-; ASM-DAG-NEXT: s_wait_kmcnt 0x0
-; ASM-DAG-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v0
-; ASM-DAG-NEXT: v_mov_b32_e32 v0, v1
-; ASM-DAG-NEXT: s_clause 0x4
-; ASM-DAG-NEXT: scratch_load_b32 v35, off, s32 offset:12
-; ASM-DAG-NEXT: scratch_load_b32 v34, off, s32 offset:8
-; ASM-DAG-NEXT: scratch_load_b32 v31, off, s32 offset:4
-; ASM-DAG-NEXT: scratch_load_b32 v30, off, s32
-; ASM-DAG-NEXT: scratch_load_b32 v1, off, s32 offset:16
-; ASM-DAG-NEXT: s_mov_b32 s0, exec_lo
-; ASM-DAG-NEXT: v_and_b32_e32 v33, 1, v33
-; ASM-DAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; ASM-DAG-NEXT: v_cmpx_eq_u32_e32 1, v33
-; ASM-DAG-NEXT: s_cbranch_execz .LBB2_2
-; ASM-DAG-NEXT: ; %bb.1: ; %if.then
-; ASM-DAG-NEXT: v_dual_mov_b32 v8, 15 :: v_dual_mov_b32 v7, 13
-; ASM-DAG-NEXT: s_wait_loadcnt 0x0
-; ASM-DAG-NEXT: v_add_nc_u32_e32 v0, 15, v1
-; ASM-DAG-NEXT: ; implicit-def: $vgpr2
-; ASM-DAG-NEXT: ; implicit-def: $vgpr3
-; ASM-DAG-NEXT: ; implicit-def: $vgpr4
-; ASM-DAG-NEXT: ; implicit-def: $vgpr5
-; ASM-DAG-NEXT: ; implicit-def: $vgpr6
-; ASM-DAG-NEXT: ; implicit-def: $vgpr9
-; ASM-DAG-NEXT: ; implicit-def: $vgpr10
-; ASM-DAG-NEXT: ; implicit-def: $vgpr11
-; ASM-DAG-NEXT: ; implicit-def: $vgpr12
-; ASM-DAG-NEXT: ; implicit-def: $vgpr13
-; ASM-DAG-NEXT: ; implicit-def: $vgpr14
-; ASM-DAG-NEXT: ; implicit-def: $vgpr15
-; ASM-DAG-NEXT: ; implicit-def: $vgpr16
-; ASM-DAG-NEXT: ; implicit-def: $vgpr17
-; ASM-DAG-NEXT: ; implicit-def: $vgpr18
-; ASM-DAG-NEXT: ; implicit-def: $vgpr19
-; ASM-DAG-NEXT: ; implicit-def: $vgpr20
-; ASM-DAG-NEXT: ; implicit-def: $vgpr21
-; ASM-DAG-NEXT: ; implicit-def: $vgpr22
-; ASM-DAG-NEXT: ; implicit-def: $vgpr23
-; ASM-DAG-NEXT: ; implicit-def: $vgpr24
-; ASM-DAG-NEXT: ; implicit-def: $vgpr25
-; ASM-DAG-NEXT: ; implicit-def: $vgpr26
-; ASM-DAG-NEXT: ; implicit-def: $vgpr27
-; ASM-DAG-NEXT: ; implicit-def: $vgpr28
-; ASM-DAG-NEXT: ; implicit-def: $vgpr29
-; ASM-DAG-NEXT: ; implicit-def: $vgpr32
-; ASM-DAG-NEXT: ; implicit-def: $vgpr30
-; ASM-DAG-NEXT: ; implicit-def: $vgpr31
-; ASM-DAG-NEXT: global_store_b32 v[34:35], v0, off
-; ASM-DAG-NEXT: ; implicit-def: $vgpr0
-; ASM-DAG-NEXT: .LBB2_2: ; %if.end
-; ASM-DAG-NEXT: s_wait_alu depctr_sa_sdst(0)
-; ASM-DAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; ASM-DAG-NEXT: s_wait_loadcnt 0x0
-; ASM-DAG-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v3
-; ASM-DAG-NEXT: v_dual_mov_b32 v3, v4 :: v_dual_mov_b32 v4, v5
-; ASM-DAG-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
-; ASM-DAG-NEXT: v_dual_mov_b32 v7, v8 :: v_dual_mov_b32 v8, v9
-; ASM-DAG-NEXT: v_dual_mov_b32 v9, v10 :: v_dual_mov_b32 v10, v11
-; ASM-DAG-NEXT: v_dual_mov_b32 v11, v12 :: v_dual_mov_b32 v12, v13
-; ASM-DAG-NEXT: v_dual_mov_b32 v13, v14 :: v_dual_mov_b32 v14, v15
-; ASM-DAG-NEXT: v_dual_mov_b32 v15, v16 :: v_dual_mov_b32 v16, v17
-; ASM-DAG-NEXT: v_dual_mov_b32 v17, v18 :: v_dual_mov_b32 v18, v19
-; ASM-DAG-NEXT: v_dual_mov_b32 v19, v20 :: v_dual_mov_b32 v20, v21
-; ASM-DAG-NEXT: v_dual_mov_b32 v21, v22 :: v_dual_mov_b32 v22, v23
-; ASM-DAG-NEXT: v_dual_mov_b32 v23, v24 :: v_dual_mov_b32 v24, v25
-; ASM-DAG-NEXT: v_dual_mov_b32 v25, v26 :: v_dual_mov_b32 v26, v27
-; ASM-DAG-NEXT: v_dual_mov_b32 v27, v28 :: v_dual_mov_b32 v28, v29
-; ASM-DAG-NEXT: v_mov_b32_e32 v29, v32
-; ASM-DAG-NEXT: s_setpc_b64 s[30:31]
+; ASM-SDAG-LABEL: dead_array:
+; ASM-SDAG: ; %bb.0: ; %entry
+; ASM-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; ASM-SDAG-NEXT: s_wait_expcnt 0x0
+; ASM-SDAG-NEXT: s_wait_samplecnt 0x0
+; ASM-SDAG-NEXT: s_wait_bvhcnt 0x0
+; ASM-SDAG-NEXT: s_wait_kmcnt 0x0
+; ASM-SDAG-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v0
+; ASM-SDAG-NEXT: v_mov_b32_e32 v0, v1
+; ASM-SDAG-NEXT: s_clause 0x4
+; ASM-SDAG-NEXT: scratch_load_b32 v35, off, s32 offset:12
+; ASM-SDAG-NEXT: scratch_load_b32 v34, off, s32 offset:8
+; ASM-SDAG-NEXT: scratch_load_b32 v31, off, s32 offset:4
+; ASM-SDAG-NEXT: scratch_load_b32 v30, off, s32
+; ASM-SDAG-NEXT: scratch_load_b32 v1, off, s32 offset:16
+; ASM-SDAG-NEXT: s_mov_b32 s0, exec_lo
+; ASM-SDAG-NEXT: v_and_b32_e32 v33, 1, v33
+; ASM-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; ASM-SDAG-NEXT: v_cmpx_eq_u32_e32 1, v33
+; ASM-SDAG-NEXT: s_cbranch_execz .LBB2_2
+; ASM-SDAG-NEXT: ; %bb.1: ; %if.then
+; ASM-SDAG-NEXT: v_dual_mov_b32 v8, 15 :: v_dual_mov_b32 v7, 13
+; ASM-SDAG-NEXT: s_wait_loadcnt 0x0
+; ASM-SDAG-NEXT: v_add_nc_u32_e32 v0, 15, v1
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr2
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr3
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr4
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr5
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr6
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr9
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr10
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr11
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr12
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr13
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr14
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr15
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr16
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr17
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr18
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr19
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr20
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr21
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr22
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr23
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr24
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr25
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr26
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr27
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr28
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr29
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr32
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr30
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr31
+; ASM-SDAG-NEXT: global_store_b32 v[34:35], v0, off
+; ASM-SDAG-NEXT: ; implicit-def: $vgpr0
+; ASM-SDAG-NEXT: .LBB2_2: ; %if.end
+; ASM-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
+; ASM-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; ASM-SDAG-NEXT: s_wait_loadcnt 0x0
+; ASM-SDAG-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v3
+; ASM-SDAG-NEXT: v_dual_mov_b32 v3, v4 :: v_dual_mov_b32 v4, v5
+; ASM-SDAG-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
+; ASM-SDAG-NEXT: v_dual_mov_b32 v7, v8 :: v_dual_mov_b32 v8, v9
+; ASM-SDAG-NEXT: v_dual_mov_b32 v9, v10 :: v_dual_mov_b32 v10, v11
+; ASM-SDAG-NEXT: v_dual_mov_b32 v11, v12 :: v_dual_mov_b32 v12, v13
+; ASM-SDAG-NEXT: v_dual_mov_b32 v13, v14 :: v_dual_mov_b32 v14, v15
+; ASM-SDAG-NEXT: v_dual_mov_b32 v15, v16 :: v_dual_mov_b32 v16, v17
+; ASM-SDAG-NEXT: v_dual_mov_b32 v17, v18 :: v_dual_mov_b32 v18, v19
+; ASM-SDAG-NEXT: v_dual_mov_b32 v19, v20 :: v_dual_mov_b32 v20, v21
+; ASM-SDAG-NEXT: v_dual_mov_b32 v21, v22 :: v_dual_mov_b32 v22, v23
+; ASM-SDAG-NEXT: v_dual_mov_b32 v23, v24 :: v_dual_mov_b32 v24, v25
+; ASM-SDAG-NEXT: v_dual_mov_b32 v25, v26 :: v_dual_mov_b32 v26, v27
+; ASM-SDAG-NEXT: v_dual_mov_b32 v27, v28 :: v_dual_mov_b32 v28, v29
+; ASM-SDAG-NEXT: v_mov_b32_e32 v29, v32
+; ASM-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; ASM-GISEL-TRUE16-LABEL: dead_array:
; ASM-GISEL-TRUE16: ; %bb.0: ; %entry
``````````
</details>
https://github.com/llvm/llvm-project/pull/191411
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