[llvm] [AMDGPU] Add readfirstlane for inline asm SGPR with VGPR input (PR #176330)

[Matt Arsenault via llvm-commits]

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@@ -8776,6 +8780,80 @@ SDValue SITargetLowering::lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const {
   return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops);
 }
 
+/// When a divergent value (in VGPR) is passed to an inline asm with an SGPR
+/// constraint ('s'), we need to insert v_readfirstlane to move the value from
+/// VGPR to SGPR. This is done by modifying the CopyToReg nodes in the glue
+/// chain that feed into the INLINEASM node.
+SDValue SITargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
+  unsigned NumOps = Op.getNumOperands();
+
+  const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
+  SmallSet<Register, 8> SGPRInputRegs;
+
+  for (unsigned I = InlineAsm::Op_FirstOperand; I < NumOps - 1;) {
+    const InlineAsm::Flag Flags(Op.getConstantOperandVal(I));
+    unsigned NumVals = Flags.getNumOperandRegisters();
+    ++I;
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arsenm wrote:

Put this in the normal loop increment position? DOn't you just need to add a +1 in the indexing? 

https://github.com/llvm/llvm-project/pull/176330