[llvm] [RISCV] Add TuneJumpIsExpensive (PR #191374)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Pengcheng Wang (wangpc-pp)

<details>
<summary>Changes</summary>

We had `setJumpIsExpensive(true)` before 18.x but it was removed
in #<!-- -->74647. This feature allows users to tune the ISel behavior.

We have #<!-- -->80124 and #<!-- -->178394 landed, so it should be more flexible
to tune branches and selects now.

This is an alternative of #<!-- -->191158.


---
Full diff: https://github.com/llvm/llvm-project/pull/191374.diff


4 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+4) 
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+2) 
- (modified) llvm/test/CodeGen/RISCV/features-info.ll (+1) 
- (modified) llvm/unittests/TargetParser/RISCVTargetParserTest.cpp (+1) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 492c44a35b35a..ccc07e5518048 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -2051,6 +2051,10 @@ def TunePreferVsetvliOverReadVLENB
           "prefer-vsetvli-over-read-vlenb", "PreferVsetvliOverReadVLENB",
           "true", "Prefer vsetvli over read vlenb CSR to calculate VLEN">;
 
+def TuneJumpIsExpensive
+    : RISCVSimpleTuneFeature<"jump-is-expensive", "IsJumpExpensive",
+                             "true", "Jump is expensive">;
+
 //===----------------------------------------------------------------------===//
 // CPU Families (alphabetized by vendor).
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index ce8cd0f6f5776..dc427f54c4e07 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1914,6 +1914,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
 
   setMaxLargeFPConvertBitWidthSupported(Subtarget.is64Bit() ? 128 : 64);
 
+  setJumpIsExpensive(Subtarget.isJumpExpensive());
+
   // Disable strict node mutation.
   IsStrictFPEnabled = true;
   EnableExtLdPromotion = true;
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index 7c4271b409f82..4be8273430a2e 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -62,6 +62,7 @@
 ; CHECK-NEXT:   fusion-zextw                     - Enable SLLI+SRLI to be fused to zero extension of word.
 ; CHECK-NEXT:   h                                - 'H' (Hypervisor).
 ; CHECK-NEXT:   i                                - 'I' (Base Integer Instruction Set).
+; CHECK-NEXT:   jump-is-expensive                - Jump is expensive.
 ; CHECK-NEXT:   log-vrgather                     - Has vrgather.vv with LMUL*log2(LMUL) latency
 ; CHECK-NEXT:   m                                - 'M' (Integer Multiplication and Division).
 ; CHECK-NEXT:   mips-p8700                       - MIPS p8700 processor.
diff --git a/llvm/unittests/TargetParser/RISCVTargetParserTest.cpp b/llvm/unittests/TargetParser/RISCVTargetParserTest.cpp
index 0302d56e3e3fa..0cdb7fedeffe0 100644
--- a/llvm/unittests/TargetParser/RISCVTargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVTargetParserTest.cpp
@@ -51,6 +51,7 @@ TEST(RISCVTuneFeature, AllTuneFeatures) {
                  "disable-misched-store-clustering",
                  "disable-postmisched-load-clustering",
                  "disable-postmisched-store-clustering",
+                 "jump-is-expensive",
                  "single-element-vec-fp64",
                  "no-default-unroll",
                  "no-sink-splat-operands",

``````````

</details>


https://github.com/llvm/llvm-project/pull/191374