[llvm] 0a0a333 - [NFC][AMDGPU]: expose IGLPStrategyID in AMDGPUIGroupLP.h (#191340)

[via llvm-commits]

Author: hidekisaito
Date: 2026-04-09T23:02:28-07:00
New Revision: 0a0a33363c1c3ea5393997df5537f524d0e72a6d

URL: https://github.com/llvm/llvm-project/commit/0a0a33363c1c3ea5393997df5537f524d0e72a6d
DIFF: https://github.com/llvm/llvm-project/commit/0a0a33363c1c3ea5393997df5537f524d0e72a6d.diff

LOG: [NFC][AMDGPU]: expose IGLPStrategyID in AMDGPUIGroupLP.h (#191340)

Move IGLPStrategyID and its enumerators into llvm::AMDGPU in the public
header so other translation units can share the immediate encoding.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
    llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
index d49ec90e4c212..df778704bb5d4 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
@@ -27,6 +27,7 @@
 #include <type_traits>
 
 using namespace llvm;
+using namespace llvm::AMDGPU;
 
 #define DEBUG_TYPE "igrouplp"
 
@@ -819,13 +820,6 @@ void PipelineSolver::solve() {
   LLVM_DEBUG(DAG->dump());
 }
 
-enum IGLPStrategyID : int {
-  MFMASmallGemmOptID = 0,
-  MFMASmallGemmSingleWaveOptID = 1,
-  MFMAExpInterleaveID = 2,
-  MFMAExpSimpleInterleaveID = 3
-};
-
 // Implement a IGLP scheduling strategy.
 class IGLPStrategy {
 protected:

diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.h b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.h
index 0688f07873493..1cb45ebc315f5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.h
@@ -17,6 +17,14 @@ namespace llvm {
 namespace AMDGPU {
 // The current phase of instruction scheduling
 enum class SchedulingPhase { Initial, PreRAReentry, PostRA };
+
+/// Operand 0 immediate for IGLP_OPT pseudo instructions.
+enum IGLPStrategyID : int {
+  MFMASmallGemmOptID = 0,
+  MFMASmallGemmSingleWaveOptID = 1,
+  MFMAExpInterleaveID = 2,
+  MFMAExpSimpleInterleaveID = 3,
+};
 } // namespace AMDGPU
 
 std::unique_ptr<ScheduleDAGMutation>