[llvm] AMDGPU/GlobalISel: RegBankLegalize rules for G_AMDGPU_S_BUFFER_PREFETCH (PR #191315)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 9 15:42:50 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: vangthao95
<details>
<summary>Changes</summary>
---
Full diff: https://github.com/llvm/llvm-project/pull/191315.diff
2 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp (+3)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll (+95-15)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index c3157c9441027..455006c2aca89 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1385,6 +1385,9 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Any({{UniS64, S32}, {{UniInVgprS64}, {Vgpr32}}})
.Any({{DivS64, S32}, {{Vgpr64}, {Vgpr32}}});
+ addRulesForGOpcs({G_AMDGPU_S_BUFFER_PREFETCH})
+ .Any({{}, {{}, {SgprV4S32_WF, Imm, Sgpr32_WF}}});
+
addRulesForGOpcs({G_FPEXT})
.Any({{DivS32, S16}, {{Vgpr32}, {Vgpr16}}})
.Any({{UniS64, S32}, {{UniInVgprS64}, {Vgpr32}}})
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll
index dc33c4f0adf23..0652391291647 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefix=GCN %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefix=GCN %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GCN,SDAG %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GCN,GISEL %s
declare void @llvm.amdgcn.s.buffer.prefetch.data(ptr addrspace(8) %rsrc, i32 %offset, i32 %len)
@@ -25,26 +25,106 @@ entry:
}
define amdgpu_ps void @buffer_prefetch_data_imm_offset_vgpr_len(ptr addrspace(8) inreg %rsrc, i32 %len) {
-; GCN-LABEL: buffer_prefetch_data_imm_offset_vgpr_len:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: v_readfirstlane_b32 s4, v0
-; GCN-NEXT: s_buffer_prefetch_data s[0:3], 0x80, s4, 0
-; GCN-NEXT: s_endpgm
+; SDAG-LABEL: buffer_prefetch_data_imm_offset_vgpr_len:
+; SDAG: ; %bb.0: ; %entry
+; SDAG-NEXT: v_readfirstlane_b32 s4, v0
+; SDAG-NEXT: s_buffer_prefetch_data s[0:3], 0x80, s4, 0
+; SDAG-NEXT: s_endpgm
+;
+; GISEL-LABEL: buffer_prefetch_data_imm_offset_vgpr_len:
+; GISEL: ; %bb.0: ; %entry
+; GISEL-NEXT: s_mov_b32 s4, exec_lo
+; GISEL-NEXT: .LBB2_1: ; =>This Inner Loop Header: Depth=1
+; GISEL-NEXT: v_readfirstlane_b32 s5, v0
+; GISEL-NEXT: s_mov_b32 s4, exec_lo
+; GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GISEL-NEXT: v_cmpx_eq_u32_e64 s5, v0
+; GISEL-NEXT: s_buffer_prefetch_data s[0:3], 0x80, s5, 0
+; GISEL-NEXT: ; implicit-def: $vgpr0
+; GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s4
+; GISEL-NEXT: s_cbranch_execnz .LBB2_1
+; GISEL-NEXT: ; %bb.2:
+; GISEL-NEXT: s_endpgm
entry:
tail call void @llvm.amdgcn.s.buffer.prefetch.data(ptr addrspace(8) inreg %rsrc, i32 128, i32 %len)
ret void
}
define amdgpu_ps void @buffer_prefetch_data_vgpr_rsrc_imm_offset_sgpr_len(ptr addrspace(8) %rsrc, i32 inreg %len) {
-; GCN-LABEL: buffer_prefetch_data_vgpr_rsrc_imm_offset_sgpr_len:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: v_readfirstlane_b32 s4, v0
-; GCN-NEXT: v_readfirstlane_b32 s5, v1
-; GCN-NEXT: v_readfirstlane_b32 s6, v2
-; GCN-NEXT: v_readfirstlane_b32 s7, v3
-; GCN-NEXT: s_buffer_prefetch_data s[4:7], 0x80, s0, 0
-; GCN-NEXT: s_endpgm
+; SDAG-LABEL: buffer_prefetch_data_vgpr_rsrc_imm_offset_sgpr_len:
+; SDAG: ; %bb.0: ; %entry
+; SDAG-NEXT: v_readfirstlane_b32 s4, v0
+; SDAG-NEXT: v_readfirstlane_b32 s5, v1
+; SDAG-NEXT: v_readfirstlane_b32 s6, v2
+; SDAG-NEXT: v_readfirstlane_b32 s7, v3
+; SDAG-NEXT: s_buffer_prefetch_data s[4:7], 0x80, s0, 0
+; SDAG-NEXT: s_endpgm
+;
+; GISEL-LABEL: buffer_prefetch_data_vgpr_rsrc_imm_offset_sgpr_len:
+; GISEL: ; %bb.0: ; %entry
+; GISEL-NEXT: s_mov_b32 s1, exec_lo
+; GISEL-NEXT: .LBB3_1: ; =>This Inner Loop Header: Depth=1
+; GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GISEL-NEXT: v_readfirstlane_b32 s7, v3
+; GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GISEL-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
+; GISEL-NEXT: v_cmp_eq_u64_e64 s1, s[6:7], v[2:3]
+; GISEL-NEXT: s_and_b32 s1, vcc_lo, s1
+; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GISEL-NEXT: s_and_saveexec_b32 s1, s1
+; GISEL-NEXT: s_buffer_prefetch_data s[4:7], 0x80, s0, 0
+; GISEL-NEXT: ; implicit-def: $vgpr0
+; GISEL-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s1
+; GISEL-NEXT: s_cbranch_execnz .LBB3_1
+; GISEL-NEXT: ; %bb.2:
+; GISEL-NEXT: s_endpgm
entry:
tail call void @llvm.amdgcn.s.buffer.prefetch.data(ptr addrspace(8) inreg %rsrc, i32 128, i32 %len)
ret void
}
+
+define amdgpu_ps void @buffer_prefetch_data_vgpr_rsrc_imm_offset_vgpr_len(ptr addrspace(8) %rsrc, i32 %len) {
+; SDAG-LABEL: buffer_prefetch_data_vgpr_rsrc_imm_offset_vgpr_len:
+; SDAG: ; %bb.0: ; %entry
+; SDAG-NEXT: v_readfirstlane_b32 s0, v0
+; SDAG-NEXT: v_readfirstlane_b32 s1, v1
+; SDAG-NEXT: v_readfirstlane_b32 s2, v2
+; SDAG-NEXT: v_readfirstlane_b32 s3, v3
+; SDAG-NEXT: v_readfirstlane_b32 s4, v4
+; SDAG-NEXT: s_buffer_prefetch_data s[0:3], 0x80, s4, 0
+; SDAG-NEXT: s_endpgm
+;
+; GISEL-LABEL: buffer_prefetch_data_vgpr_rsrc_imm_offset_vgpr_len:
+; GISEL: ; %bb.0: ; %entry
+; GISEL-NEXT: s_mov_b32 s0, exec_lo
+; GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GISEL-NEXT: v_readfirstlane_b32 s7, v3
+; GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GISEL-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
+; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GISEL-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
+; GISEL-NEXT: v_cmp_eq_u32_e64 s1, s2, v4
+; GISEL-NEXT: s_and_b32 s0, vcc_lo, s0
+; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GISEL-NEXT: s_and_b32 s0, s0, s1
+; GISEL-NEXT: s_and_saveexec_b32 s0, s0
+; GISEL-NEXT: s_buffer_prefetch_data s[4:7], 0x80, s2, 0
+; GISEL-NEXT: ; implicit-def: $vgpr0
+; GISEL-NEXT: ; implicit-def: $vgpr4
+; GISEL-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s0
+; GISEL-NEXT: s_cbranch_execnz .LBB4_1
+; GISEL-NEXT: ; %bb.2:
+; GISEL-NEXT: s_endpgm
+entry:
+ tail call void @llvm.amdgcn.s.buffer.prefetch.data(ptr addrspace(8) %rsrc, i32 128, i32 %len)
+ ret void
+}
``````````
</details>
https://github.com/llvm/llvm-project/pull/191315
More information about the llvm-commits
mailing list