[llvm] [PowerPC] Rework AMO load with Compare and Swap Not Equal to use post-RA pseudo expansion (PR #190698)

[Eli Friedman via llvm-commits]

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@@ -5892,3 +5895,42 @@ bool PPCInstrInfo::areMemAccessesTriviallyDisjoint(
   }
   return false;
 }
+
+// Expands LWAT_CSNE_PSEUDO/LDAT_CSNE_PSEUDO post register allocation.
+// lwat/ldat FC=16 requires 3 consecutive registers. X3/X4/X5 are
+// hardcoded post-RA to satisfy this constraint without a dedicated
+// register class.
+bool PPCInstrInfo::expandAMOCSNEPseudo(MachineInstr &MI) const {
+  MachineBasicBlock &MBB = *MI.getParent();
+  DebugLoc DL = MI.getDebugLoc();
+  bool IsLDAT = MI.getOpcode() == PPC::LDAT_CSNE_PSEUDO;
+
+  Register DstReg = MI.getOperand(0).getReg();
+  Register PtrReg = MI.getOperand(1).getReg();
+
+  Register ScratchReg = PtrReg;
+  if (PtrReg == PPC::X3 || PtrReg == PPC::X4 || PtrReg == PPC::X5) {
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efriedma-quic wrote:

I'd like to see a test where scavenging forces a spill.

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It looks like this is assuming the pointer will be stored in a 64-bit register; is that a safe assumption?  (Can you use this intrinsic with a 32-bit target?)

https://github.com/llvm/llvm-project/pull/190698