[llvm] [VPlan] Replace WideCanIV with CanIV when possible (PR #191276)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 9 12:20:40 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-transforms
@llvm/pr-subscribers-backend-risc-v
Author: Ramkumar Ramachandra (artagnon)
<details>
<summary>Changes</summary>
Improve removeRedundantCanonicalIVs to replace WideCanonicalIV with CanonicalIV when possible. Unfortunately, the test mve-reg-pressure-spills could not be saved, and had to be removed.
---
Patch is 77.59 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/191276.diff
15 Files Affected:
- (modified) llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp (+9-7)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/ARM/active-lane-mask.ll (+6-8)
- (modified) llvm/test/Transforms/LoopVectorize/ARM/mve-gather-scatter-tailpred.ll (+2-2)
- (removed) llvm/test/Transforms/LoopVectorize/ARM/mve-reg-pressure-spills.ll (-268)
- (modified) llvm/test/Transforms/LoopVectorize/ARM/tail-folding-counting-down.ll (+1-2)
- (modified) llvm/test/Transforms/LoopVectorize/ARM/tail-folding-prefer-flag.ll (+13-20)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/interleaved-masked-access.ll (+8-8)
- (modified) llvm/test/Transforms/LoopVectorize/as_cast.ll (+1)
- (modified) llvm/test/Transforms/LoopVectorize/cast-induction.ll (+8-9)
- (modified) llvm/test/Transforms/LoopVectorize/first-order-recurrence-tail-folding.ll (+21-30)
- (modified) llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll (+11-16)
- (modified) llvm/test/Transforms/LoopVectorize/pr45679-fold-tail-by-masking.ll (+12-18)
- (modified) llvm/test/Transforms/LoopVectorize/strict-fadd-interleave-only.ll (+16-29)
- (modified) llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll (+16-26)
``````````diff
diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
index 098d9975beabb..7fc4f4b5222f4 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
@@ -679,15 +679,17 @@ static void removeRedundantInductionCasts(VPlan &Plan) {
static void removeRedundantCanonicalIVs(VPlan &Plan) {
VPRegionBlock *LoopRegion = Plan.getVectorLoopRegion();
VPCanonicalIVPHIRecipe *CanonicalIV = LoopRegion->getCanonicalIV();
- VPWidenCanonicalIVRecipe *WidenNewIV = nullptr;
- for (VPUser *U : CanonicalIV->users()) {
- WidenNewIV = dyn_cast<VPWidenCanonicalIVRecipe>(U);
- if (WidenNewIV)
- break;
- }
+ auto *FoundWideIV =
+ find_if(CanonicalIV->users(), IsaPred<VPWidenCanonicalIVRecipe>);
+ if (FoundWideIV == CanonicalIV->user_end())
+ return;
+ auto *WidenNewIV = cast<VPWidenCanonicalIVRecipe>(*FoundWideIV);
- if (!WidenNewIV)
+ if (Plan.hasScalarVFOnly() || vputils::onlyScalarValuesUsed(WidenNewIV)) {
+ WidenNewIV->replaceAllUsesWith(CanonicalIV);
+ WidenNewIV->eraseFromParent();
return;
+ }
VPBasicBlock *HeaderVPBB = LoopRegion->getEntryBasicBlock();
for (VPRecipeBase &Phi : HeaderVPBB->phis()) {
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
index f352fa12e1093..44d17756f6aba 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
@@ -107,7 +107,7 @@ define void @masked_strided1(ptr noalias nocapture readonly %p, ptr noalias noca
; PREDICATED_TAIL_FOLDING-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], [[TMP1]]
; PREDICATED_TAIL_FOLDING-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i32(i32 [[INDEX_NEXT]], i32 1024)
; PREDICATED_TAIL_FOLDING-NEXT: [[TMP14:%.*]] = extractelement <vscale x 16 x i1> [[ACTIVE_LANE_MASK_NEXT]], i64 0
-; PREDICATED_TAIL_FOLDING-NEXT: [[VEC_IND_NEXT]] = add <vscale x 16 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]]
+; PREDICATED_TAIL_FOLDING-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <vscale x 16 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]]
; PREDICATED_TAIL_FOLDING-NEXT: br i1 [[TMP14]], label [[VECTOR_BODY]], label [[MIDDLE_BLOCK:%.*]], !llvm.loop [[LOOP0:![0-9]+]]
; PREDICATED_TAIL_FOLDING: middle.block:
; PREDICATED_TAIL_FOLDING-NEXT: br label [[FOR_END:%.*]]
@@ -233,7 +233,7 @@ define void @masked_strided2(ptr noalias nocapture readnone %p, ptr noalias noca
; PREDICATED_TAIL_FOLDING-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], [[TMP1]]
; PREDICATED_TAIL_FOLDING-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i32(i32 [[INDEX_NEXT]], i32 1024)
; PREDICATED_TAIL_FOLDING-NEXT: [[TMP11:%.*]] = extractelement <vscale x 16 x i1> [[ACTIVE_LANE_MASK_NEXT]], i64 0
-; PREDICATED_TAIL_FOLDING-NEXT: [[VEC_IND_NEXT]] = add <vscale x 16 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]]
+; PREDICATED_TAIL_FOLDING-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <vscale x 16 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]]
; PREDICATED_TAIL_FOLDING-NEXT: br i1 [[TMP11]], label [[VECTOR_BODY]], label [[MIDDLE_BLOCK:%.*]], !llvm.loop [[LOOP3:![0-9]+]]
; PREDICATED_TAIL_FOLDING: middle.block:
; PREDICATED_TAIL_FOLDING-NEXT: br label [[FOR_END:%.*]]
@@ -363,7 +363,7 @@ define void @masked_strided3(ptr noalias nocapture readnone %p, ptr noalias noca
; PREDICATED_TAIL_FOLDING-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], [[TMP1]]
; PREDICATED_TAIL_FOLDING-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i32(i32 [[INDEX_NEXT]], i32 1024)
; PREDICATED_TAIL_FOLDING-NEXT: [[TMP13:%.*]] = extractelement <vscale x 16 x i1> [[ACTIVE_LANE_MASK_NEXT]], i64 0
-; PREDICATED_TAIL_FOLDING-NEXT: [[VEC_IND_NEXT]] = add <vscale x 16 x i32> [[VEC_IND]], [[BROADCAST_SPLAT4]]
+; PREDICATED_TAIL_FOLDING-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <vscale x 16 x i32> [[VEC_IND]], [[BROADCAST_SPLAT4]]
; PREDICATED_TAIL_FOLDING-NEXT: br i1 [[TMP13]], label [[VECTOR_BODY]], label [[MIDDLE_BLOCK:%.*]], !llvm.loop [[LOOP4:![0-9]+]]
; PREDICATED_TAIL_FOLDING: middle.block:
; PREDICATED_TAIL_FOLDING-NEXT: br label [[FOR_END:%.*]]
@@ -519,7 +519,7 @@ define void @masked_strided_factor4(ptr noalias nocapture readonly %p, ptr noali
; PREDICATED_TAIL_FOLDING-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], [[TMP1]]
; PREDICATED_TAIL_FOLDING-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i32(i32 [[INDEX_NEXT]], i32 1024)
; PREDICATED_TAIL_FOLDING-NEXT: [[TMP18:%.*]] = extractelement <vscale x 16 x i1> [[ACTIVE_LANE_MASK_NEXT]], i64 0
-; PREDICATED_TAIL_FOLDING-NEXT: [[VEC_IND_NEXT]] = add <vscale x 16 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]]
+; PREDICATED_TAIL_FOLDING-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <vscale x 16 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]]
; PREDICATED_TAIL_FOLDING-NEXT: br i1 [[TMP18]], label [[VECTOR_BODY]], label [[MIDDLE_BLOCK:%.*]], !llvm.loop [[LOOP5:![0-9]+]]
; PREDICATED_TAIL_FOLDING: middle.block:
; PREDICATED_TAIL_FOLDING-NEXT: br label [[FOR_END:%.*]]
diff --git a/llvm/test/Transforms/LoopVectorize/ARM/active-lane-mask.ll b/llvm/test/Transforms/LoopVectorize/ARM/active-lane-mask.ll
index 3ffafa404269b..df5afc66ed877 100644
--- a/llvm/test/Transforms/LoopVectorize/ARM/active-lane-mask.ll
+++ b/llvm/test/Transforms/LoopVectorize/ARM/active-lane-mask.ll
@@ -17,21 +17,19 @@ define void @f0(ptr noalias %dst, ptr readonly %src, i64 %n) #0 {
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]]
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 16
-; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 [[INDEX]], i64 [[N]])
+; CHECK-NEXT: [[TMP0:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[ACTIVE_LANE_MASK1:%.*]] = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 [[TMP0]], i64 [[N]])
-; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[INDEX]]
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[TMP0]]
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i32 16
-; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 [[TMP1]], <16 x i1> [[ACTIVE_LANE_MASK]], <16 x i8> poison)
+; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 [[TMP1]], <16 x i1> [[ACTIVE_LANE_MASK1]], <16 x i8> poison)
; CHECK-NEXT: [[WIDE_MASKED_LOAD2:%.*]] = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 [[TMP3]], <16 x i1> [[ACTIVE_LANE_MASK1]], <16 x i8> poison)
; CHECK-NEXT: [[TMP4:%.*]] = mul <16 x i8> [[WIDE_MASKED_LOAD]], splat (i8 3)
; CHECK-NEXT: [[TMP5:%.*]] = mul <16 x i8> [[WIDE_MASKED_LOAD2]], splat (i8 3)
-; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[INDEX]]
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[TMP0]]
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[TMP6]], i32 16
-; CHECK-NEXT: call void @llvm.masked.store.v16i8.p0(<16 x i8> [[TMP4]], ptr align 1 [[TMP6]], <16 x i1> [[ACTIVE_LANE_MASK]])
+; CHECK-NEXT: call void @llvm.masked.store.v16i8.p0(<16 x i8> [[TMP4]], ptr align 1 [[TMP6]], <16 x i1> [[ACTIVE_LANE_MASK1]])
; CHECK-NEXT: call void @llvm.masked.store.v16i8.p0(<16 x i8> [[TMP5]], ptr align 1 [[TMP8]], <16 x i1> [[ACTIVE_LANE_MASK1]])
-; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 32
+; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[TMP0]], 32
; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
diff --git a/llvm/test/Transforms/LoopVectorize/ARM/mve-gather-scatter-tailpred.ll b/llvm/test/Transforms/LoopVectorize/ARM/mve-gather-scatter-tailpred.ll
index 3ed25a18d91f7..f1345281704b5 100644
--- a/llvm/test/Transforms/LoopVectorize/ARM/mve-gather-scatter-tailpred.ll
+++ b/llvm/test/Transforms/LoopVectorize/ARM/mve-gather-scatter-tailpred.ll
@@ -193,7 +193,7 @@ define void @test_stride3_4i32(ptr readonly %data, ptr noalias nocapture %dst, i
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[DST:%.*]], i32 [[INDEX]]
; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0(<4 x i32> [[TMP4]], ptr align 4 [[TMP5]], <4 x i1> [[ACTIVE_LANE_MASK]])
; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4
-; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4)
+; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i32> [[VEC_IND]], splat (i32 4)
; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
; CHECK: middle.block:
@@ -240,7 +240,7 @@ define void @test_stride4_4i32(ptr readonly %data, ptr noalias nocapture %dst, i
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[DST:%.*]], i32 [[INDEX]]
; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0(<4 x i32> [[TMP4]], ptr align 4 [[TMP5]], <4 x i1> [[ACTIVE_LANE_MASK]])
; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4
-; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4)
+; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i32> [[VEC_IND]], splat (i32 4)
; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
; CHECK: middle.block:
diff --git a/llvm/test/Transforms/LoopVectorize/ARM/mve-reg-pressure-spills.ll b/llvm/test/Transforms/LoopVectorize/ARM/mve-reg-pressure-spills.ll
deleted file mode 100644
index 193bd60a9dfe2..0000000000000
--- a/llvm/test/Transforms/LoopVectorize/ARM/mve-reg-pressure-spills.ll
+++ /dev/null
@@ -1,268 +0,0 @@
-; REQUIRES: asserts
-; RUN: opt -mcpu=cortex-m55 -passes=loop-vectorize -disable-output -debug-only=loop-vectorize,vplan -vplan-verify-each -vectorizer-consider-reg-pressure=false %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-NOPRESSURE
-; RUN: opt -mcpu=cortex-m55 -passes=loop-vectorize -disable-output -debug-only=loop-vectorize,vplan -vplan-verify-each -vectorizer-consider-reg-pressure=true %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-PRESSURE
-; RUN: opt -mcpu=cortex-m55 -passes=loop-vectorize -disable-output -debug-only=loop-vectorize,vplan -vplan-verify-each %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-PRESSURE
-
-target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
-target triple = "thumbv8.1m.main-unknown-none-eabihf"
-
-; In this function the spills make it not profitable to vectorize if considering
-; register pressure.
-define void @spills_not_profitable(ptr %in1, ptr %in2, ptr %out, i32 %n) {
-; CHECK-LABEL: LV: Checking a loop in 'spills_not_profitable'
-; CHECK: LV: Scalar loop costs: 86
-; CHECK-NOPRESSURE: Cost for VF 2: 394 (Estimated cost per lane: 197.0)
-; CHECK-NOPRESSURE: Cost for VF 4: 338 (Estimated cost per lane: 84.5)
-; CHECK-NOPRESSURE: LV: Selecting VF: 4
-; CHECK-PRESSURE: LV(REG): Cost of 50 from 25 spills of Generic::VectorRC
-; CHECK-PRESSURE-NEXT: Cost for VF 2: 444 (Estimated cost per lane: 222.0)
-; CHECK-PRESSURE: LV(REG): Cost of 50 from 25 spills of Generic::VectorRC
-; CHECK-PRESSURE-NEXT: Cost for VF 4: 388 (Estimated cost per lane: 97.0)
-; CHECK-PRESSURE: LV: Selecting VF: 1
-entry:
- %cmp = icmp eq i32 %n, 0
- br i1 %cmp, label %exit, label %for.body
-
-for.body:
- %i = phi i32 [ %inc, %for.body ], [ 0, %entry ]
- %x4 = phi float [ %x4.next, %for.body ], [ 0.000000e+00, %entry ]
- %x3 = phi float [ %x3.next, %for.body ], [ 0.000000e+00, %entry ]
- %x2 = phi float [ %x2.next, %for.body ], [ 0.000000e+00, %entry ]
- %x1 = phi float [ %x1.next, %for.body ], [ 0.000000e+00, %entry ]
- %x0 = phi float [ %x0.next, %for.body ], [ 0.000000e+00, %entry ]
- %acc7 = phi float [ %acc7.next, %for.body ], [ 0.000000e+00, %entry ]
- %acc6 = phi float [ %acc6.next, %for.body ], [ 0.000000e+00, %entry ]
- %acc5 = phi float [ %acc5.next, %for.body ], [ 0.000000e+00, %entry ]
- %acc4 = phi float [ %acc4.next, %for.body ], [ 0.000000e+00, %entry ]
- %acc3 = phi float [ %acc3.next, %for.body ], [ 0.000000e+00, %entry ]
- %acc2 = phi float [ %acc2.next, %for.body ], [ 0.000000e+00, %entry ]
- %acc1 = phi float [ %acc1.next, %for.body ], [ 0.000000e+00, %entry ]
- %acc0 = phi float [ %acc0.next, %for.body ], [ 0.000000e+00, %entry ]
- %in1.addr = phi ptr [ %in1.addr.next, %for.body ], [ %in1, %entry ]
- %in2.addr = phi ptr [ %in2.addr.next, %for.body ], [ %in2, %entry ]
- %incdec.ptr = getelementptr inbounds nuw i8, ptr %in1.addr, i32 4
- %0 = load float, ptr %in1.addr, align 4
- %incdec.ptr1 = getelementptr inbounds nuw i8, ptr %in2.addr, i32 4
- %1 = load float, ptr %in2.addr, align 4
- %mul = fmul fast float %0, %x0
- %add = fadd fast float %mul, %acc0
- %mul2 = fmul fast float %0, %x1
- %add3 = fadd fast float %mul2, %acc1
- %mul4 = fmul fast float %0, %x2
- %add5 = fadd fast float %mul4, %acc2
- %mul6 = fmul fast float %0, %x3
- %add7 = fadd fast float %mul6, %acc3
- %mul8 = fmul fast float %0, %x4
- %add9 = fadd fast float %mul8, %acc4
- %mul10 = fmul fast float %1, %0
- %add11 = fadd fast float %mul10, %acc7
- %incdec.ptr12 = getelementptr inbounds nuw i8, ptr %in1.addr, i32 8
- %2 = load float, ptr %incdec.ptr, align 4
- %incdec.ptr13 = getelementptr inbounds nuw i8, ptr %in2.addr, i32 8
- %x0.next = load float, ptr %incdec.ptr1, align 4
- %mul14 = fmul fast float %2, %x1
- %add15 = fadd fast float %add, %mul14
- %mul16 = fmul fast float %2, %x2
- %add17 = fadd fast float %add3, %mul16
- %mul18 = fmul fast float %2, %x3
- %add19 = fadd fast float %add5, %mul18
- %mul20 = fmul fast float %2, %x4
- %add21 = fadd fast float %add7, %mul20
- %mul22 = fmul fast float %2, %1
- %add23 = fadd fast float %mul22, %acc6
- %mul24 = fmul fast float %x0.next, %2
- %add25 = fadd fast float %add11, %mul24
- %incdec.ptr26 = getelementptr inbounds nuw i8, ptr %in1.addr, i32 12
- %4 = load float, ptr %incdec.ptr12, align 4
- %incdec.ptr27 = getelementptr inbounds nuw i8, ptr %in2.addr, i32 12
- %x1.next = load float, ptr %incdec.ptr13, align 4
- %mul28 = fmul fast float %4, %x2
- %add29 = fadd fast float %add15, %mul28
- %mul30 = fmul fast float %4, %x3
- %add31 = fadd fast float %add17, %mul30
- %mul32 = fmul fast float %4, %x4
- %add33 = fadd fast float %add19, %mul32
- %mul34 = fmul fast float %4, %1
- %add35 = fadd fast float %mul34, %acc5
- %mul36 = fmul fast float %4, %x0.next
- %add37 = fadd fast float %add23, %mul36
- %mul38 = fmul fast float %x1.next, %4
- %add39 = fadd fast float %add25, %mul38
- %incdec.ptr40 = getelementptr inbounds nuw i8, ptr %in1.addr, i32 16
- %6 = load float, ptr %incdec.ptr26, align 4
- %incdec.ptr41 = getelementptr inbounds nuw i8, ptr %in2.addr, i32 16
- %x2.next = load float, ptr %incdec.ptr27, align 4
- %mul42 = fmul fast float %6, %x3
- %add43 = fadd fast float %add29, %mul42
- %mul44 = fmul fast float %6, %x4
- %acc1.next = fadd fast float %add31, %mul44
- %mul46 = fmul fast float %6, %1
- %add47 = fadd fast float %add9, %mul46
- %mul48 = fmul fast float %6, %x0.next
- %add49 = fadd fast float %add35, %mul48
- %mul50 = fmul fast float %6, %x1.next
- %add51 = fadd fast float %add37, %mul50
- %mul52 = fmul fast float %x2.next, %6
- %add53 = fadd fast float %add39, %mul52
- %incdec.ptr54 = getelementptr inbounds nuw i8, ptr %in1.addr, i32 20
- %8 = load float, ptr %incdec.ptr40, align 4
- %incdec.ptr55 = getelementptr inbounds nuw i8, ptr %in2.addr, i32 20
- %x3.next = load float, ptr %incdec.ptr41, align 4
- %mul56 = fmul fast float %8, %x4
- %acc0.next = fadd fast float %add43, %mul56
- %mul58 = fmul fast float %8, %1
- %add59 = fadd fast float %add21, %mul58
- %mul60 = fmul fast float %8, %x0.next
- %add61 = fadd fast float %add47, %mul60
- %mul62 = fmul fast float %8, %x1.next
- %add63 = fadd fast float %add49, %mul62
- %mul64 = fmul fast float %8, %x2.next
- %add65 = fadd fast float %add51, %mul64
- %mul66 = fmul fast float %x3.next, %8
- %add67 = fadd fast float %add53, %mul66
- %in1.addr.next = getelementptr inbounds nuw i8, ptr %in1.addr, i32 24
- %10 = load float, ptr %incdec.ptr54, align 4
- %in2.addr.next = getelementptr inbounds nuw i8, ptr %in2.addr, i32 24
- %x4.next = load float, ptr %incdec.ptr55, align 4
- %mul70 = fmul fast float %10, %1
- %acc2.next = fadd fast float %add33, %mul70
- %mul72 = fmul fast float %10, %x0.next
- %acc3.next = fadd fast float %add59, %mul72
- %mul74 = fmul fast float %10, %x1.next
- %acc4.next = fadd fast float %add61, %mul74
- %mul76 = fmul fast float %10, %x2.next
- %acc5.next = fadd fast float %add63, %mul76
- %mul78 = fmul fast float %10, %x3.next
- %acc6.next = fadd fast float %add65, %mul78
- %mul80 = fmul fast float %x4.next, %10
- %acc7.next = fadd fast float %add67, %mul80
- %inc = add nuw i32 %i, 1
- %exitcond = icmp eq i32 %inc, %n
- br i1 %exitcond, label %exit, label %for.body
-
-exit:
- %acc0.exit = phi float [ 0.000000e+00, %entry ], [ %acc0.next, %for.body ]
- %acc1.exit = phi float [ 0.000000e+00, %entry ], [ %acc1.next, %for.body ]
- %acc2.exit = phi float [ 0.000000e+00, %entry ], [ %acc2.next, %for.body ]
- %acc3.exit = phi float [ 0.000000e+00, %entry ], [ %acc3.next, %for.body ]
- %acc4.exit = phi float [ 0.000000e+00, %entry ], [ %acc4.next, %for.body ]
- %acc5.exit = phi float [ 0.000000e+00, %entry ], [ %acc5.next, %for.body ]
- %acc6.exit = phi float [ 0.000000e+00, %entry ], [ %acc6.next, %for.body ]
- %acc7.exit = phi float [ 0.000000e+00, %entry ], [ %acc7.next, %for.body ]
- store float %acc0.exit, ptr %out, align 4
- %arrayidx82 = getelementptr inbounds nuw i8, ptr %out, i32 4
- store float %acc1.exit, ptr %arrayidx82, align 4
- %arrayidx83 = getelementptr inbounds nuw i8, ptr %out, i32 8
- store float %acc2.exit, ptr %arrayidx83, align 4
- %arrayidx84 = getelementptr inbounds nuw i8, ptr %out, i32 12
- store float %acc3.exit, ptr %arrayidx84, align 4
- %arrayidx85 = getelementptr inbounds nuw i8, ptr %out, i32 16
- store float %acc4.exit, ptr %arrayidx85, align 4
- %arrayidx86 = getelementptr inbounds nuw i8, ptr %out, i32 20
- store float %acc5.exit, ptr %arrayidx86, align 4
- %arrayidx87 = getelementptr inbounds nuw i8, ptr %out, i32 24
- store float %acc6.exit, ptr %arrayidx87, align 4
- %arrayidx88 = getelementptr inbounds nuw i8, ptr %out, i32 28
- store float %acc7.exit, ptr %arrayidx88, align 4
- ret void
-}
-
-; In this function we have spills but it is still profitable to vectorize when
-; considering register pressure.
-define void @spills_profitable(ptr %in1, ptr %in2, ptr %out, i32 %n, i32 %m) {
-; CHECK-LABEL: LV: Checking a loop in 'spills_profitable'
-; CHECK: LV: Scalar loop costs: 54
-; CHECK-NOPRESSURE: Cost for VF 2: 1530 (Estimated cost per lane: 765.0)
-; CHECK-NOPRESSURE: Cost for VF 4: 38 (Estimated cost per lane: 9.5)
-; CHECK-PRESSURE: LV(REG): Cost of 4 from 2 spills of Generic::ScalarRC
-; CHECK-PRESSURE-NEXT: Cost for VF 2: 1534 (Estimated cost per lane: 767.0)
-; CHECK-PRESSURE: LV(REG): Cost of 6 from 3 spills of Generic::VectorRC
-; CHECK-PRESSURE-NEXT: Cost for VF 4: 44 (Estimated cost per lane: 11.0)
-; CHECK: LV: Selecting VF: 4
-entry:
- %cmp = icmp eq i32 %n, 0
- br i1 %cmp, label %exit, label %for.body.preheader
-
-for.body.preheader:
- %add.ptr3.idx = mul i32 %m, 12
- %add.ptr3 = getelementptr inbounds nuw i8, ptr %in1, i32 %add.ptr3.idx
- %add.ptr1.idx = shl i32 %m, 3
- %add.ptr1 = getelementptr inbounds nuw i8, ptr %in1, i32 %add.ptr1.idx
- %add.ptr = getelementptr inbounds nuw i32, ptr %in1, i32 %m
- br label %for.body
-
-for.body:
- %i = phi i32 [...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/191276
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