[llvm] [WebAssembly][GlobalISel] Add legalization & selection of most integer ops (PR #190234)
Demetrius Kanios via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 8 14:16:27 PDT 2026
https://github.com/QuantumSegfault updated https://github.com/llvm/llvm-project/pull/190234
>From 6be5a44d589acda067cac72bc9e23cfa709e7735 Mon Sep 17 00:00:00 2001
From: Demetrius Kanios <demetrius at kanios.net>
Date: Thu, 2 Apr 2026 11:54:20 -0700
Subject: [PATCH 1/7] Add legalization, regbank, and isel for most integer ops.
---
.../GISel/WebAssemblyInstructionSelector.cpp | 52 +++
.../GISel/WebAssemblyLegalizerInfo.cpp | 61 ++-
.../GISel/WebAssemblyLegalizerInfo.h | 3 +
.../GISel/WebAssemblyRegisterBankInfo.cpp | 41 +-
.../WebAssembly/WebAssemblyInstrInteger.td | 8 +
.../GlobalISel/instruction-select/bitwise.mir | 433 +++++++++++++++++-
.../GlobalISel/instruction-select/consts.mir | 76 +++
.../instruction-select/ext-trunc.mir | 186 ++++++++
.../instruction-select/int-arithmetic.mir | 271 ++++++++++-
.../WebAssembly/GlobalISel/legalizer/add.mir | 61 ++-
.../WebAssembly/GlobalISel/legalizer/and.mir | 116 +++++
.../GlobalISel/legalizer/anyext.mir | 95 ++++
.../WebAssembly/GlobalISel/legalizer/ashr.mir | 331 +++++++++++++
.../GlobalISel/legalizer/constant.mir | 145 ++++++
.../WebAssembly/GlobalISel/legalizer/ctlz.mir | 152 ++++++
.../GlobalISel/legalizer/ctlz_zero_undef.mir | 148 ++++++
.../GlobalISel/legalizer/ctpop.mir | 148 ++++++
.../WebAssembly/GlobalISel/legalizer/cttz.mir | 148 ++++++
.../GlobalISel/legalizer/cttz_zero_undef.mir | 144 ++++++
.../WebAssembly/GlobalISel/legalizer/fshl.mir | 393 ++++++++++++++++
.../WebAssembly/GlobalISel/legalizer/fshr.mir | 389 ++++++++++++++++
.../GlobalISel/legalizer/implicit_def.mir | 72 +++
.../WebAssembly/GlobalISel/legalizer/lshr.mir | 286 ++++++++++++
.../WebAssembly/GlobalISel/legalizer/mul.mir | 91 ++++
.../WebAssembly/GlobalISel/legalizer/or.mir | 117 +++++
.../WebAssembly/GlobalISel/legalizer/rotl.mir | 303 ++++++++++++
.../WebAssembly/GlobalISel/legalizer/rotr.mir | 303 ++++++++++++
.../WebAssembly/GlobalISel/legalizer/sdiv.mir | 126 +++++
.../WebAssembly/GlobalISel/legalizer/sext.mir | 138 ++++++
.../GlobalISel/legalizer/sext_inreg.mir | 181 ++++++++
.../WebAssembly/GlobalISel/legalizer/shl.mir | 278 +++++++++++
.../WebAssembly/GlobalISel/legalizer/srem.mir | 126 +++++
.../WebAssembly/GlobalISel/legalizer/sub.mir | 91 ++++
.../GlobalISel/legalizer/trunc.mir | 95 ++++
.../WebAssembly/GlobalISel/legalizer/udiv.mir | 99 ++++
.../WebAssembly/GlobalISel/legalizer/urem.mir | 99 ++++
.../WebAssembly/GlobalISel/legalizer/xor.mir | 116 +++++
.../WebAssembly/GlobalISel/legalizer/zext.mir | 103 +++++
.../GlobalISel/regbankselect/bitwise.mir | 414 ++++++++++++++++-
.../GlobalISel/regbankselect/consts.mir | 72 +++
.../GlobalISel/regbankselect/ext-trunc.mir | 177 +++++++
.../regbankselect/int-arithmetic.mir | 259 ++++++++++-
42 files changed, 6913 insertions(+), 34 deletions(-)
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/consts.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/ext-trunc.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/and.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/anyext.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ashr.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/constant.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ctlz.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ctlz_zero_undef.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ctpop.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/cttz.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/cttz_zero_undef.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/fshl.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/fshr.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/implicit_def.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/lshr.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/mul.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/or.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/rotl.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/rotr.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sdiv.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sext.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sext_inreg.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/shl.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/srem.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sub.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/trunc.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/udiv.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/urem.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/xor.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/zext.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/consts.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/ext-trunc.mir
diff --git a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp
index 463d3977c329d..7359156ccf60c 100644
--- a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp
+++ b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp
@@ -23,6 +23,7 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/IR/IntrinsicsWebAssembly.h"
+#include "llvm/Support/ErrorHandling.h"
#define DEBUG_TYPE "wasm-isel"
@@ -83,7 +84,35 @@ WebAssemblyInstructionSelector::WebAssemblyInstructionSelector(
{
}
+static const TargetRegisterClass &getRegClassForBank(const RegisterBank &RB) {
+ switch (RB.getID()) {
+ case WebAssembly::I32RegBankID:
+ return WebAssembly::I32RegClass;
+ case WebAssembly::I64RegBankID:
+ return WebAssembly::I64RegClass;
+ case WebAssembly::F32RegBankID:
+ return WebAssembly::F32RegClass;
+ case WebAssembly::F64RegBankID:
+ return WebAssembly::F64RegClass;
+ case WebAssembly::EXNREFRegBankID:
+ return WebAssembly::EXNREFRegClass;
+ case WebAssembly::EXTERNREFRegBankID:
+ return WebAssembly::EXTERNREFRegClass;
+ case WebAssembly::FUNCREFRegBankID:
+ return WebAssembly::FUNCREFRegClass;
+ case WebAssembly::V128RegBankID:
+ return WebAssembly::V128RegClass;
+ default:
+ reportFatalInternalError(
+ "Found unexpected RegisterBank in `getRegClassForBank`");
+ }
+}
+
bool WebAssemblyInstructionSelector::select(MachineInstr &I) {
+ MachineBasicBlock &MBB = *I.getParent();
+ MachineFunction &MF = *MBB.getParent();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+
if (!I.isPreISelOpcode()) {
return true;
}
@@ -91,6 +120,29 @@ bool WebAssemblyInstructionSelector::select(MachineInstr &I) {
if (selectImpl(I, *CoverageInfo))
return true;
+ using namespace TargetOpcode;
+
+ switch (I.getOpcode()) {
+ case G_IMPLICIT_DEF: {
+ const Register DefReg = I.getOperand(0).getReg();
+ const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(DefReg);
+
+ const TargetRegisterClass *DefRC =
+ dyn_cast<const TargetRegisterClass *>(RegClassOrBank);
+
+ if (!DefRC) {
+ const RegisterBank &RB = *cast<const RegisterBank *>(RegClassOrBank);
+ DefRC = &getRegClassForBank(RB);
+ }
+
+ I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF));
+
+ return RBI.constrainGenericRegister(DefReg, *DefRC, MRI) != nullptr;
+ }
+ default:
+ break;
+ }
+
return false;
}
diff --git a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.cpp b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.cpp
index ecbaf79db751d..0b9bbc1a6853a 100644
--- a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.cpp
+++ b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.cpp
@@ -12,6 +12,8 @@
#include "WebAssemblyLegalizerInfo.h"
#include "WebAssemblySubtarget.h"
+#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
+#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
#define DEBUG_TYPE "wasm-legalinfo"
@@ -25,18 +27,71 @@ WebAssemblyLegalizerInfo::WebAssemblyLegalizerInfo(
const LLT s32 = LLT::scalar(32);
const LLT s64 = LLT::scalar(64);
- getActionDefinitionsBuilder({G_CONSTANT, G_ADD, G_AND})
+ getActionDefinitionsBuilder({G_CONSTANT, G_IMPLICIT_DEF, G_ADD, G_SUB, G_MUL,
+ G_UDIV, G_SDIV, G_UREM, G_SREM, G_AND, G_OR,
+ G_XOR})
.legalFor({s32, s64})
.widenScalarToNextPow2(0)
.clampScalar(0, s32, s64);
- getActionDefinitionsBuilder({G_ASHR, G_SHL})
+ getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL})
.legalFor({{s32, s32}, {s64, s64}})
.widenScalarToNextPow2(0)
.clampScalar(0, s32, s64)
.scalarSameSizeAs(1, 0);
- getActionDefinitionsBuilder(G_SEXT_INREG).lower();
+ getActionDefinitionsBuilder(
+ {G_CTLZ, G_CTLZ_ZERO_UNDEF, G_CTTZ, G_CTTZ_ZERO_UNDEF, G_CTPOP})
+ .legalFor({{s32, s32}, {s64, s64}})
+ .widenScalarToNextPow2(1)
+ .clampScalar(1, s32, s64)
+ .scalarSameSizeAs(0, 1);
+
+ getActionDefinitionsBuilder({G_ROTL, G_ROTR})
+ .legalFor({{s32, s32}, {s64, s64}})
+ .scalarSameSizeAs(1, 0)
+ .lower();
+
+ getActionDefinitionsBuilder({G_FSHL, G_FSHR}).lower();
+
+ getActionDefinitionsBuilder({G_ANYEXT, G_SEXT, G_ZEXT})
+ .legalFor({{s64, s32}})
+ .clampScalar(0, s64, s64)
+ .clampScalar(1, s32, s32);
+
+ getActionDefinitionsBuilder(G_TRUNC)
+ .legalFor({{s32, s64}})
+ .clampScalar(0, s32, s32)
+ .clampScalar(1, s64, s64);
+
+ getActionDefinitionsBuilder(G_SEXT_INREG)
+ .clampScalar(0, s32, s64)
+ .customFor(ST.hasSignExt(), {s32, s64})
+ .lower();
getLegacyLegalizerInfo().computeTables();
}
+
+bool WebAssemblyLegalizerInfo::legalizeCustom(
+ LegalizerHelper &Helper, MachineInstr &MI,
+ LostDebugLocObserver &LocObserver) const {
+ switch (MI.getOpcode()) {
+ case TargetOpcode::G_SEXT_INREG: {
+ assert(MI.getOperand(2).isImm() && "Expected immediate");
+
+ // Mark only 8/16/32-bit SEXT_INREG as legal
+ auto [DstType, SrcType] = MI.getFirst2LLTs();
+ auto ExtFromWidth = MI.getOperand(2).getImm();
+
+ if (ExtFromWidth == 8 || ExtFromWidth == 16 ||
+ (DstType.getScalarSizeInBits() == 64 && ExtFromWidth == 32)) {
+ return true;
+ }
+
+ return Helper.lower(MI, 0, DstType);
+ }
+ default:
+ break;
+ }
+ return false;
+}
diff --git a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.h b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.h
index 61f4aa621d44f..45f21d7190abe 100644
--- a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.h
+++ b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.h
@@ -24,6 +24,9 @@ class WebAssemblySubtarget;
class WebAssemblyLegalizerInfo : public LegalizerInfo {
public:
WebAssemblyLegalizerInfo(const WebAssemblySubtarget &ST);
+
+ bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
+ LostDebugLocObserver &LocObserver) const override;
};
} // namespace llvm
#endif
diff --git a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyRegisterBankInfo.cpp b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyRegisterBankInfo.cpp
index 4aaf04eb2496e..f7be420b49d2f 100644
--- a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyRegisterBankInfo.cpp
+++ b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyRegisterBankInfo.cpp
@@ -88,14 +88,51 @@ WebAssemblyRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
using namespace TargetOpcode;
switch (Opc) {
+ case G_CONSTANT:
+ OperandsMapping = getOperandsMapping({&Op0IntValueMapping, nullptr});
+ break;
+ case G_IMPLICIT_DEF:
+ OperandsMapping = &Op0IntValueMapping;
+ break;
case G_ADD:
+ case G_SUB:
+ case G_MUL:
+ case G_UDIV:
+ case G_SDIV:
+ case G_UREM:
+ case G_SREM:
case G_AND:
+ case G_OR:
+ case G_XOR:
case G_ASHR:
+ case G_LSHR:
case G_SHL:
+ case G_CTLZ:
+ case G_CTLZ_ZERO_UNDEF:
+ case G_CTTZ:
+ case G_CTTZ_ZERO_UNDEF:
+ case G_CTPOP:
+ case G_ROTL:
+ case G_ROTR:
OperandsMapping = &Op0IntValueMapping;
break;
- case G_CONSTANT:
- OperandsMapping = getOperandsMapping({&Op0IntValueMapping, nullptr});
+ case G_ZEXT:
+ case G_ANYEXT:
+ case G_SEXT:
+ case G_TRUNC: {
+ const LLT Op1Ty = MRI.getType(MI.getOperand(1).getReg());
+ unsigned Op1Size = Op1Ty.getSizeInBits();
+
+ auto &Op1IntValueMapping =
+ WebAssembly::ValueMappings[Op1Size == 64 ? WebAssembly::I64Idx
+ : WebAssembly::I32Idx];
+ OperandsMapping =
+ getOperandsMapping({&Op0IntValueMapping, &Op1IntValueMapping});
+ break;
+ }
+ case G_SEXT_INREG:
+ OperandsMapping =
+ getOperandsMapping({&Op0IntValueMapping, &Op0IntValueMapping, nullptr});
break;
}
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInteger.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInteger.td
index 991507e883f28..99ca22e21f70b 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInteger.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInteger.td
@@ -82,10 +82,18 @@ defm LE_U : ComparisonInt<SETULE, "le_u", 0x4d, 0x58>;
defm GE_S : ComparisonInt<SETGE, "ge_s", 0x4e, 0x59>;
defm GE_U : ComparisonInt<SETUGE, "ge_u", 0x4f, 0x5a>;
+
defm CLZ : UnaryInt<ctlz, "clz ", 0x67, 0x79>;
+def : Pat<(ctlz_zero_undef I32:$src), (CLZ_I32 I32:$src)>;
+def : Pat<(ctlz_zero_undef I64:$src), (CLZ_I64 I64:$src)>;
+
defm CTZ : UnaryInt<cttz, "ctz ", 0x68, 0x7a>;
+def : Pat<(cttz_zero_undef I32:$src), (CTZ_I32 I32:$src)>;
+def : Pat<(cttz_zero_undef I64:$src), (CTZ_I64 I64:$src)>;
+
defm POPCNT : UnaryInt<ctpop, "popcnt", 0x69, 0x7b>;
+
defm EQZ_I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins),
[(set I32:$dst, (setcc I32:$src, 0, SETEQ))],
"i32.eqz \t$dst, $src", "i32.eqz", 0x45>;
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/bitwise.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/bitwise.mir
index c1c111606d15f..1a5943259b521 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/bitwise.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/bitwise.mir
@@ -23,7 +23,6 @@ body: |
%2:i32regbank(s32) = G_AND %0, %1
RETURN %2(s32), implicit-def $arguments
...
-
---
name: and_i64
alignment: 1
@@ -47,6 +46,96 @@ body: |
RETURN %2(s64), implicit-def $arguments
...
+---
+name: or_i32
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: or_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = OR_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:i32regbank(s32) = G_OR %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: or_i64
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: or_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = OR_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:i64regbank(s64) = G_OR %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
+
+---
+name: xor_i32
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: xor_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[XOR_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:i32regbank(s32) = G_XOR %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: xor_i64
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: xor_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[XOR_I64_:%[0-9]+]]:i64 = XOR_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[XOR_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:i64regbank(s64) = G_XOR %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
+
---
name: shl_i32
alignment: 1
@@ -69,7 +158,6 @@ body: |
%2:i32regbank(s32) = G_SHL %0, %1
RETURN %2(s32), implicit-def $arguments
...
-
---
name: shl_i64
alignment: 1
@@ -115,7 +203,6 @@ body: |
%2:i32regbank(s32) = G_ASHR %0, %1
RETURN %2(s32), implicit-def $arguments
...
-
---
name: ashr_i64
alignment: 1
@@ -138,3 +225,343 @@ body: |
%2:i64regbank(s64) = G_ASHR %0, %1
RETURN %2(s64), implicit-def $arguments
...
+
+---
+name: lshr_i32
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshr_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 5, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_U_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32regbank(s32) = G_CONSTANT i32 5
+ %2:i32regbank(s32) = G_LSHR %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: lshr_i64
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshr_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_U_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64regbank(s64) = G_CONSTANT i64 37
+ %2:i64regbank(s64) = G_LSHR %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
+
+---
+name: ctlz_i32
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CLZ_I32_:%[0-9]+]]:i32 = CLZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CLZ_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32regbank(s32) = G_CTLZ %0
+ RETURN %1(s32), implicit-def $arguments
+...
+---
+name: ctlz_i64
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CLZ_I64_:%[0-9]+]]:i64 = CLZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CLZ_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64regbank(s64) = G_CTLZ %0
+ RETURN %1(s64), implicit-def $arguments
+...
+
+---
+name: ctlz_zundef_i32
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_zundef_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CLZ_I32_:%[0-9]+]]:i32 = CLZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CLZ_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32regbank(s32) = G_CTLZ_ZERO_UNDEF %0
+ RETURN %1(s32), implicit-def $arguments
+...
+---
+name: ctlz_zundef_i64
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_zundef_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CLZ_I64_:%[0-9]+]]:i64 = CLZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CLZ_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64regbank(s64) = G_CTLZ_ZERO_UNDEF %0
+ RETURN %1(s64), implicit-def $arguments
+...
+
+---
+name: cttz_i32
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: cttz_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CTZ_I32_:%[0-9]+]]:i32 = CTZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CTZ_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32regbank(s32) = G_CTTZ %0
+ RETURN %1(s32), implicit-def $arguments
+...
+---
+name: cttz_i64
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: cttz_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTZ_I64_:%[0-9]+]]:i64 = CTZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CTZ_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64regbank(s64) = G_CTTZ %0
+ RETURN %1(s64), implicit-def $arguments
+...
+
+---
+name: cttz_zundef_i32
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: cttz_zundef_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CTZ_I32_:%[0-9]+]]:i32 = CTZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CTZ_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32regbank(s32) = G_CTTZ_ZERO_UNDEF %0
+ RETURN %1(s32), implicit-def $arguments
+...
+---
+name: cttz_zundef_i64
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: cttz_zundef_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTZ_I64_:%[0-9]+]]:i64 = CTZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CTZ_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64regbank(s64) = G_CTTZ_ZERO_UNDEF %0
+ RETURN %1(s64), implicit-def $arguments
+...
+
+---
+name: ctpop_i32
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctpop_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[POPCNT_I32_:%[0-9]+]]:i32 = POPCNT_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[POPCNT_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32regbank(s32) = G_CTPOP %0
+ RETURN %1(s32), implicit-def $arguments
+...
+---
+name: ctpop_i64
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctpop_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[POPCNT_I64_:%[0-9]+]]:i64 = POPCNT_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[POPCNT_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64regbank(s64) = G_CTPOP %0
+ RETURN %1(s64), implicit-def $arguments
+...
+
+---
+name: rotl_i32
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotl_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ROTL_I32_:%[0-9]+]]:i32 = ROTL_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[ROTL_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:i32regbank(s32) = G_ROTL %0, %1(s32)
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: rotl_i64
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotl_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[ROTL_I64_:%[0-9]+]]:i64 = ROTL_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[ROTL_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:i64regbank(s64) = G_ROTL %0, %1(s64)
+ RETURN %2(s64), implicit-def $arguments
+...
+
+---
+name: rotr_i32
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotr_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ROTR_I32_:%[0-9]+]]:i32 = ROTR_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[ROTR_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:i32regbank(s32) = G_ROTR %0, %1(s32)
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: rotr_i64
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotr_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[ROTR_I64_:%[0-9]+]]:i64 = ROTR_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[ROTR_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:i64regbank(s64) = G_ROTR %0, %1(s64)
+ RETURN %2(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/consts.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/consts.mir
new file mode 100644
index 0000000000000..f3ee685d18a85
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/consts.mir
@@ -0,0 +1,76 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: const_i32
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: const_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 0, implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CONST_I32_]], implicit-def $arguments
+ %0:i32regbank(s32) = G_CONSTANT i32 0
+ RETURN %0(s32), implicit-def $arguments
+...
+---
+name: const_i64
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: const_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 0, implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CONST_I64_]], implicit-def $arguments
+ %0:i64regbank(s64) = G_CONSTANT i64 0
+ RETURN %0(s64), implicit-def $arguments
+...
+
+---
+name: implicit_i32
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: implicit_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:i32 = IMPLICIT_DEF
+ ; CHECK-NEXT: RETURN [[DEF]], implicit-def $arguments
+ %0:i32regbank(s32) = G_IMPLICIT_DEF
+ RETURN %0(s32), implicit-def $arguments
+...
+---
+name: implicit_i64
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: implicit_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:i64 = IMPLICIT_DEF
+ ; CHECK-NEXT: RETURN [[DEF]], implicit-def $arguments
+ %0:i64regbank(s64) = G_IMPLICIT_DEF
+ RETURN %0(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/ext-trunc.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/ext-trunc.mir
new file mode 100644
index 0000000000000..6c150bd2884cf
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/ext-trunc.mir
@@ -0,0 +1,186 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: anyext
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: anyext
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I64_EXTEND_U_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i64regbank(s64) = G_ANYEXT %0
+ RETURN %1(s64), implicit-def $arguments
+...
+---
+name: sext
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sext
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[I64_EXTEND_S_I32_:%[0-9]+]]:i64 = I64_EXTEND_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I64_EXTEND_S_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i64regbank(s64) = G_SEXT %0
+ RETURN %1(s64), implicit-def $arguments
+...
+---
+name: zext
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: zext
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I64_EXTEND_U_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i64regbank(s64) = G_ZEXT %0
+ RETURN %1(s64), implicit-def $arguments
+...
+---
+name: trunc
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: trunc
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i32regbank(s32) = G_TRUNC %0
+ RETURN %1(s32), implicit-def $arguments
+...
+
+---
+name: sext_inreg_i32_8
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sext_inreg_i32_8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[I32_EXTEND8_S_I32_:%[0-9]+]]:i32 = I32_EXTEND8_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I32_EXTEND8_S_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32regbank(s32) = G_SEXT_INREG %0, 8
+ RETURN %1(s32), implicit-def $arguments
+...
+---
+name: sext_inreg_i64_8
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sext_inreg_i64_8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[I64_EXTEND8_S_I64_:%[0-9]+]]:i64 = I64_EXTEND8_S_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I64_EXTEND8_S_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64regbank(s64) = G_SEXT_INREG %0, 8
+ RETURN %1(s64), implicit-def $arguments
+...
+
+---
+name: sext_inreg_i32_16
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sext_inreg_i32_16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[I32_EXTEND16_S_I32_:%[0-9]+]]:i32 = I32_EXTEND16_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I32_EXTEND16_S_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32regbank(s32) = G_SEXT_INREG %0, 16
+ RETURN %1(s32), implicit-def $arguments
+...
+---
+name: sext_inreg_i64_16
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sext_inreg_i64_16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[I64_EXTEND16_S_I64_:%[0-9]+]]:i64 = I64_EXTEND16_S_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I64_EXTEND16_S_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64regbank(s64) = G_SEXT_INREG %0, 16
+ RETURN %1(s64), implicit-def $arguments
+...
+
+---
+name: sext_inreg_i64_32
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sext_inreg_i64_32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[I64_EXTEND32_S_I64_:%[0-9]+]]:i64 = I64_EXTEND32_S_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I64_EXTEND32_S_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64regbank(s64) = G_SEXT_INREG %0, 32
+ RETURN %1(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/int-arithmetic.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/int-arithmetic.mir
index 60c916c372636..2d13318da5a84 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/int-arithmetic.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/int-arithmetic.mir
@@ -23,7 +23,6 @@ body: |
%2:i32regbank(s32) = G_ADD %0, %1
RETURN %2(s32), implicit-def $arguments
...
-
---
name: add_i64
alignment: 1
@@ -46,3 +45,273 @@ body: |
%2:i64regbank(s64) = G_ADD %0, %1
RETURN %2(s64), implicit-def $arguments
...
+
+---
+name: sub_i32
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sub_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[SUB_I32_:%[0-9]+]]:i32 = SUB_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SUB_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:i32regbank(s32) = G_SUB %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: sub_i64
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sub_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[SUB_I64_:%[0-9]+]]:i64 = SUB_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SUB_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:i64regbank(s64) = G_SUB %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
+
+---
+name: mul_i32
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: mul_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[MUL_I32_:%[0-9]+]]:i32 = MUL_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[MUL_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:i32regbank(s32) = G_MUL %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: mul_i64
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: mul_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[MUL_I64_:%[0-9]+]]:i64 = MUL_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[MUL_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:i64regbank(s64) = G_MUL %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
+
+---
+name: udiv_i32
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: udiv_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[DIV_U_I32_:%[0-9]+]]:i32 = DIV_U_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[DIV_U_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:i32regbank(s32) = G_UDIV %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: udiv_i64
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: udiv_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[DIV_U_I64_:%[0-9]+]]:i64 = DIV_U_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[DIV_U_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:i64regbank(s64) = G_UDIV %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
+
+---
+name: sdiv_i32
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sdiv_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[DIV_S_I32_:%[0-9]+]]:i32 = DIV_S_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[DIV_S_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:i32regbank(s32) = G_SDIV %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: sdiv_i64
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sdiv_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[DIV_S_I64_:%[0-9]+]]:i64 = DIV_S_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[DIV_S_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:i64regbank(s64) = G_SDIV %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
+
+---
+name: urem_i32
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: urem_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[REM_U_I32_:%[0-9]+]]:i32 = REM_U_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[REM_U_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:i32regbank(s32) = G_UREM %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: urem_i64
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: urem_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[REM_U_I64_:%[0-9]+]]:i64 = REM_U_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[REM_U_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:i64regbank(s64) = G_UREM %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
+
+---
+name: srem_i32
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: srem_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[REM_S_I32_:%[0-9]+]]:i32 = REM_S_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[REM_S_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:i32regbank(s32) = G_SREM %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: srem_i64
+alignment: 1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: srem_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[REM_S_I64_:%[0-9]+]]:i64 = REM_S_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[REM_S_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:i64regbank(s64) = G_SREM %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/add.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/add.mir
index 0d12b749e461e..8865e0e730f61 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/add.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/add.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=-sign-ext -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NO-SIGNEXT
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=+sign-ext -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,SIGNEXT
---
name: add_i8_zext
@@ -35,16 +36,25 @@ body: |
bb.1.entry:
liveins: $arguments
- ; CHECK-LABEL: name: add_i8_sext
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ADD]], [[C]](s32)
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:i32(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; CHECK-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
+ ; NO-SIGNEXT-LABEL: name: add_i8_sext
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
+ ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ADD]], [[C]](s32)
+ ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:i32(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; NO-SIGNEXT-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: add_i8_sext
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; SIGNEXT-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
+ ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:i32(s32) = G_SEXT_INREG [[ADD]], 8
+ ; SIGNEXT-NEXT: RETURN [[SEXT_INREG]](s32), implicit-def $arguments
%2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s8) = G_TRUNC %2(s32)
%3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
@@ -113,16 +123,25 @@ body: |
bb.1.entry:
liveins: $arguments
- ; CHECK-LABEL: name: add_i16_sext
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ADD]], [[C]](s32)
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:i32(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; CHECK-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
+ ; NO-SIGNEXT-LABEL: name: add_i16_sext
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
+ ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ADD]], [[C]](s32)
+ ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:i32(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; NO-SIGNEXT-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: add_i16_sext
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; SIGNEXT-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
+ ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:i32(s32) = G_SEXT_INREG [[ADD]], 16
+ ; SIGNEXT-NEXT: RETURN [[SEXT_INREG]](s32), implicit-def $arguments
%2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s16) = G_TRUNC %2(s32)
%3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/and.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/and.mir
new file mode 100644
index 0000000000000..52c2de6715dd3
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/and.mir
@@ -0,0 +1,116 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: and_i1
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: and_i1
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]]
+ ; CHECK-NEXT: RETURN [[AND]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s1) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s1) = G_TRUNC %3(s32)
+ %4:_(s1) = G_AND %1, %0
+ %5:_(s32) = G_ANYEXT %4(s1)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: and_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: and_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]]
+ ; CHECK-NEXT: RETURN [[AND]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_AND %1, %0
+ %5:_(s32) = G_ANYEXT %4(s8)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: and_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: and_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]]
+ ; CHECK-NEXT: RETURN [[AND]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_AND %1, %0
+ %5:_(s32) = G_ANYEXT %4(s16)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: and_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: and_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]]
+ ; CHECK-NEXT: RETURN [[AND]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_AND %1, %0
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: and_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: and_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ARGUMENT_i64_1]], [[ARGUMENT_i64_]]
+ ; CHECK-NEXT: RETURN [[AND]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_AND %1, %0
+ RETURN %2(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/anyext.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/anyext.mir
new file mode 100644
index 0000000000000..7380ad857cd9d
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/anyext.mir
@@ -0,0 +1,95 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: aext_i8_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: aext_i8_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: RETURN [[ARGUMENT_i32_]](s32), implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %1(s32)
+ %2:i32(s32) = G_ANYEXT %0(s8)
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: aext_i8_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: aext_i8_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:i32(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[ANYEXT]](s64), implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %1(s32)
+ %2:i32(s64) = G_ANYEXT %0(s8)
+ RETURN %2(s64), implicit-def $arguments
+...
+---
+name: aext_i16_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: aext_i16_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: RETURN [[ARGUMENT_i32_]](s32), implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %1(s32)
+ %2:i32(s32) = G_ANYEXT %0(s16)
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: aext_i16_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: aext_i16_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:i32(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[ANYEXT]](s64), implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %1(s32)
+ %2:i32(s64) = G_ANYEXT %0(s16)
+ RETURN %2(s64), implicit-def $arguments
+...
+---
+name: aext_i32_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: aext_i32_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:i32(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[ANYEXT]](s64), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s64) = G_ANYEXT %0(s32)
+ RETURN %1(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ashr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ashr.mir
new file mode 100644
index 0000000000000..e38b3b87c9e8d
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ashr.mir
@@ -0,0 +1,331 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=-sign-ext -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NO-SIGNEXT
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=+sign-ext -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,SIGNEXT
+
+---
+name: ashr_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: ashr_i8
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+ ; NO-SIGNEXT-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C1]](s32)
+ ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
+ ; NO-SIGNEXT-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C]](s32)
+ ; NO-SIGNEXT-NEXT: RETURN [[ASHR1]](s32), implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: ashr_i8
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+ ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ARGUMENT_i32_]], 8
+ ; SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
+ ; SIGNEXT-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %1:_(s8) = G_CONSTANT i8 5
+ %3:_(s8) = G_ASHR %0, %1
+ %4:_(s32) = G_ANYEXT %3(s8)
+ RETURN %4(s32), implicit-def $arguments
+
+...
+---
+name: ashrv_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: ashrv_i8
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
+ ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; NO-SIGNEXT-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; NO-SIGNEXT-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C1]]
+ ; NO-SIGNEXT-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
+ ; NO-SIGNEXT-NEXT: RETURN [[ASHR1]](s32), implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: ashrv_i8
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ARGUMENT_i32_]], 8
+ ; SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; SIGNEXT-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C]]
+ ; SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
+ ; SIGNEXT-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_ASHR %0, %1
+ %5:_(s32) = G_ANYEXT %4(s8)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: ashr_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: ashr_i16
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
+ ; NO-SIGNEXT-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C1]](s32)
+ ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
+ ; NO-SIGNEXT-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C]](s32)
+ ; NO-SIGNEXT-NEXT: RETURN [[ASHR1]](s32), implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: ashr_i16
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
+ ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ARGUMENT_i32_]], 16
+ ; SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
+ ; SIGNEXT-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %1:_(s16) = G_CONSTANT i16 13
+ %3:_(s16) = G_ASHR %0, %1
+ %4:_(s32) = G_ANYEXT %3(s16)
+ RETURN %4(s32), implicit-def $arguments
+
+...
+---
+name: ashrv_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: ashrv_i16
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
+ ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; NO-SIGNEXT-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; NO-SIGNEXT-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C1]]
+ ; NO-SIGNEXT-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
+ ; NO-SIGNEXT-NEXT: RETURN [[ASHR1]](s32), implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: ashrv_i16
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ARGUMENT_i32_]], 16
+ ; SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; SIGNEXT-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C]]
+ ; SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
+ ; SIGNEXT-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_ASHR %0, %1
+ %5:_(s32) = G_ANYEXT %4(s16)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: ashr_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ashr_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ARGUMENT_i32_]], [[C]](s32)
+ ; CHECK-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_CONSTANT i32 21
+ %2:_(s32) = G_ASHR %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: ashrv_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ashrv_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]](s32)
+ ; CHECK-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_ASHR %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: ashr_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ashr_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ARGUMENT_i32_]], [[C]](s32)
+ ; CHECK-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s8) = G_CONSTANT i8 21
+ %2:_(s32) = G_ASHR %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: ashrv_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ashrv_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C]]
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ARGUMENT_i32_]], [[AND]](s32)
+ ; CHECK-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %2(s32)
+ %3:_(s32) = G_ASHR %0, %1
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: ashr_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ashr_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[ARGUMENT_i64_]], [[C]](s64)
+ ; CHECK-NEXT: RETURN [[ASHR]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_CONSTANT i64 37
+ %2:_(s64) = G_ASHR %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: ashrv_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ashrv_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]](s64)
+ ; CHECK-NEXT: RETURN [[ASHR]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_ASHR %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: ashr_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ashr_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[C]], [[C1]]
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[ARGUMENT_i64_]], [[AND]](s64)
+ ; CHECK-NEXT: RETURN [[ASHR]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s8) = G_CONSTANT i8 37
+ %2:_(s64) = G_ASHR %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: ashrv_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ashrv_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[ARGUMENT_i64_]], [[AND]](s64)
+ ; CHECK-NEXT: RETURN [[ASHR]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %2(s32)
+ %3:_(s64) = G_ASHR %0, %1
+ RETURN %3(s64), implicit-def $arguments
+
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/constant.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/constant.mir
new file mode 100644
index 0000000000000..41b06f5c5c836
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/constant.mir
@@ -0,0 +1,145 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: const_i8_zext
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: const_i8_zext
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: RETURN [[C]](s32), implicit-def $arguments
+ %0:_(s8) = G_CONSTANT i8 255
+ %1:_(s32) = G_ZEXT %0(s8)
+ RETURN %1(s32), implicit-def $arguments
+...
+
+---
+name: const_i8_sext
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: const_i8_sext
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: RETURN [[C]](s32), implicit-def $arguments
+ %0:_(s8) = G_CONSTANT i8 255
+ %1:_(s32) = G_SEXT %0(s8)
+ RETURN %1(s32), implicit-def $arguments
+...
+
+---
+name: const_i8_aext
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: const_i8_aext
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: RETURN [[C]](s32), implicit-def $arguments
+ %0:_(s8) = G_CONSTANT i8 255
+ %1:_(s32) = G_ANYEXT %0(s8)
+ RETURN %1(s32), implicit-def $arguments
+...
+
+
+---
+name: const_i16_zext
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: const_i16_zext
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: RETURN [[C]](s32), implicit-def $arguments
+ %0:_(s16) = G_CONSTANT i16 65535
+ %1:_(s32) = G_ZEXT %0(s16)
+ RETURN %1(s32), implicit-def $arguments
+...
+
+---
+name: const_i16_sext
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: const_i16_sext
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: RETURN [[C]](s32), implicit-def $arguments
+ %0:_(s16) = G_CONSTANT i16 65535
+ %1:_(s32) = G_SEXT %0(s16)
+ RETURN %1(s32), implicit-def $arguments
+...
+
+---
+name: const_i16_aext
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: const_i16_aext
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: RETURN [[C]](s32), implicit-def $arguments
+ %0:_(s16) = G_CONSTANT i16 65535
+ %1:_(s32) = G_ANYEXT %0(s16)
+ RETURN %1(s32), implicit-def $arguments
+...
+
+---
+name: const_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: const_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: RETURN [[C]](s32), implicit-def $arguments
+ %0:_(s32) = G_CONSTANT i32 4294967295
+ RETURN %0(s32), implicit-def $arguments
+...
+
+---
+name: const_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: const_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: RETURN [[C]](s64), implicit-def $arguments
+ %0:_(s64) = G_CONSTANT i64 18446744073709551615
+ RETURN %0(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ctlz.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ctlz.mir
new file mode 100644
index 0000000000000..39e1531194711
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ctlz.mir
@@ -0,0 +1,152 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: ctlz_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
+ ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = nuw G_SUB [[CTLZ]], [[C1]]
+ ; CHECK-NEXT: RETURN [[SUB]](s32), implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %1(s32)
+ %2:_(s8) = G_CTLZ %0
+ %3:_(s32) = G_ANYEXT %2(s8)
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: ctlz_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
+ ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = nuw G_SUB [[CTLZ]], [[C1]]
+ ; CHECK-NEXT: RETURN [[SUB]](s32), implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %1(s32)
+ %2:_(s16) = G_CTLZ %0
+ %3:_(s32) = G_ANYEXT %2(s16)
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: ctlz_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[CTLZ]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_CTLZ %0
+ RETURN %1(s32), implicit-def $arguments
+
+...
+---
+name: ctlz_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[CTLZ]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s8) = G_CTLZ %0
+ %2:_(s32) = G_ANYEXT %1(s8)
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: ctlz_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: RETURN [[CTLZ]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_CTLZ %0
+ RETURN %1(s64), implicit-def $arguments
+
+...
+---
+name: ctlz_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTLZ]](s64)
+ ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s8) = G_CTLZ %0
+ %2:_(s32) = G_ANYEXT %1(s8)
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: ctlz_i64_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_i64_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTLZ]](s64)
+ ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s32) = G_CTLZ %0
+ RETURN %1(s32), implicit-def $arguments
+
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ctlz_zero_undef.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ctlz_zero_undef.mir
new file mode 100644
index 0000000000000..045706eb22c14
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ctlz_zero_undef.mir
@@ -0,0 +1,148 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: ctlz_zundef_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_zundef_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
+ ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[SHL]](s32)
+ ; CHECK-NEXT: RETURN [[CTLZ_ZERO_UNDEF]](s32), implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %1(s32)
+ %2:_(s8) = G_CTLZ_ZERO_UNDEF %0
+ %3:_(s32) = G_ANYEXT %2(s8)
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: ctlz_zundef_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_zundef_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
+ ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[SHL]](s32)
+ ; CHECK-NEXT: RETURN [[CTLZ_ZERO_UNDEF]](s32), implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %1(s32)
+ %2:_(s16) = G_CTLZ_ZERO_UNDEF %0
+ %3:_(s32) = G_ANYEXT %2(s16)
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: ctlz_zundef_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_zundef_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[CTLZ_ZERO_UNDEF]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_CTLZ_ZERO_UNDEF %0
+ RETURN %1(s32), implicit-def $arguments
+
+...
+---
+name: ctlz_zundef_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_zundef_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[CTLZ_ZERO_UNDEF]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s8) = G_CTLZ_ZERO_UNDEF %0
+ %2:_(s32) = G_ANYEXT %1(s8)
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: ctlz_zundef_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_zundef_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s64) = G_CTLZ_ZERO_UNDEF [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: RETURN [[CTLZ_ZERO_UNDEF]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_CTLZ_ZERO_UNDEF %0
+ RETURN %1(s64), implicit-def $arguments
+
+...
+---
+name: ctlz_zundef_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_zundef_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s64) = G_CTLZ_ZERO_UNDEF [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTLZ_ZERO_UNDEF]](s64)
+ ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s8) = G_CTLZ_ZERO_UNDEF %0
+ %2:_(s32) = G_ANYEXT %1(s8)
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: ctlz_zundef_i64_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_zundef_i64_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s64) = G_CTLZ_ZERO_UNDEF [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTLZ_ZERO_UNDEF]](s64)
+ ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s32) = G_CTLZ_ZERO_UNDEF %0
+ RETURN %1(s32), implicit-def $arguments
+
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ctpop.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ctpop.mir
new file mode 100644
index 0000000000000..3dcbd10b40447
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ctpop.mir
@@ -0,0 +1,148 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: ctpop_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctpop_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
+ ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
+ ; CHECK-NEXT: RETURN [[CTPOP]](s32), implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %1(s32)
+ %2:_(s8) = G_CTPOP %0
+ %3:_(s32) = G_ANYEXT %2(s8)
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: ctpop_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctpop_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
+ ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
+ ; CHECK-NEXT: RETURN [[CTPOP]](s32), implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %1(s32)
+ %2:_(s16) = G_CTPOP %0
+ %3:_(s32) = G_ANYEXT %2(s16)
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: ctpop_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctpop_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[CTPOP]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_CTPOP %0
+ RETURN %1(s32), implicit-def $arguments
+
+...
+---
+name: ctpop_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctpop_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[CTPOP]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s8) = G_CTPOP %0
+ %2:_(s32) = G_ANYEXT %1(s8)
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: ctpop_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctpop_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(s64) = G_CTPOP [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: RETURN [[CTPOP]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_CTPOP %0
+ RETURN %1(s64), implicit-def $arguments
+
+...
+---
+name: ctpop_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctpop_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(s64) = G_CTPOP [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTPOP]](s64)
+ ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s8) = G_CTPOP %0
+ %2:_(s32) = G_ANYEXT %1(s8)
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: ctpop_i64_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctpop_i64_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(s64) = G_CTPOP [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTPOP]](s64)
+ ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s32) = G_CTPOP %0
+ RETURN %1(s32), implicit-def $arguments
+
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/cttz.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/cttz.mir
new file mode 100644
index 0000000000000..1d1d90b8420d6
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/cttz.mir
@@ -0,0 +1,148 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: cttz_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: cttz_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ARGUMENT_i32_]], [[C]]
+ ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
+ ; CHECK-NEXT: RETURN [[CTTZ_ZERO_UNDEF]](s32), implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %1(s32)
+ %2:_(s8) = G_CTTZ %0
+ %3:_(s32) = G_ANYEXT %2(s8)
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: cttz_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: cttz_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ARGUMENT_i32_]], [[C]]
+ ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
+ ; CHECK-NEXT: RETURN [[CTTZ_ZERO_UNDEF]](s32), implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %1(s32)
+ %2:_(s16) = G_CTTZ %0
+ %3:_(s32) = G_ANYEXT %2(s16)
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: cttz_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: cttz_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[CTTZ]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_CTTZ %0
+ RETURN %1(s32), implicit-def $arguments
+
+...
+---
+name: cttz_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: cttz_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[CTTZ]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s8) = G_CTTZ %0
+ %2:_(s32) = G_ANYEXT %1(s8)
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: cttz_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: cttz_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s64) = G_CTTZ [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: RETURN [[CTTZ]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_CTTZ %0
+ RETURN %1(s64), implicit-def $arguments
+
+...
+---
+name: cttz_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: cttz_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s64) = G_CTTZ [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTTZ]](s64)
+ ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s8) = G_CTTZ %0
+ %2:_(s32) = G_ANYEXT %1(s8)
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: cttz_i64_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: cttz_i64_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s64) = G_CTTZ [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTTZ]](s64)
+ ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s32) = G_CTTZ %0
+ RETURN %1(s32), implicit-def $arguments
+
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/cttz_zero_undef.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/cttz_zero_undef.mir
new file mode 100644
index 0000000000000..adb0cab5879d0
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/cttz_zero_undef.mir
@@ -0,0 +1,144 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: cttz_zundef_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: cttz_zundef_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[CTTZ_ZERO_UNDEF]](s32), implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %1(s32)
+ %2:_(s8) = G_CTTZ_ZERO_UNDEF %0
+ %3:_(s32) = G_ANYEXT %2(s8)
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: cttz_zundef_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: cttz_zundef_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[CTTZ_ZERO_UNDEF]](s32), implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %1(s32)
+ %2:_(s16) = G_CTTZ_ZERO_UNDEF %0
+ %3:_(s32) = G_ANYEXT %2(s16)
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: cttz_zundef_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: cttz_zundef_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[CTTZ_ZERO_UNDEF]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_CTTZ_ZERO_UNDEF %0
+ RETURN %1(s32), implicit-def $arguments
+
+...
+---
+name: cttz_zundef_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: cttz_zundef_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[CTTZ_ZERO_UNDEF]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s8) = G_CTTZ_ZERO_UNDEF %0
+ %2:_(s32) = G_ANYEXT %1(s8)
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: cttz_zundef_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: cttz_zundef_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s64) = G_CTTZ_ZERO_UNDEF [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: RETURN [[CTTZ_ZERO_UNDEF]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_CTTZ_ZERO_UNDEF %0
+ RETURN %1(s64), implicit-def $arguments
+
+...
+---
+name: cttz_zundef_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: cttz_zundef_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s64) = G_CTTZ_ZERO_UNDEF [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTTZ_ZERO_UNDEF]](s64)
+ ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s8) = G_CTTZ_ZERO_UNDEF %0
+ %2:_(s32) = G_ANYEXT %1(s8)
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: cttz_zundef_i64_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: cttz_zundef_i64_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s64) = G_CTTZ_ZERO_UNDEF [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTTZ_ZERO_UNDEF]](s64)
+ ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s32) = G_CTTZ_ZERO_UNDEF %0
+ RETURN %1(s32), implicit-def $arguments
+
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/fshl.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/fshl.mir
new file mode 100644
index 0000000000000..3aa32c39ee15f
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/fshl.mir
@@ -0,0 +1,393 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: fshl_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshl_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C2]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C1]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_CONSTANT i8 5
+ %5:_(s8) = G_FSHL %0, %1, %4(s8)
+ %6:_(s32) = G_ANYEXT %5(s8)
+ RETURN %6(s32), implicit-def $arguments
+
+...
+---
+name: fshlv_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshlv_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_2]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_2]], [[C1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[AND]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C3]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C2]](s32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
+ ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND1]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR1]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %3:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %3(s32)
+ %4:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %4(s32)
+ %5:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ %2:_(s8) = G_TRUNC %5(s32)
+ %6:_(s8) = G_FSHL %0, %1, %2(s8)
+ %7:_(s32) = G_ANYEXT %6(s8)
+ RETURN %7(s32), implicit-def $arguments
+
+...
+---
+name: fshl_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshl_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C2]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C1]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_CONSTANT i16 13
+ %5:_(s16) = G_FSHL %0, %1, %4(s16)
+ %6:_(s32) = G_ANYEXT %5(s16)
+ RETURN %6(s32), implicit-def $arguments
+
+...
+---
+name: fshlv_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshlv_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_2]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_2]], [[C1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[AND]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C3]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C2]](s32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
+ ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND1]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR1]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %3:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %3(s32)
+ %4:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %4(s32)
+ %5:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ %2:_(s16) = G_TRUNC %5(s32)
+ %6:_(s16) = G_FSHL %0, %1, %2(s16)
+ %7:_(s32) = G_ANYEXT %6(s16)
+ RETURN %7(s32), implicit-def $arguments
+
+...
+---
+name: fshl_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshl_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ARGUMENT_i32_1]], [[C1]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_CONSTANT i32 21
+ %3:_(s32) = G_FSHL %0, %1, %2(s32)
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: fshlv_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshlv_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_2]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_2]], [[C1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[AND]](s32)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ARGUMENT_i32_1]], [[C2]](s32)
+ ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[AND1]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR1]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ %3:_(s32) = G_FSHL %0, %1, %2(s32)
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: fshl_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshl_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ARGUMENT_i32_1]], [[C1]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s8) = G_CONSTANT i8 21
+ %3:_(s32) = G_FSHL %0, %1, %2(s8)
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: fshlv_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshlv_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_2]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_2]], [[C1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[AND]](s32)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ARGUMENT_i32_1]], [[C2]](s32)
+ ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[AND1]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR1]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %3:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ %2:_(s8) = G_TRUNC %3(s32)
+ %4:_(s32) = G_FSHL %0, %1, %2(s8)
+ RETURN %4(s32), implicit-def $arguments
+
+...
+---
+name: fshl_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshl_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 27
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ARGUMENT_i64_]], [[C]](s64)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ARGUMENT_i64_1]], [[C1]](s64)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL]], [[LSHR]]
+ ; CHECK-NEXT: RETURN [[OR]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_CONSTANT i64 37
+ %3:_(s64) = G_FSHL %0, %1, %2(s64)
+ RETURN %3(s64), implicit-def $arguments
+
+...
+---
+name: fshlv_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshlv_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_2:%[0-9]+]]:i64(s64) = ARGUMENT_i64 2, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ARGUMENT_i64_2]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ARGUMENT_i64_2]], [[C1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ARGUMENT_i64_]], [[AND]](s64)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ARGUMENT_i64_1]], [[C2]](s64)
+ ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[LSHR]], [[AND1]](s64)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL]], [[LSHR1]]
+ ; CHECK-NEXT: RETURN [[OR]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:i64(s64) = ARGUMENT_i64 2, implicit $arguments
+ %3:_(s64) = G_FSHL %0, %1, %2(s64)
+ RETURN %3(s64), implicit-def $arguments
+
+...
+---
+name: fshl_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshl_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 21
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[C]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ARGUMENT_i64_]], [[AND]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 43
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[C2]], [[C3]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ARGUMENT_i64_1]], [[AND1]](s64)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL]], [[LSHR]]
+ ; CHECK-NEXT: RETURN [[OR]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s8) = G_CONSTANT i8 21
+ %3:_(s64) = G_FSHL %0, %1, %2(s8)
+ RETURN %3(s64), implicit-def $arguments
+
+...
+---
+name: fshlv_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshlv_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_]], [[C1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C2]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ARGUMENT_i64_]], [[AND2]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[C3]], [[C4]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ARGUMENT_i64_1]], [[AND3]](s64)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[AND1]](s32)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ANYEXT1]], [[C5]]
+ ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[LSHR]], [[AND4]](s64)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL]], [[LSHR1]]
+ ; CHECK-NEXT: RETURN [[OR]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %3:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ %2:_(s8) = G_TRUNC %3(s32)
+ %4:_(s64) = G_FSHL %0, %1, %2(s8)
+ RETURN %4(s64), implicit-def $arguments
+
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/fshr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/fshr.mir
new file mode 100644
index 0000000000000..0437c51d310c9
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/fshr.mir
@@ -0,0 +1,389 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: fshr_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshr_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C1]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C2]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_CONSTANT i8 5
+ %5:_(s8) = G_FSHR %0, %1, %4(s8)
+ %6:_(s32) = G_ANYEXT %5(s8)
+ RETURN %6(s32), implicit-def $arguments
+
+...
+---
+name: fshrv_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshrv_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_2]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_2]], [[C1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C2]](s32)
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C3]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL1]], [[LSHR]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %3:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %3(s32)
+ %4:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %4(s32)
+ %5:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ %2:_(s8) = G_TRUNC %5(s32)
+ %6:_(s8) = G_FSHR %0, %1, %2(s8)
+ %7:_(s32) = G_ANYEXT %6(s8)
+ RETURN %7(s32), implicit-def $arguments
+
+...
+---
+name: fshr_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshr_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C1]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C2]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_CONSTANT i16 13
+ %5:_(s16) = G_FSHR %0, %1, %4(s16)
+ %6:_(s32) = G_ANYEXT %5(s16)
+ RETURN %6(s32), implicit-def $arguments
+
+...
+---
+name: fshrv_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshrv_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_2]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_2]], [[C1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C2]](s32)
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C3]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL1]], [[LSHR]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %3:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %3(s32)
+ %4:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %4(s32)
+ %5:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ %2:_(s16) = G_TRUNC %5(s32)
+ %6:_(s16) = G_FSHR %0, %1, %2(s16)
+ %7:_(s32) = G_ANYEXT %6(s16)
+ RETURN %7(s32), implicit-def $arguments
+
+...
+---
+name: fshr_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshr_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C1]](s32)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ARGUMENT_i32_1]], [[C]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_CONSTANT i32 21
+ %3:_(s32) = G_FSHR %0, %1, %2(s32)
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: fshrv_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshrv_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_2]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_2]], [[C1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C2]](s32)
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ARGUMENT_i32_1]], [[AND]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL1]], [[LSHR]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ %3:_(s32) = G_FSHR %0, %1, %2(s32)
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: fshr_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshr_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C1]](s32)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ARGUMENT_i32_1]], [[C]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s8) = G_CONSTANT i8 21
+ %3:_(s32) = G_FSHR %0, %1, %2(s8)
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: fshrv_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshrv_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_2]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_2]], [[C1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C2]](s32)
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ARGUMENT_i32_1]], [[AND]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL1]], [[LSHR]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %3:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ %2:_(s8) = G_TRUNC %3(s32)
+ %4:_(s32) = G_FSHR %0, %1, %2(s8)
+ RETURN %4(s32), implicit-def $arguments
+
+...
+---
+name: fshr_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshr_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 27
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ARGUMENT_i64_]], [[C1]](s64)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ARGUMENT_i64_1]], [[C]](s64)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL]], [[LSHR]]
+ ; CHECK-NEXT: RETURN [[OR]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_CONSTANT i64 37
+ %3:_(s64) = G_FSHR %0, %1, %2(s64)
+ RETURN %3(s64), implicit-def $arguments
+
+...
+---
+name: fshrv_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshrv_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_2:%[0-9]+]]:i64(s64) = ARGUMENT_i64 2, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ARGUMENT_i64_2]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ARGUMENT_i64_2]], [[C1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ARGUMENT_i64_]], [[C2]](s64)
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SHL]], [[AND1]](s64)
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ARGUMENT_i64_1]], [[AND]](s64)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL1]], [[LSHR]]
+ ; CHECK-NEXT: RETURN [[OR]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:i64(s64) = ARGUMENT_i64 2, implicit $arguments
+ %3:_(s64) = G_FSHR %0, %1, %2(s64)
+ RETURN %3(s64), implicit-def $arguments
+
+...
+---
+name: fshr_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshr_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 43
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[C]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ARGUMENT_i64_]], [[AND]](s64)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 21
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[C2]], [[C3]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ARGUMENT_i64_1]], [[AND1]](s64)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL]], [[LSHR]]
+ ; CHECK-NEXT: RETURN [[OR]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s8) = G_CONSTANT i8 21
+ %3:_(s64) = G_FSHR %0, %1, %2(s8)
+ RETURN %3(s64), implicit-def $arguments
+
+...
+---
+name: fshrv_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshrv_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_]], [[C1]]
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[C2]], [[C3]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ARGUMENT_i64_]], [[AND2]](s64)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND1]](s32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C4]]
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SHL]], [[AND3]](s64)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[AND]](s32)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ANYEXT1]], [[C5]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ARGUMENT_i64_1]], [[AND4]](s64)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL1]], [[LSHR]]
+ ; CHECK-NEXT: RETURN [[OR]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %3:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ %2:_(s8) = G_TRUNC %3(s32)
+ %4:_(s64) = G_FSHR %0, %1, %2(s8)
+ RETURN %4(s64), implicit-def $arguments
+
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/implicit_def.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/implicit_def.mir
new file mode 100644
index 0000000000000..4b6685214a963
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/implicit_def.mir
@@ -0,0 +1,72 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: implicit_def_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: implicit_def_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: RETURN [[DEF]](s32), implicit-def $arguments
+ %0:_(s8) = G_IMPLICIT_DEF
+ %1:_(s32) = G_ANYEXT %0(s8)
+ RETURN %1(s32), implicit-def $arguments
+...
+
+---
+name: implicit_def_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: implicit_def_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: RETURN [[DEF]](s32), implicit-def $arguments
+ %0:_(s16) = G_IMPLICIT_DEF
+ %1:_(s32) = G_ANYEXT %0(s16)
+ RETURN %1(s32), implicit-def $arguments
+...
+
+---
+name: implicit_def_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: implicit_def_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: RETURN [[DEF]](s32), implicit-def $arguments
+ %0:_(s32) = G_IMPLICIT_DEF
+ RETURN %0(s32), implicit-def $arguments
+...
+
+---
+name: implicit_def_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: implicit_def_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: RETURN [[DEF]](s64), implicit-def $arguments
+ %0:_(s64) = G_IMPLICIT_DEF
+ RETURN %0(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/lshr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/lshr.mir
new file mode 100644
index 0000000000000..f8150c9cfd7a4
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/lshr.mir
@@ -0,0 +1,286 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: lshr_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshr_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C1]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)
+ ; CHECK-NEXT: RETURN [[LSHR]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %1:_(s8) = G_CONSTANT i8 5
+ %3:_(s8) = G_LSHR %0, %1
+ %4:_(s32) = G_ANYEXT %3(s8)
+ RETURN %4(s32), implicit-def $arguments
+
+...
+---
+name: lshrv_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshrv_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C1]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[AND1]](s32)
+ ; CHECK-NEXT: RETURN [[LSHR]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_LSHR %0, %1
+ %5:_(s32) = G_ANYEXT %4(s8)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: lshr_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshr_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C1]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)
+ ; CHECK-NEXT: RETURN [[LSHR]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %1:_(s16) = G_CONSTANT i16 13
+ %3:_(s16) = G_LSHR %0, %1
+ %4:_(s32) = G_ANYEXT %3(s16)
+ RETURN %4(s32), implicit-def $arguments
+
+...
+---
+name: lshrv_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshrv_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C1]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[AND1]](s32)
+ ; CHECK-NEXT: RETURN [[LSHR]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_LSHR %0, %1
+ %5:_(s32) = G_ANYEXT %4(s16)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: lshr_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshr_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ARGUMENT_i32_]], [[C]](s32)
+ ; CHECK-NEXT: RETURN [[LSHR]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_CONSTANT i32 21
+ %2:_(s32) = G_LSHR %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: lshrv_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshrv_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]](s32)
+ ; CHECK-NEXT: RETURN [[LSHR]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_LSHR %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: lshr_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshr_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ARGUMENT_i32_]], [[C]](s32)
+ ; CHECK-NEXT: RETURN [[LSHR]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s8) = G_CONSTANT i8 21
+ %2:_(s32) = G_LSHR %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: lshrv_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshrv_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ARGUMENT_i32_]], [[AND]](s32)
+ ; CHECK-NEXT: RETURN [[LSHR]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %2(s32)
+ %3:_(s32) = G_LSHR %0, %1
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: lshr_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshr_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ARGUMENT_i64_]], [[C]](s64)
+ ; CHECK-NEXT: RETURN [[LSHR]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_CONSTANT i64 37
+ %2:_(s64) = G_LSHR %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: lshrv_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshrv_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]](s64)
+ ; CHECK-NEXT: RETURN [[LSHR]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_LSHR %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: lshr_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshr_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[C]], [[C1]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ARGUMENT_i64_]], [[AND]](s64)
+ ; CHECK-NEXT: RETURN [[LSHR]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s8) = G_CONSTANT i8 37
+ %2:_(s64) = G_LSHR %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: lshrv_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshrv_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ARGUMENT_i64_]], [[AND]](s64)
+ ; CHECK-NEXT: RETURN [[LSHR]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %2(s32)
+ %3:_(s64) = G_LSHR %0, %1
+ RETURN %3(s64), implicit-def $arguments
+
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/mul.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/mul.mir
new file mode 100644
index 0000000000000..537d8f9fcf52d
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/mul.mir
@@ -0,0 +1,91 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: mul_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: mul_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[MUL]](s32)
+ ; CHECK-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_MUL %0, %1
+ %5:i32(s32) = G_ANYEXT %4(s8)
+ RETURN %5(s32), implicit-def $arguments
+...
+---
+name: mul_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: mul_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[MUL]](s32)
+ ; CHECK-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_MUL %0, %1
+ %5:i32(s32) = G_ANYEXT %4(s16)
+ RETURN %5(s32), implicit-def $arguments
+...
+---
+name: mul_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: mul_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
+ ; CHECK-NEXT: RETURN [[MUL]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_MUL %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: mul_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: mul_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
+ ; CHECK-NEXT: RETURN [[MUL]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_MUL %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/or.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/or.mir
new file mode 100644
index 0000000000000..d86bd04d2e455
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/or.mir
@@ -0,0 +1,117 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: or_i1
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: or_i1
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s1) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s1) = G_TRUNC %3(s32)
+ %4:_(s1) = G_OR %1, %0
+ %5:_(s32) = G_ANYEXT %4(s1)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: or_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: or_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_OR %1, %0
+ %5:_(s32) = G_ANYEXT %4(s8)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: or_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: or_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_OR %1, %0
+ %5:_(s32) = G_ANYEXT %4(s16)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: or_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: or_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_OR %1, %0
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: or_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: or_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ARGUMENT_i64_1]], [[ARGUMENT_i64_]]
+ ; CHECK-NEXT: RETURN [[OR]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_OR %1, %0
+ RETURN %2(s64), implicit-def $arguments
+
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/rotl.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/rotl.mir
new file mode 100644
index 0000000000000..82c1bcf76ae5b
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/rotl.mir
@@ -0,0 +1,303 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+
+---
+name: rotl_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotl_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C2]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C1]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %1:_(s8) = G_CONSTANT i8 5
+ %3:_(s8) = G_ROTL %0, %1
+ %4:_(s32) = G_ANYEXT %3(s8)
+ RETURN %4(s32), implicit-def $arguments
+
+...
+---
+name: rotlv_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotlv_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[ARGUMENT_i32_1]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[AND]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C2]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND1]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_ROTL %0, %1
+ %5:_(s32) = G_ANYEXT %4(s8)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: rotl_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotl_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C2]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C1]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %1:_(s16) = G_CONSTANT i16 13
+ %3:_(s16) = G_ROTL %0, %1
+ %4:_(s32) = G_ANYEXT %3(s16)
+ RETURN %4(s32), implicit-def $arguments
+
+...
+---
+name: rotlv_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotlv_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[ARGUMENT_i32_1]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[AND]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C2]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND1]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_ROTL %0, %1
+ %5:_(s32) = G_ANYEXT %4(s16)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: rotl_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotl_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
+ ; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[ARGUMENT_i32_]], [[C]](s32)
+ ; CHECK-NEXT: RETURN [[ROTL]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_CONSTANT i32 21
+ %2:_(s32) = G_ROTL %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: rotlv_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotlv_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]](s32)
+ ; CHECK-NEXT: RETURN [[ROTL]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_ROTL %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: rotl_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotl_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
+ ; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[ARGUMENT_i32_]], [[C]](s32)
+ ; CHECK-NEXT: RETURN [[ROTL]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s8) = G_CONSTANT i8 21
+ %2:_(s32) = G_ROTL %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: rotlv_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotlv_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C]]
+ ; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[ARGUMENT_i32_]], [[AND]](s32)
+ ; CHECK-NEXT: RETURN [[ROTL]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %2(s32)
+ %3:_(s32) = G_ROTL %0, %1
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: rotl_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotl_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
+ ; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(s64) = G_ROTL [[ARGUMENT_i64_]], [[C]](s64)
+ ; CHECK-NEXT: RETURN [[ROTL]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_CONSTANT i64 37
+ %2:_(s64) = G_ROTL %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: rotlv_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotlv_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(s64) = G_ROTL [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]](s64)
+ ; CHECK-NEXT: RETURN [[ROTL]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_ROTL %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: rotl_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotl_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[C]], [[C1]]
+ ; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(s64) = G_ROTL [[ARGUMENT_i64_]], [[AND]](s64)
+ ; CHECK-NEXT: RETURN [[ROTL]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s8) = G_CONSTANT i8 37
+ %2:_(s64) = G_ROTL %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: rotlv_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotlv_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(s64) = G_ROTL [[ARGUMENT_i64_]], [[AND]](s64)
+ ; CHECK-NEXT: RETURN [[ROTL]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %2(s32)
+ %3:_(s64) = G_ROTL %0, %1
+ RETURN %3(s64), implicit-def $arguments
+
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/rotr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/rotr.mir
new file mode 100644
index 0000000000000..e8fc7e5db324e
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/rotr.mir
@@ -0,0 +1,303 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+
+---
+name: rotr_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotr_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C1]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C2]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[LSHR]], [[SHL]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %1:_(s8) = G_CONSTANT i8 5
+ %3:_(s8) = G_ROTR %0, %1
+ %4:_(s32) = G_ANYEXT %3(s8)
+ RETURN %4(s32), implicit-def $arguments
+
+...
+---
+name: rotrv_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotrv_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[ARGUMENT_i32_1]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C2]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[AND2]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[LSHR]], [[SHL]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_ROTR %0, %1
+ %5:_(s32) = G_ANYEXT %4(s8)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: rotr_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotr_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C1]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C2]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[LSHR]], [[SHL]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %1:_(s16) = G_CONSTANT i16 13
+ %3:_(s16) = G_ROTR %0, %1
+ %4:_(s32) = G_ANYEXT %3(s16)
+ RETURN %4(s32), implicit-def $arguments
+
+...
+---
+name: rotrv_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotrv_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[ARGUMENT_i32_1]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C2]]
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[AND2]](s32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[LSHR]], [[SHL]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_ROTR %0, %1
+ %5:_(s32) = G_ANYEXT %4(s16)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: rotr_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotr_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
+ ; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[ARGUMENT_i32_]], [[C]](s32)
+ ; CHECK-NEXT: RETURN [[ROTR]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_CONSTANT i32 21
+ %2:_(s32) = G_ROTR %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: rotrv_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotrv_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]](s32)
+ ; CHECK-NEXT: RETURN [[ROTR]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_ROTR %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: rotr_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotr_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
+ ; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[ARGUMENT_i32_]], [[C]](s32)
+ ; CHECK-NEXT: RETURN [[ROTR]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s8) = G_CONSTANT i8 21
+ %2:_(s32) = G_ROTR %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: rotrv_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotrv_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C]]
+ ; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[ARGUMENT_i32_]], [[AND]](s32)
+ ; CHECK-NEXT: RETURN [[ROTR]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %2(s32)
+ %3:_(s32) = G_ROTR %0, %1
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: rotr_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotr_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
+ ; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(s64) = G_ROTR [[ARGUMENT_i64_]], [[C]](s64)
+ ; CHECK-NEXT: RETURN [[ROTR]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_CONSTANT i64 37
+ %2:_(s64) = G_ROTR %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: rotrv_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotrv_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(s64) = G_ROTR [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]](s64)
+ ; CHECK-NEXT: RETURN [[ROTR]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_ROTR %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: rotr_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotr_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[C]], [[C1]]
+ ; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(s64) = G_ROTR [[ARGUMENT_i64_]], [[AND]](s64)
+ ; CHECK-NEXT: RETURN [[ROTR]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s8) = G_CONSTANT i8 37
+ %2:_(s64) = G_ROTR %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: rotrv_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotrv_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(s64) = G_ROTR [[ARGUMENT_i64_]], [[AND]](s64)
+ ; CHECK-NEXT: RETURN [[ROTR]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %2(s32)
+ %3:_(s64) = G_ROTR %0, %1
+ RETURN %3(s64), implicit-def $arguments
+
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sdiv.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sdiv.mir
new file mode 100644
index 0000000000000..e7d3581e1c1b7
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sdiv.mir
@@ -0,0 +1,126 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=-sign-ext -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NO-SIGNEXT
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=+sign-ext -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,SIGNEXT
+
+---
+name: sdiv_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: sdiv_i8
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
+ ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; NO-SIGNEXT-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; NO-SIGNEXT-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_1]], [[C1]](s32)
+ ; NO-SIGNEXT-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
+ ; NO-SIGNEXT-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
+ ; NO-SIGNEXT-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[SDIV]](s32)
+ ; NO-SIGNEXT-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: sdiv_i8
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ARGUMENT_i32_]], 8
+ ; SIGNEXT-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ARGUMENT_i32_1]], 8
+ ; SIGNEXT-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
+ ; SIGNEXT-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[SDIV]](s32)
+ ; SIGNEXT-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_SDIV %0, %1
+ %5:i32(s32) = G_ANYEXT %4(s8)
+ RETURN %5(s32), implicit-def $arguments
+...
+---
+name: sdiv_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: sdiv_i16
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
+ ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; NO-SIGNEXT-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; NO-SIGNEXT-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_1]], [[C1]](s32)
+ ; NO-SIGNEXT-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
+ ; NO-SIGNEXT-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
+ ; NO-SIGNEXT-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[SDIV]](s32)
+ ; NO-SIGNEXT-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: sdiv_i16
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ARGUMENT_i32_]], 16
+ ; SIGNEXT-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ARGUMENT_i32_1]], 16
+ ; SIGNEXT-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
+ ; SIGNEXT-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[SDIV]](s32)
+ ; SIGNEXT-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_SDIV %0, %1
+ %5:i32(s32) = G_ANYEXT %4(s16)
+ RETURN %5(s32), implicit-def $arguments
+...
+---
+name: sdiv_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sdiv_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
+ ; CHECK-NEXT: RETURN [[SDIV]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_SDIV %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: sdiv_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sdiv_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
+ ; CHECK-NEXT: RETURN [[SDIV]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_SDIV %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sext.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sext.mir
new file mode 100644
index 0000000000000..6b443b1f91e82
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sext.mir
@@ -0,0 +1,138 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=-sign-ext -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NO-SIGNEXT
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=+sign-ext -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,SIGNEXT
+
+---
+name: sext_i8_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: sext_i8_i32
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
+ ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:i32(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; NO-SIGNEXT-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: sext_i8_i32
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:i32(s32) = G_SEXT_INREG [[ARGUMENT_i32_]], 8
+ ; SIGNEXT-NEXT: RETURN [[SEXT_INREG]](s32), implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %1(s32)
+ %2:i32(s32) = G_SEXT %0(s8)
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: sext_i8_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: sext_i8_i64
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
+ ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
+ ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C]](s64)
+ ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:i32(s64) = G_ASHR [[SHL]], [[C]](s64)
+ ; NO-SIGNEXT-NEXT: RETURN [[ASHR]](s64), implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: sext_i8_i64
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
+ ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:i32(s64) = G_SEXT_INREG [[ANYEXT]], 8
+ ; SIGNEXT-NEXT: RETURN [[SEXT_INREG]](s64), implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %1(s32)
+ %2:i32(s64) = G_SEXT %0(s8)
+ RETURN %2(s64), implicit-def $arguments
+...
+---
+name: sext_i16_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: sext_i16_i32
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
+ ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:i32(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; NO-SIGNEXT-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: sext_i16_i32
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:i32(s32) = G_SEXT_INREG [[ARGUMENT_i32_]], 16
+ ; SIGNEXT-NEXT: RETURN [[SEXT_INREG]](s32), implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %1(s32)
+ %2:i32(s32) = G_SEXT %0(s16)
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: sext_i16_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: sext_i16_i64
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
+ ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
+ ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C]](s64)
+ ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:i32(s64) = G_ASHR [[SHL]], [[C]](s64)
+ ; NO-SIGNEXT-NEXT: RETURN [[ASHR]](s64), implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: sext_i16_i64
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
+ ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:i32(s64) = G_SEXT_INREG [[ANYEXT]], 16
+ ; SIGNEXT-NEXT: RETURN [[SEXT_INREG]](s64), implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %1(s32)
+ %2:i32(s64) = G_SEXT %0(s16)
+ RETURN %2(s64), implicit-def $arguments
+...
+---
+name: sext_i32_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sext_i32_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:i32(s64) = G_SEXT [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[SEXT]](s64), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s64) = G_SEXT %0(s32)
+ RETURN %1(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sext_inreg.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sext_inreg.mir
new file mode 100644
index 0000000000000..2d5daf7b906f3
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sext_inreg.mir
@@ -0,0 +1,181 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=-sign-ext -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NO-SIGNEXT
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=+sign-ext -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,SIGNEXT
+
+---
+name: sext_inreg_i1_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sext_inreg_i1_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %1, [[C]](s32)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; CHECK-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_SEXT_INREG %1(s32), 1
+ RETURN %1(s32), implicit-def $arguments
+...
+---
+name: sext_inreg_i8_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: sext_inreg_i8_i32
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %1, [[C]](s32)
+ ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; NO-SIGNEXT-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: sext_inreg_i8_i32
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SEXT_INREG]], 8
+ ; SIGNEXT-NEXT: RETURN [[SEXT_INREG]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_SEXT_INREG %1(s32), 8
+ RETURN %1(s32), implicit-def $arguments
+...
+---
+name: sext_inreg_i16_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: sext_inreg_i16_i32
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %1, [[C]](s32)
+ ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; NO-SIGNEXT-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: sext_inreg_i16_i32
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SEXT_INREG]], 16
+ ; SIGNEXT-NEXT: RETURN [[SEXT_INREG]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_SEXT_INREG %1(s32), 16
+ RETURN %1(s32), implicit-def $arguments
+...
+
+---
+name: sext_inreg_i1_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sext_inreg_i1_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL %1, [[C]](s64)
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
+ ; CHECK-NEXT: RETURN [[ASHR]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_SEXT_INREG %1(s64), 1
+ RETURN %1(s64), implicit-def $arguments
+...
+---
+name: sext_inreg_i8_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: sext_inreg_i8_i64
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
+ ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL %1, [[C]](s64)
+ ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
+ ; NO-SIGNEXT-NEXT: RETURN [[ASHR]](s64), implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: sext_inreg_i8_i64
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SEXT_INREG]], 8
+ ; SIGNEXT-NEXT: RETURN [[SEXT_INREG]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_SEXT_INREG %1(s64), 8
+ RETURN %1(s64), implicit-def $arguments
+...
+---
+name: sext_inreg_i16_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: sext_inreg_i16_i64
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
+ ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL %1, [[C]](s64)
+ ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
+ ; NO-SIGNEXT-NEXT: RETURN [[ASHR]](s64), implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: sext_inreg_i16_i64
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SEXT_INREG]], 16
+ ; SIGNEXT-NEXT: RETURN [[SEXT_INREG]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_SEXT_INREG %1(s64), 16
+ RETURN %1(s64), implicit-def $arguments
+...
+
+---
+name: sext_inreg_i32_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: sext_inreg_i32_i64
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
+ ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL %1, [[C]](s64)
+ ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
+ ; NO-SIGNEXT-NEXT: RETURN [[ASHR]](s64), implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: sext_inreg_i32_i64
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SEXT_INREG]], 32
+ ; SIGNEXT-NEXT: RETURN [[SEXT_INREG]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_SEXT_INREG %1(s64), 32
+ RETURN %1(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/shl.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/shl.mir
new file mode 100644
index 0000000000000..25c75c551a1e7
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/shl.mir
@@ -0,0 +1,278 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: shl_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shl_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
+ ; CHECK-NEXT: RETURN [[SHL]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %1:_(s8) = G_CONSTANT i8 5
+ %3:_(s8) = G_SHL %0, %1
+ %4:_(s32) = G_ANYEXT %3(s8)
+ RETURN %4(s32), implicit-def $arguments
+
+...
+---
+name: shlv_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shlv_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[AND]](s32)
+ ; CHECK-NEXT: RETURN [[SHL]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_SHL %0, %1
+ %5:_(s32) = G_ANYEXT %4(s8)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: shl_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shl_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
+ ; CHECK-NEXT: RETURN [[SHL]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %1:_(s16) = G_CONSTANT i16 13
+ %3:_(s16) = G_SHL %0, %1
+ %4:_(s32) = G_ANYEXT %3(s16)
+ RETURN %4(s32), implicit-def $arguments
+
+...
+---
+name: shlv_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shlv_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[AND]](s32)
+ ; CHECK-NEXT: RETURN [[SHL]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_SHL %0, %1
+ %5:_(s32) = G_ANYEXT %4(s16)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: shl_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shl_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
+ ; CHECK-NEXT: RETURN [[SHL]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_CONSTANT i32 21
+ %2:_(s32) = G_SHL %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: shlv_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shlv_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]](s32)
+ ; CHECK-NEXT: RETURN [[SHL]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_SHL %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: shl_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shl_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
+ ; CHECK-NEXT: RETURN [[SHL]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s8) = G_CONSTANT i8 21
+ %2:_(s32) = G_SHL %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: shlv_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shlv_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[AND]](s32)
+ ; CHECK-NEXT: RETURN [[SHL]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %2(s32)
+ %3:_(s32) = G_SHL %0, %1
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: shl_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shl_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ARGUMENT_i64_]], [[C]](s64)
+ ; CHECK-NEXT: RETURN [[SHL]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_CONSTANT i64 37
+ %2:_(s64) = G_SHL %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: shlv_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shlv_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]](s64)
+ ; CHECK-NEXT: RETURN [[SHL]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_SHL %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: shl_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shl_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[C]], [[C1]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ARGUMENT_i64_]], [[AND]](s64)
+ ; CHECK-NEXT: RETURN [[SHL]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s8) = G_CONSTANT i8 37
+ %2:_(s64) = G_SHL %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: shlv_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shlv_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ARGUMENT_i64_]], [[AND]](s64)
+ ; CHECK-NEXT: RETURN [[SHL]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %2(s32)
+ %3:_(s64) = G_SHL %0, %1
+ RETURN %3(s64), implicit-def $arguments
+
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/srem.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/srem.mir
new file mode 100644
index 0000000000000..e6d9d2c5bad2d
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/srem.mir
@@ -0,0 +1,126 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=-sign-ext -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NO-SIGNEXT
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=+sign-ext -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,SIGNEXT
+
+---
+name: srem_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: srem_i8
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
+ ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; NO-SIGNEXT-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; NO-SIGNEXT-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_1]], [[C1]](s32)
+ ; NO-SIGNEXT-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
+ ; NO-SIGNEXT-NEXT: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
+ ; NO-SIGNEXT-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[SREM]](s32)
+ ; NO-SIGNEXT-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: srem_i8
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ARGUMENT_i32_]], 8
+ ; SIGNEXT-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ARGUMENT_i32_1]], 8
+ ; SIGNEXT-NEXT: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[SEXT_INREG]], [[SEXT_INREG1]]
+ ; SIGNEXT-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[SREM]](s32)
+ ; SIGNEXT-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_SREM %0, %1
+ %5:i32(s32) = G_ANYEXT %4(s8)
+ RETURN %5(s32), implicit-def $arguments
+...
+---
+name: srem_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: srem_i16
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
+ ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; NO-SIGNEXT-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; NO-SIGNEXT-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_1]], [[C1]](s32)
+ ; NO-SIGNEXT-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
+ ; NO-SIGNEXT-NEXT: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
+ ; NO-SIGNEXT-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[SREM]](s32)
+ ; NO-SIGNEXT-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: srem_i16
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ARGUMENT_i32_]], 16
+ ; SIGNEXT-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ARGUMENT_i32_1]], 16
+ ; SIGNEXT-NEXT: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[SEXT_INREG]], [[SEXT_INREG1]]
+ ; SIGNEXT-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[SREM]](s32)
+ ; SIGNEXT-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_SREM %0, %1
+ %5:i32(s32) = G_ANYEXT %4(s16)
+ RETURN %5(s32), implicit-def $arguments
+...
+---
+name: srem_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: srem_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
+ ; CHECK-NEXT: RETURN [[SREM]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_SREM %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: srem_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: srem_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[SREM:%[0-9]+]]:_(s64) = G_SREM [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
+ ; CHECK-NEXT: RETURN [[SREM]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_SREM %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sub.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sub.mir
new file mode 100644
index 0000000000000..97770cb6280cb
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sub.mir
@@ -0,0 +1,91 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: sub_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sub_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[SUB]](s32)
+ ; CHECK-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_SUB %0, %1
+ %5:i32(s32) = G_ANYEXT %4(s8)
+ RETURN %5(s32), implicit-def $arguments
+...
+---
+name: sub_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sub_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[SUB]](s32)
+ ; CHECK-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_SUB %0, %1
+ %5:i32(s32) = G_ANYEXT %4(s16)
+ RETURN %5(s32), implicit-def $arguments
+...
+---
+name: sub_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sub_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
+ ; CHECK-NEXT: RETURN [[SUB]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_SUB %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: sub_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sub_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
+ ; CHECK-NEXT: RETURN [[SUB]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_SUB %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/trunc.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/trunc.mir
new file mode 100644
index 0000000000000..c9dfd3175e6d6
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/trunc.mir
@@ -0,0 +1,95 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: trunc_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: trunc_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: RETURN [[ARGUMENT_i32_]](s32), implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %1(s32)
+ %2:i32(s32) = G_ANYEXT %0(s8)
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: trunc_i32_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: trunc_i32_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: RETURN [[ARGUMENT_i32_]](s32), implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %1(s32)
+ %2:i32(s32) = G_ANYEXT %0(s16)
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: trunc_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: trunc_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:i32(s32) = G_TRUNC [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
+ %1:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %1(s64)
+ %2:i32(s32) = G_ANYEXT %0(s8)
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: trunc_i64_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: trunc_i64_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:i32(s32) = G_TRUNC [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
+ %1:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %1(s64)
+ %2:i32(s32) = G_ANYEXT %0(s16)
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: trunc_i64_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: trunc_i64_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
+ %1:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %0:_(s32) = G_TRUNC %1(s64)
+ RETURN %0(s32), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/udiv.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/udiv.mir
new file mode 100644
index 0000000000000..9d547bf0a110a
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/udiv.mir
@@ -0,0 +1,99 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: udiv_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: udiv_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C1]]
+ ; CHECK-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[UDIV]](s32)
+ ; CHECK-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_UDIV %0, %1
+ %5:i32(s32) = G_ANYEXT %4(s8)
+ RETURN %5(s32), implicit-def $arguments
+...
+---
+name: udiv_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: udiv_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C1]]
+ ; CHECK-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[UDIV]](s32)
+ ; CHECK-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_UDIV %0, %1
+ %5:i32(s32) = G_ANYEXT %4(s16)
+ RETURN %5(s32), implicit-def $arguments
+...
+---
+name: udiv_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: udiv_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
+ ; CHECK-NEXT: RETURN [[UDIV]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_UDIV %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: udiv_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: udiv_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
+ ; CHECK-NEXT: RETURN [[UDIV]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_UDIV %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/urem.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/urem.mir
new file mode 100644
index 0000000000000..068023509eb07
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/urem.mir
@@ -0,0 +1,99 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: urem_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: urem_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C1]]
+ ; CHECK-NEXT: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[AND]], [[AND1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[UREM]](s32)
+ ; CHECK-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_UREM %0, %1
+ %5:i32(s32) = G_ANYEXT %4(s8)
+ RETURN %5(s32), implicit-def $arguments
+...
+---
+name: urem_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: urem_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C1]]
+ ; CHECK-NEXT: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[AND]], [[AND1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[UREM]](s32)
+ ; CHECK-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_UREM %0, %1
+ %5:i32(s32) = G_ANYEXT %4(s16)
+ RETURN %5(s32), implicit-def $arguments
+...
+---
+name: urem_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: urem_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
+ ; CHECK-NEXT: RETURN [[UREM]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_UREM %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: urem_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: urem_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[UREM:%[0-9]+]]:_(s64) = G_UREM [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
+ ; CHECK-NEXT: RETURN [[UREM]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_UREM %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/xor.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/xor.mir
new file mode 100644
index 0000000000000..1bc7ace2b3e7f
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/xor.mir
@@ -0,0 +1,116 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: xor_i1
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: xor_i1
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]]
+ ; CHECK-NEXT: RETURN [[XOR]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s1) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s1) = G_TRUNC %3(s32)
+ %4:_(s1) = G_XOR %1, %0
+ %5:_(s32) = G_ANYEXT %4(s1)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: xor_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: xor_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]]
+ ; CHECK-NEXT: RETURN [[XOR]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_XOR %1, %0
+ %5:_(s32) = G_ANYEXT %4(s8)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: xor_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: xor_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]]
+ ; CHECK-NEXT: RETURN [[XOR]](s32), implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_XOR %1, %0
+ %5:_(s32) = G_ANYEXT %4(s16)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: xor_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: xor_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]]
+ ; CHECK-NEXT: RETURN [[XOR]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_XOR %1, %0
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: xor_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: xor_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ARGUMENT_i64_1]], [[ARGUMENT_i64_]]
+ ; CHECK-NEXT: RETURN [[XOR]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_XOR %1, %0
+ RETURN %2(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/zext.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/zext.mir
new file mode 100644
index 0000000000000..84ee4cc9ac3e1
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/zext.mir
@@ -0,0 +1,103 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: zext_i8_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: zext_i8_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:i32(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
+ ; CHECK-NEXT: RETURN [[AND]](s32), implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %1(s32)
+ %2:i32(s32) = G_ZEXT %0(s8)
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: zext_i8_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: zext_i8_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:i32(s64) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK-NEXT: RETURN [[AND]](s64), implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %1(s32)
+ %2:i32(s64) = G_ZEXT %0(s8)
+ RETURN %2(s64), implicit-def $arguments
+...
+---
+name: zext_i16_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: zext_i16_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:i32(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
+ ; CHECK-NEXT: RETURN [[AND]](s32), implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %1(s32)
+ %2:i32(s32) = G_ZEXT %0(s16)
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: zext_i16_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: zext_i16_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:i32(s64) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK-NEXT: RETURN [[AND]](s64), implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %1(s32)
+ %2:i32(s64) = G_ZEXT %0(s16)
+ RETURN %2(s64), implicit-def $arguments
+...
+---
+name: zext_i32_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: zext_i32_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:i32(s64) = G_ZEXT [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[ZEXT]](s64), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s64) = G_ZEXT %0(s32)
+ RETURN %1(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/bitwise.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/bitwise.mir
index 157ef5b9034c2..185ab2d550084 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/bitwise.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/bitwise.mir
@@ -22,7 +22,6 @@ body: |
%2:_(s32) = G_AND %0, %1
RETURN %2(s32), implicit-def $arguments
...
-
---
name: and_i64
alignment: 1
@@ -45,6 +44,92 @@ body: |
RETURN %2(s64), implicit-def $arguments
...
+---
+name: or_i32
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: or_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:i32regbank(s32) = G_OR [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
+ ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_OR %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: or_i64
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: or_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:i64regbank(s64) = G_OR [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
+ ; CHECK-NEXT: RETURN [[OR]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_OR %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
+
+---
+name: xor_i32
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: xor_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:i32regbank(s32) = G_XOR [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
+ ; CHECK-NEXT: RETURN [[XOR]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_XOR %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: xor_i64
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: xor_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:i64regbank(s64) = G_XOR [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
+ ; CHECK-NEXT: RETURN [[XOR]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_XOR %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
+
---
name: shl_i32
alignment: 1
@@ -66,7 +151,6 @@ body: |
%2:_(s32) = G_SHL %0, %1
RETURN %2(s32), implicit-def $arguments
...
-
---
name: shl_i64
alignment: 1
@@ -110,7 +194,6 @@ body: |
%2:_(s32) = G_ASHR %0, %1
RETURN %2(s32), implicit-def $arguments
...
-
---
name: ashr_i64
alignment: 1
@@ -132,3 +215,328 @@ body: |
%2:_(s64) = G_ASHR %0, %1
RETURN %2(s64), implicit-def $arguments
...
+
+---
+name: lshr_i32
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshr_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:i32regbank(s32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:i32regbank(s32) = G_LSHR [[ARGUMENT_i32_]], [[C]](s32)
+ ; CHECK-NEXT: RETURN [[LSHR]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_CONSTANT i32 5
+ %2:_(s32) = G_LSHR %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: lshr_i64
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshr_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:i64regbank(s64) = G_CONSTANT i64 37
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:i64regbank(s64) = G_LSHR [[ARGUMENT_i64_]], [[C]](s64)
+ ; CHECK-NEXT: RETURN [[LSHR]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_CONSTANT i64 37
+ %2:_(s64) = G_LSHR %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
+
+---
+name: ctlz_i32
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:i32regbank(s32) = G_CTLZ [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[CTLZ]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_CTLZ %0
+ RETURN %1(s32), implicit-def $arguments
+...
+---
+name: ctlz_i64
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:i64regbank(s64) = G_CTLZ [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: RETURN [[CTLZ]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_CTLZ %0
+ RETURN %1(s64), implicit-def $arguments
+...
+
+---
+name: ctlz_zundef_i32
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_zundef_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:i32regbank(s32) = G_CTLZ_ZERO_UNDEF [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[CTLZ_ZERO_UNDEF]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_CTLZ_ZERO_UNDEF %0
+ RETURN %1(s32), implicit-def $arguments
+...
+---
+name: ctlz_zundef_i64
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_zundef_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:i64regbank(s64) = G_CTLZ_ZERO_UNDEF [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: RETURN [[CTLZ_ZERO_UNDEF]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_CTLZ_ZERO_UNDEF %0
+ RETURN %1(s64), implicit-def $arguments
+...
+
+---
+name: cttz_i32
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: cttz_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:i32regbank(s32) = G_CTTZ [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[CTTZ]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_CTTZ %0
+ RETURN %1(s32), implicit-def $arguments
+...
+---
+name: cttz_i64
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: cttz_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:i64regbank(s64) = G_CTTZ [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: RETURN [[CTTZ]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_CTTZ %0
+ RETURN %1(s64), implicit-def $arguments
+...
+
+---
+name: cttz_zundef_i32
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: cttz_zundef_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:i32regbank(s32) = G_CTTZ_ZERO_UNDEF [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[CTTZ_ZERO_UNDEF]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_CTTZ_ZERO_UNDEF %0
+ RETURN %1(s32), implicit-def $arguments
+...
+---
+name: cttz_zundef_i64
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: cttz_zundef_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:i64regbank(s64) = G_CTTZ_ZERO_UNDEF [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: RETURN [[CTTZ_ZERO_UNDEF]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_CTTZ_ZERO_UNDEF %0
+ RETURN %1(s64), implicit-def $arguments
+...
+
+
+---
+name: ctpop_i32
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctpop_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:i32regbank(s32) = G_CTPOP [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[CTPOP]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_CTPOP %0
+ RETURN %1(s32), implicit-def $arguments
+...
+---
+name: ctpop_i64
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctpop_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:i64regbank(s64) = G_CTPOP [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: RETURN [[CTPOP]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_CTPOP %0
+ RETURN %1(s64), implicit-def $arguments
+...
+
+---
+name: rotl_i32
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotl_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ROTL:%[0-9]+]]:i32regbank(s32) = G_ROTL [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]](s32)
+ ; CHECK-NEXT: RETURN [[ROTL]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_ROTL %0, %1(s32)
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: rotl_i64
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotl_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[ROTL:%[0-9]+]]:i64regbank(s64) = G_ROTL [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]](s64)
+ ; CHECK-NEXT: RETURN [[ROTL]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_ROTL %0, %1(s64)
+ RETURN %2(s64), implicit-def $arguments
+...
+
+---
+name: rotr_i32
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotr_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ROTR:%[0-9]+]]:i32regbank(s32) = G_ROTR [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]](s32)
+ ; CHECK-NEXT: RETURN [[ROTR]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_ROTR %0, %1(s32)
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: rotr_i64
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotr_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[ROTR:%[0-9]+]]:i64regbank(s64) = G_ROTR [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]](s64)
+ ; CHECK-NEXT: RETURN [[ROTR]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_ROTR %0, %1(s64)
+ RETURN %2(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/consts.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/consts.mir
new file mode 100644
index 0000000000000..3cf45bbcf3702
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/consts.mir
@@ -0,0 +1,72 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: const_i32
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: const_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[C:%[0-9]+]]:i32regbank(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: RETURN [[C]](s32), implicit-def $arguments
+ %0:_(s32) = G_CONSTANT i32 0
+ RETURN %0(s32), implicit-def $arguments
+...
+---
+name: const_i64
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: const_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[C:%[0-9]+]]:i64regbank(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: RETURN [[C]](s64), implicit-def $arguments
+ %0:_(s64) = G_CONSTANT i64 0
+ RETURN %0(s64), implicit-def $arguments
+...
+
+---
+name: implicit_i32
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: implicit_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:i32regbank(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: RETURN [[DEF]](s32), implicit-def $arguments
+ %0:_(s32) = G_IMPLICIT_DEF
+ RETURN %0(s32), implicit-def $arguments
+...
+---
+name: implicit_i64
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: implicit_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:i64regbank(s64) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: RETURN [[DEF]](s64), implicit-def $arguments
+ %0:_(s64) = G_IMPLICIT_DEF
+ RETURN %0(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/ext-trunc.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/ext-trunc.mir
new file mode 100644
index 0000000000000..a95bb61143547
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/ext-trunc.mir
@@ -0,0 +1,177 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: anyext
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: anyext
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:i64regbank(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[ANYEXT]](s64), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s64) = G_ANYEXT %0
+ RETURN %1(s64), implicit-def $arguments
+...
+---
+name: sext
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sext
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:i64regbank(s64) = G_SEXT [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[SEXT]](s64), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s64) = G_SEXT %0
+ RETURN %1(s64), implicit-def $arguments
+...
+---
+name: zext
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: zext
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:i64regbank(s64) = G_ZEXT [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[ZEXT]](s64), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s64) = G_ZEXT %0
+ RETURN %1(s64), implicit-def $arguments
+...
+---
+name: trunc
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: trunc
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:i32regbank(s32) = G_TRUNC [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s32) = G_TRUNC %0
+ RETURN %1(s32), implicit-def $arguments
+...
+
+---
+name: sext_inreg_i32_8
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sext_inreg_i32_8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:i32regbank(s32) = G_SEXT_INREG [[ARGUMENT_i32_]], 8
+ ; CHECK-NEXT: RETURN [[SEXT_INREG]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_SEXT_INREG %0, 8
+ RETURN %1(s32), implicit-def $arguments
+...
+---
+name: sext_inreg_i64_8
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sext_inreg_i64_8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:i64regbank(s64) = G_SEXT_INREG [[ARGUMENT_i64_]], 8
+ ; CHECK-NEXT: RETURN [[SEXT_INREG]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_SEXT_INREG %0, 8
+ RETURN %1(s64), implicit-def $arguments
+...
+
+---
+name: sext_inreg_i32_16
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sext_inreg_i32_16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:i32regbank(s32) = G_SEXT_INREG [[ARGUMENT_i32_]], 16
+ ; CHECK-NEXT: RETURN [[SEXT_INREG]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_SEXT_INREG %0, 16
+ RETURN %1(s32), implicit-def $arguments
+...
+---
+name: sext_inreg_i64_16
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sext_inreg_i64_16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:i64regbank(s64) = G_SEXT_INREG [[ARGUMENT_i64_]], 16
+ ; CHECK-NEXT: RETURN [[SEXT_INREG]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_SEXT_INREG %0, 16
+ RETURN %1(s64), implicit-def $arguments
+...
+
+---
+name: sext_inreg_i64_32
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sext_inreg_i64_32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:i64regbank(s64) = G_SEXT_INREG [[ARGUMENT_i64_]], 32
+ ; CHECK-NEXT: RETURN [[SEXT_INREG]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_SEXT_INREG %0, 32
+ RETURN %1(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/int-arithmetic.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/int-arithmetic.mir
index 1a2515d4b9abe..a2118b9744051 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/int-arithmetic.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/int-arithmetic.mir
@@ -22,7 +22,6 @@ body: |
%2:_(s32) = G_ADD %0, %1
RETURN %2(s32), implicit-def $arguments
...
-
---
name: add_i64
alignment: 1
@@ -44,3 +43,261 @@ body: |
%2:_(s64) = G_ADD %0, %1
RETURN %2(s64), implicit-def $arguments
...
+
+---
+name: sub_i32
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sub_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:i32regbank(s32) = G_SUB [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
+ ; CHECK-NEXT: RETURN [[SUB]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_SUB %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: sub_i64
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sub_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:i64regbank(s64) = G_SUB [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
+ ; CHECK-NEXT: RETURN [[SUB]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_SUB %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
+
+---
+name: mul_i32
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: mul_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:i32regbank(s32) = G_MUL [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
+ ; CHECK-NEXT: RETURN [[MUL]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_MUL %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: mul_i64
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: mul_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:i64regbank(s64) = G_MUL [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
+ ; CHECK-NEXT: RETURN [[MUL]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_MUL %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
+
+---
+name: udiv_i32
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: udiv_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[UDIV:%[0-9]+]]:i32regbank(s32) = G_UDIV [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
+ ; CHECK-NEXT: RETURN [[UDIV]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_UDIV %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: udiv_i64
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: udiv_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[UDIV:%[0-9]+]]:i64regbank(s64) = G_UDIV [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
+ ; CHECK-NEXT: RETURN [[UDIV]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_UDIV %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
+
+---
+name: sdiv_i32
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sdiv_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[SDIV:%[0-9]+]]:i32regbank(s32) = G_SDIV [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
+ ; CHECK-NEXT: RETURN [[SDIV]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_SDIV %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: sdiv_i64
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sdiv_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[SDIV:%[0-9]+]]:i64regbank(s64) = G_SDIV [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
+ ; CHECK-NEXT: RETURN [[SDIV]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_SDIV %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
+
+---
+name: urem_i32
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: urem_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[UREM:%[0-9]+]]:i32regbank(s32) = G_UREM [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
+ ; CHECK-NEXT: RETURN [[UREM]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_UREM %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: urem_i64
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: urem_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[UREM:%[0-9]+]]:i64regbank(s64) = G_UREM [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
+ ; CHECK-NEXT: RETURN [[UREM]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_UREM %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
+
+---
+name: srem_i32
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: srem_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[SREM:%[0-9]+]]:i32regbank(s32) = G_SREM [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
+ ; CHECK-NEXT: RETURN [[SREM]](s32), implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_SREM %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: srem_i64
+alignment: 1
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: srem_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[SREM:%[0-9]+]]:i64regbank(s64) = G_SREM [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
+ ; CHECK-NEXT: RETURN [[SREM]](s64), implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_SREM %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
>From 711fc036d1ce9d9b1a35fa6f617fa671d6d13eb2 Mon Sep 17 00:00:00 2001
From: Demetrius Kanios <demetrius at kanios.net>
Date: Fri, 3 Apr 2026 10:33:55 -0700
Subject: [PATCH 2/7] Address review comments
---
.../GISel/WebAssemblyInstructionSelector.cpp | 31 +------------
.../GISel/WebAssemblyLegalizerInfo.cpp | 2 +-
.../WebAssembly/WebAssemblyRegisterInfo.cpp | 46 +++++++++++++++++++
.../WebAssembly/WebAssemblyRegisterInfo.h | 3 ++
4 files changed, 52 insertions(+), 30 deletions(-)
diff --git a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp
index 7359156ccf60c..19b4cffa334bc 100644
--- a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp
+++ b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp
@@ -84,30 +84,6 @@ WebAssemblyInstructionSelector::WebAssemblyInstructionSelector(
{
}
-static const TargetRegisterClass &getRegClassForBank(const RegisterBank &RB) {
- switch (RB.getID()) {
- case WebAssembly::I32RegBankID:
- return WebAssembly::I32RegClass;
- case WebAssembly::I64RegBankID:
- return WebAssembly::I64RegClass;
- case WebAssembly::F32RegBankID:
- return WebAssembly::F32RegClass;
- case WebAssembly::F64RegBankID:
- return WebAssembly::F64RegClass;
- case WebAssembly::EXNREFRegBankID:
- return WebAssembly::EXNREFRegClass;
- case WebAssembly::EXTERNREFRegBankID:
- return WebAssembly::EXTERNREFRegClass;
- case WebAssembly::FUNCREFRegBankID:
- return WebAssembly::FUNCREFRegClass;
- case WebAssembly::V128RegBankID:
- return WebAssembly::V128RegClass;
- default:
- reportFatalInternalError(
- "Found unexpected RegisterBank in `getRegClassForBank`");
- }
-}
-
bool WebAssemblyInstructionSelector::select(MachineInstr &I) {
MachineBasicBlock &MBB = *I.getParent();
MachineFunction &MF = *MBB.getParent();
@@ -125,18 +101,15 @@ bool WebAssemblyInstructionSelector::select(MachineInstr &I) {
switch (I.getOpcode()) {
case G_IMPLICIT_DEF: {
const Register DefReg = I.getOperand(0).getReg();
- const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(DefReg);
const TargetRegisterClass *DefRC =
- dyn_cast<const TargetRegisterClass *>(RegClassOrBank);
+ TRI.getConstrainedRegClassForOperand(I.getOperand(0), MRI);
if (!DefRC) {
- const RegisterBank &RB = *cast<const RegisterBank *>(RegClassOrBank);
- DefRC = &getRegClassForBank(RB);
+ return false;
}
I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF));
-
return RBI.constrainGenericRegister(DefReg, *DefRC, MRI) != nullptr;
}
default:
diff --git a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.cpp b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.cpp
index 0b9bbc1a6853a..ab19ad9499048 100644
--- a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.cpp
+++ b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.cpp
@@ -65,8 +65,8 @@ WebAssemblyLegalizerInfo::WebAssemblyLegalizerInfo(
.clampScalar(1, s64, s64);
getActionDefinitionsBuilder(G_SEXT_INREG)
- .clampScalar(0, s32, s64)
.customFor(ST.hasSignExt(), {s32, s64})
+ .clampScalar(0, s32, s64)
.lower();
getLegacyLegalizerInfo().computeTables();
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp
index ebb5f555df67a..4b4f07bd782ad 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp
@@ -13,6 +13,7 @@
//===----------------------------------------------------------------------===//
#include "WebAssemblyRegisterInfo.h"
+#include "GISel/WebAssemblyRegisterBankInfo.h"
#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
#include "WebAssemblyFrameLowering.h"
#include "WebAssemblyInstrInfo.h"
@@ -154,3 +155,48 @@ WebAssemblyRegisterInfo::getPointerRegClass(unsigned Kind) const {
return TT.getArch() == Triple::wasm64 ? &WebAssembly::I64RegClass
: &WebAssembly::I32RegClass;
}
+
+static const TargetRegisterClass &getRegClassForBank(const RegisterBank &RB) {
+ switch (RB.getID()) {
+ case WebAssembly::I32RegBankID:
+ return WebAssembly::I32RegClass;
+ case WebAssembly::I64RegBankID:
+ return WebAssembly::I64RegClass;
+ case WebAssembly::F32RegBankID:
+ return WebAssembly::F32RegClass;
+ case WebAssembly::F64RegBankID:
+ return WebAssembly::F64RegClass;
+ case WebAssembly::EXNREFRegBankID:
+ return WebAssembly::EXNREFRegClass;
+ case WebAssembly::EXTERNREFRegBankID:
+ return WebAssembly::EXTERNREFRegClass;
+ case WebAssembly::FUNCREFRegBankID:
+ return WebAssembly::FUNCREFRegClass;
+ case WebAssembly::V128RegBankID:
+ return WebAssembly::V128RegClass;
+ default:
+ llvm_unreachable("Found unexpected RegisterBank in `getRegClassForBank`");
+ }
+}
+
+const TargetRegisterClass *
+WebAssemblyRegisterInfo::getConstrainedRegClassForOperand(
+ const MachineOperand &MO, const MachineRegisterInfo &MRI) const {
+ assert(MO.isReg());
+
+ const RegClassOrRegBank &RegClassOrBank =
+ MRI.getRegClassOrRegBank(MO.getReg());
+
+ if (RegClassOrBank.isNull())
+ return nullptr;
+
+ const TargetRegisterClass *DefRC =
+ dyn_cast<const TargetRegisterClass *>(RegClassOrBank);
+
+ if (!DefRC) {
+ const RegisterBank &RB = *cast<const RegisterBank *>(RegClassOrBank);
+ DefRC = &getRegClassForBank(RB);
+ }
+
+ return DefRC;
+}
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.h b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.h
index 3a73ff6b1b3b0..5b4293b9ec590 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.h
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.h
@@ -45,6 +45,9 @@ class WebAssemblyRegisterInfo final : public WebAssemblyGenRegisterInfo {
getPointerRegClass(unsigned Kind = 0) const override;
// This does not apply to wasm.
const uint32_t *getNoPreservedMask() const override { return nullptr; }
+
+ const TargetRegisterClass *getConstrainedRegClassForOperand(
+ const MachineOperand &MO, const MachineRegisterInfo &MRI) const override;
};
} // end namespace llvm
>From 40e6fb7072395d7e10fc6895355ac22aa98157fc Mon Sep 17 00:00:00 2001
From: Demetrius Kanios <demetrius at kanios.net>
Date: Fri, 3 Apr 2026 11:21:42 -0700
Subject: [PATCH 3/7] Lower `G_[CTLZ|CTTZ]_ZERO_UNDEF` instead of legal
---
.../GISel/WebAssemblyLegalizerInfo.cpp | 6 +-
.../WebAssembly/WebAssemblyInstrInteger.td | 8 --
.../GlobalISel/instruction-select/bitwise.mir | 82 -------------------
.../GlobalISel/legalizer/ctlz_zero_undef.mir | 40 +++++----
.../WebAssembly/GlobalISel/legalizer/cttz.mir | 8 +-
.../GlobalISel/legalizer/cttz_zero_undef.mir | 32 ++++----
.../GlobalISel/regbankselect/bitwise.mir | 79 ------------------
7 files changed, 48 insertions(+), 207 deletions(-)
diff --git a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.cpp b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.cpp
index ab19ad9499048..293ba88605354 100644
--- a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.cpp
+++ b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.cpp
@@ -11,6 +11,7 @@
//===----------------------------------------------------------------------===//
#include "WebAssemblyLegalizerInfo.h"
+#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
#include "WebAssemblySubtarget.h"
#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
@@ -40,13 +41,14 @@ WebAssemblyLegalizerInfo::WebAssemblyLegalizerInfo(
.clampScalar(0, s32, s64)
.scalarSameSizeAs(1, 0);
- getActionDefinitionsBuilder(
- {G_CTLZ, G_CTLZ_ZERO_UNDEF, G_CTTZ, G_CTTZ_ZERO_UNDEF, G_CTPOP})
+ getActionDefinitionsBuilder({G_CTLZ, G_CTTZ, G_CTPOP})
.legalFor({{s32, s32}, {s64, s64}})
.widenScalarToNextPow2(1)
.clampScalar(1, s32, s64)
.scalarSameSizeAs(0, 1);
+ getActionDefinitionsBuilder({G_CTLZ_ZERO_UNDEF, G_CTTZ_ZERO_UNDEF}).lower();
+
getActionDefinitionsBuilder({G_ROTL, G_ROTR})
.legalFor({{s32, s32}, {s64, s64}})
.scalarSameSizeAs(1, 0)
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInteger.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInteger.td
index 99ca22e21f70b..991507e883f28 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInteger.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInteger.td
@@ -82,18 +82,10 @@ defm LE_U : ComparisonInt<SETULE, "le_u", 0x4d, 0x58>;
defm GE_S : ComparisonInt<SETGE, "ge_s", 0x4e, 0x59>;
defm GE_U : ComparisonInt<SETUGE, "ge_u", 0x4f, 0x5a>;
-
defm CLZ : UnaryInt<ctlz, "clz ", 0x67, 0x79>;
-def : Pat<(ctlz_zero_undef I32:$src), (CLZ_I32 I32:$src)>;
-def : Pat<(ctlz_zero_undef I64:$src), (CLZ_I64 I64:$src)>;
-
defm CTZ : UnaryInt<cttz, "ctz ", 0x68, 0x7a>;
-def : Pat<(cttz_zero_undef I32:$src), (CTZ_I32 I32:$src)>;
-def : Pat<(cttz_zero_undef I64:$src), (CTZ_I64 I64:$src)>;
-
defm POPCNT : UnaryInt<ctpop, "popcnt", 0x69, 0x7b>;
-
defm EQZ_I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins),
[(set I32:$dst, (setcc I32:$src, 0, SETEQ))],
"i32.eqz \t$dst, $src", "i32.eqz", 0x45>;
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/bitwise.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/bitwise.mir
index 1a5943259b521..2af53ff71ce2d 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/bitwise.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/bitwise.mir
@@ -312,47 +312,6 @@ body: |
RETURN %1(s64), implicit-def $arguments
...
----
-name: ctlz_zundef_i32
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_zundef_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CLZ_I32_:%[0-9]+]]:i32 = CLZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CLZ_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32regbank(s32) = G_CTLZ_ZERO_UNDEF %0
- RETURN %1(s32), implicit-def $arguments
-...
----
-name: ctlz_zundef_i64
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_zundef_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CLZ_I64_:%[0-9]+]]:i64 = CLZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CLZ_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64regbank(s64) = G_CTLZ_ZERO_UNDEF %0
- RETURN %1(s64), implicit-def $arguments
-...
-
---
name: cttz_i32
alignment: 1
@@ -394,47 +353,6 @@ body: |
RETURN %1(s64), implicit-def $arguments
...
----
-name: cttz_zundef_i32
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: cttz_zundef_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CTZ_I32_:%[0-9]+]]:i32 = CTZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CTZ_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32regbank(s32) = G_CTTZ_ZERO_UNDEF %0
- RETURN %1(s32), implicit-def $arguments
-...
----
-name: cttz_zundef_i64
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: cttz_zundef_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTZ_I64_:%[0-9]+]]:i64 = CTZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CTZ_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64regbank(s64) = G_CTTZ_ZERO_UNDEF %0
- RETURN %1(s64), implicit-def $arguments
-...
-
---
name: ctpop_i32
alignment: 1
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ctlz_zero_undef.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ctlz_zero_undef.mir
index 045706eb22c14..e00396d20b7e3 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ctlz_zero_undef.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ctlz_zero_undef.mir
@@ -13,10 +13,12 @@ body: |
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
- ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[SHL]](s32)
- ; CHECK-NEXT: RETURN [[CTLZ_ZERO_UNDEF]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
+ ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = nuw G_SUB [[CTLZ]], [[C1]]
+ ; CHECK-NEXT: RETURN [[SUB]](s32), implicit-def $arguments
%1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s8) = G_TRUNC %1(s32)
%2:_(s8) = G_CTLZ_ZERO_UNDEF %0
@@ -36,10 +38,12 @@ body: |
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
- ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[SHL]](s32)
- ; CHECK-NEXT: RETURN [[CTLZ_ZERO_UNDEF]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
+ ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = nuw G_SUB [[CTLZ]], [[C1]]
+ ; CHECK-NEXT: RETURN [[SUB]](s32), implicit-def $arguments
%1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s16) = G_TRUNC %1(s32)
%2:_(s16) = G_CTLZ_ZERO_UNDEF %0
@@ -59,8 +63,8 @@ body: |
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[CTLZ_ZERO_UNDEF]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[CTLZ]](s32), implicit-def $arguments
%0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%1:_(s32) = G_CTLZ_ZERO_UNDEF %0
RETURN %1(s32), implicit-def $arguments
@@ -78,8 +82,8 @@ body: |
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[CTLZ_ZERO_UNDEF]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[CTLZ]](s32), implicit-def $arguments
%0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%1:_(s8) = G_CTLZ_ZERO_UNDEF %0
%2:_(s32) = G_ANYEXT %1(s8)
@@ -98,8 +102,8 @@ body: |
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s64) = G_CTLZ_ZERO_UNDEF [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: RETURN [[CTLZ_ZERO_UNDEF]](s64), implicit-def $arguments
+ ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: RETURN [[CTLZ]](s64), implicit-def $arguments
%0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
%1:_(s64) = G_CTLZ_ZERO_UNDEF %0
RETURN %1(s64), implicit-def $arguments
@@ -117,8 +121,8 @@ body: |
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s64) = G_CTLZ_ZERO_UNDEF [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTLZ_ZERO_UNDEF]](s64)
+ ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTLZ]](s64)
; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
%0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
%1:_(s8) = G_CTLZ_ZERO_UNDEF %0
@@ -138,8 +142,8 @@ body: |
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s64) = G_CTLZ_ZERO_UNDEF [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTLZ_ZERO_UNDEF]](s64)
+ ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTLZ]](s64)
; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
%0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
%1:_(s32) = G_CTLZ_ZERO_UNDEF %0
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/cttz.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/cttz.mir
index 1d1d90b8420d6..2feeb10b39c38 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/cttz.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/cttz.mir
@@ -15,8 +15,8 @@ body: |
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ARGUMENT_i32_]], [[C]]
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
- ; CHECK-NEXT: RETURN [[CTTZ_ZERO_UNDEF]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32)
+ ; CHECK-NEXT: RETURN [[CTTZ]](s32), implicit-def $arguments
%1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s8) = G_TRUNC %1(s32)
%2:_(s8) = G_CTTZ %0
@@ -38,8 +38,8 @@ body: |
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ARGUMENT_i32_]], [[C]]
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
- ; CHECK-NEXT: RETURN [[CTTZ_ZERO_UNDEF]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32)
+ ; CHECK-NEXT: RETURN [[CTTZ]](s32), implicit-def $arguments
%1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s16) = G_TRUNC %1(s32)
%2:_(s16) = G_CTTZ %0
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/cttz_zero_undef.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/cttz_zero_undef.mir
index adb0cab5879d0..b76234b48fe10 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/cttz_zero_undef.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/cttz_zero_undef.mir
@@ -13,8 +13,10 @@ body: |
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[CTTZ_ZERO_UNDEF]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ARGUMENT_i32_]], [[C]]
+ ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32)
+ ; CHECK-NEXT: RETURN [[CTTZ]](s32), implicit-def $arguments
%1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s8) = G_TRUNC %1(s32)
%2:_(s8) = G_CTTZ_ZERO_UNDEF %0
@@ -34,8 +36,10 @@ body: |
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[CTTZ_ZERO_UNDEF]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ARGUMENT_i32_]], [[C]]
+ ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32)
+ ; CHECK-NEXT: RETURN [[CTTZ]](s32), implicit-def $arguments
%1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s16) = G_TRUNC %1(s32)
%2:_(s16) = G_CTTZ_ZERO_UNDEF %0
@@ -55,8 +59,8 @@ body: |
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[CTTZ_ZERO_UNDEF]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[CTTZ]](s32), implicit-def $arguments
%0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%1:_(s32) = G_CTTZ_ZERO_UNDEF %0
RETURN %1(s32), implicit-def $arguments
@@ -74,8 +78,8 @@ body: |
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[CTTZ_ZERO_UNDEF]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: RETURN [[CTTZ]](s32), implicit-def $arguments
%0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%1:_(s8) = G_CTTZ_ZERO_UNDEF %0
%2:_(s32) = G_ANYEXT %1(s8)
@@ -94,8 +98,8 @@ body: |
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s64) = G_CTTZ_ZERO_UNDEF [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: RETURN [[CTTZ_ZERO_UNDEF]](s64), implicit-def $arguments
+ ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s64) = G_CTTZ [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: RETURN [[CTTZ]](s64), implicit-def $arguments
%0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
%1:_(s64) = G_CTTZ_ZERO_UNDEF %0
RETURN %1(s64), implicit-def $arguments
@@ -113,8 +117,8 @@ body: |
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s64) = G_CTTZ_ZERO_UNDEF [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTTZ_ZERO_UNDEF]](s64)
+ ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s64) = G_CTTZ [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTTZ]](s64)
; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
%0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
%1:_(s8) = G_CTTZ_ZERO_UNDEF %0
@@ -134,8 +138,8 @@ body: |
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s64) = G_CTTZ_ZERO_UNDEF [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTTZ_ZERO_UNDEF]](s64)
+ ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s64) = G_CTTZ [[ARGUMENT_i64_]](s64)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTTZ]](s64)
; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
%0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
%1:_(s32) = G_CTTZ_ZERO_UNDEF %0
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/bitwise.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/bitwise.mir
index 185ab2d550084..9657732d43aaf 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/bitwise.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/bitwise.mir
@@ -298,45 +298,6 @@ body: |
RETURN %1(s64), implicit-def $arguments
...
----
-name: ctlz_zundef_i32
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_zundef_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:i32regbank(s32) = G_CTLZ_ZERO_UNDEF [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[CTLZ_ZERO_UNDEF]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_CTLZ_ZERO_UNDEF %0
- RETURN %1(s32), implicit-def $arguments
-...
----
-name: ctlz_zundef_i64
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_zundef_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:i64regbank(s64) = G_CTLZ_ZERO_UNDEF [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: RETURN [[CTLZ_ZERO_UNDEF]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_CTLZ_ZERO_UNDEF %0
- RETURN %1(s64), implicit-def $arguments
-...
-
---
name: cttz_i32
alignment: 1
@@ -376,46 +337,6 @@ body: |
RETURN %1(s64), implicit-def $arguments
...
----
-name: cttz_zundef_i32
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: cttz_zundef_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:i32regbank(s32) = G_CTTZ_ZERO_UNDEF [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[CTTZ_ZERO_UNDEF]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_CTTZ_ZERO_UNDEF %0
- RETURN %1(s32), implicit-def $arguments
-...
----
-name: cttz_zundef_i64
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: cttz_zundef_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:i64regbank(s64) = G_CTTZ_ZERO_UNDEF [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: RETURN [[CTTZ_ZERO_UNDEF]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_CTTZ_ZERO_UNDEF %0
- RETURN %1(s64), implicit-def $arguments
-...
-
-
---
name: ctpop_i32
alignment: 1
>From 459790262c77c986adf28a1f5fa120debd077302 Mon Sep 17 00:00:00 2001
From: Demetrius Kanios <demetrius at kanios.net>
Date: Tue, 7 Apr 2026 13:24:44 -0700
Subject: [PATCH 4/7] Fix typo (i32 => i64 reg class) in some legalizer tests.
[skip ci]
---
.../WebAssembly/GlobalISel/legalizer/anyext.mir | 12 ++++++------
.../WebAssembly/GlobalISel/legalizer/sext.mir | 16 ++++++++--------
.../WebAssembly/GlobalISel/legalizer/zext.mir | 12 ++++++------
3 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/anyext.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/anyext.mir
index 7380ad857cd9d..32148eae33fa3 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/anyext.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/anyext.mir
@@ -31,11 +31,11 @@ body: |
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:i32(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:i64(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
; CHECK-NEXT: RETURN [[ANYEXT]](s64), implicit-def $arguments
%1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s8) = G_TRUNC %1(s32)
- %2:i32(s64) = G_ANYEXT %0(s8)
+ %2:i64(s64) = G_ANYEXT %0(s8)
RETURN %2(s64), implicit-def $arguments
...
---
@@ -68,11 +68,11 @@ body: |
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:i32(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:i64(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
; CHECK-NEXT: RETURN [[ANYEXT]](s64), implicit-def $arguments
%1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s16) = G_TRUNC %1(s32)
- %2:i32(s64) = G_ANYEXT %0(s16)
+ %2:i64(s64) = G_ANYEXT %0(s16)
RETURN %2(s64), implicit-def $arguments
...
---
@@ -87,9 +87,9 @@ body: |
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:i32(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:i64(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
; CHECK-NEXT: RETURN [[ANYEXT]](s64), implicit-def $arguments
%0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s64) = G_ANYEXT %0(s32)
+ %1:i64(s64) = G_ANYEXT %0(s32)
RETURN %1(s64), implicit-def $arguments
...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sext.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sext.mir
index 6b443b1f91e82..7c9c704284356 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sext.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sext.mir
@@ -45,7 +45,7 @@ body: |
; NO-SIGNEXT-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C]](s64)
- ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:i32(s64) = G_ASHR [[SHL]], [[C]](s64)
+ ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:i64(s64) = G_ASHR [[SHL]], [[C]](s64)
; NO-SIGNEXT-NEXT: RETURN [[ASHR]](s64), implicit-def $arguments
;
; SIGNEXT-LABEL: name: sext_i8_i64
@@ -53,11 +53,11 @@ body: |
; SIGNEXT-NEXT: {{ $}}
; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
; SIGNEXT-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
- ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:i32(s64) = G_SEXT_INREG [[ANYEXT]], 8
+ ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:i64(s64) = G_SEXT_INREG [[ANYEXT]], 8
; SIGNEXT-NEXT: RETURN [[SEXT_INREG]](s64), implicit-def $arguments
%1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s8) = G_TRUNC %1(s32)
- %2:i32(s64) = G_SEXT %0(s8)
+ %2:i64(s64) = G_SEXT %0(s8)
RETURN %2(s64), implicit-def $arguments
...
---
@@ -103,7 +103,7 @@ body: |
; NO-SIGNEXT-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C]](s64)
- ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:i32(s64) = G_ASHR [[SHL]], [[C]](s64)
+ ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:i64(s64) = G_ASHR [[SHL]], [[C]](s64)
; NO-SIGNEXT-NEXT: RETURN [[ASHR]](s64), implicit-def $arguments
;
; SIGNEXT-LABEL: name: sext_i16_i64
@@ -111,11 +111,11 @@ body: |
; SIGNEXT-NEXT: {{ $}}
; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
; SIGNEXT-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
- ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:i32(s64) = G_SEXT_INREG [[ANYEXT]], 16
+ ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:i64(s64) = G_SEXT_INREG [[ANYEXT]], 16
; SIGNEXT-NEXT: RETURN [[SEXT_INREG]](s64), implicit-def $arguments
%1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s16) = G_TRUNC %1(s32)
- %2:i32(s64) = G_SEXT %0(s16)
+ %2:i64(s64) = G_SEXT %0(s16)
RETURN %2(s64), implicit-def $arguments
...
---
@@ -130,9 +130,9 @@ body: |
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:i32(s64) = G_SEXT [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:i64(s64) = G_SEXT [[ARGUMENT_i32_]](s32)
; CHECK-NEXT: RETURN [[SEXT]](s64), implicit-def $arguments
%0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s64) = G_SEXT %0(s32)
+ %1:i64(s64) = G_SEXT %0(s32)
RETURN %1(s64), implicit-def $arguments
...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/zext.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/zext.mir
index 84ee4cc9ac3e1..71c494bc17dc7 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/zext.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/zext.mir
@@ -35,11 +35,11 @@ body: |
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:i32(s64) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:i64(s64) = G_AND [[ANYEXT]], [[C]]
; CHECK-NEXT: RETURN [[AND]](s64), implicit-def $arguments
%1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s8) = G_TRUNC %1(s32)
- %2:i32(s64) = G_ZEXT %0(s8)
+ %2:i64(s64) = G_ZEXT %0(s8)
RETURN %2(s64), implicit-def $arguments
...
---
@@ -76,11 +76,11 @@ body: |
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:i32(s64) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:i64(s64) = G_AND [[ANYEXT]], [[C]]
; CHECK-NEXT: RETURN [[AND]](s64), implicit-def $arguments
%1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s16) = G_TRUNC %1(s32)
- %2:i32(s64) = G_ZEXT %0(s16)
+ %2:i64(s64) = G_ZEXT %0(s16)
RETURN %2(s64), implicit-def $arguments
...
---
@@ -95,9 +95,9 @@ body: |
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:i32(s64) = G_ZEXT [[ARGUMENT_i32_]](s32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:i64(s64) = G_ZEXT [[ARGUMENT_i32_]](s32)
; CHECK-NEXT: RETURN [[ZEXT]](s64), implicit-def $arguments
%0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s64) = G_ZEXT %0(s32)
+ %1:i64(s64) = G_ZEXT %0(s32)
RETURN %1(s64), implicit-def $arguments
...
>From fd5eba4f563277db3d232c3e1ee9725a6db6e5a3 Mon Sep 17 00:00:00 2001
From: Demetrius Kanios <demetrius at kanios.net>
Date: Tue, 7 Apr 2026 14:35:22 -0700
Subject: [PATCH 5/7] Merge legalizer, regbankselect, and instruction-select
tests.
---
.../GISel/WebAssemblyRegisterBankInfo.cpp | 26 +
.../WebAssembly/GlobalISel/gmir/add.mir | 217 ++++++++
.../GlobalISel/{legalizer => gmir}/and.mir | 42 +-
.../GlobalISel/{legalizer => gmir}/anyext.mir | 28 +-
.../WebAssembly/GlobalISel/gmir/ashr.mir | 331 ++++++++++++
.../{legalizer => gmir}/constant.mir | 34 +-
.../WebAssembly/GlobalISel/gmir/ctlz.mir | 152 ++++++
.../GlobalISel/gmir/ctlz_zero_undef.mir | 152 ++++++
.../GlobalISel/{legalizer => gmir}/ctpop.mir | 56 +-
.../GlobalISel/{legalizer => gmir}/cttz.mir | 56 +-
.../{legalizer => gmir}/cttz_zero_undef.mir | 56 +-
.../WebAssembly/GlobalISel/gmir/fshl.mir | 382 ++++++++++++++
.../WebAssembly/GlobalISel/gmir/fshr.mir | 378 ++++++++++++++
.../{legalizer => gmir}/implicit_def.mir | 18 +-
.../WebAssembly/GlobalISel/gmir/lshr.mir | 286 +++++++++++
.../GlobalISel/{legalizer => gmir}/mul.mir | 36 +-
.../GlobalISel/{legalizer => gmir}/or.mir | 42 +-
.../WebAssembly/GlobalISel/gmir/rotl.mir | 303 +++++++++++
.../WebAssembly/GlobalISel/gmir/rotr.mir | 303 +++++++++++
.../WebAssembly/GlobalISel/gmir/sdiv.mir | 122 +++++
.../WebAssembly/GlobalISel/gmir/sext.mir | 138 +++++
.../GlobalISel/gmir/sext_inreg.mir | 181 +++++++
.../WebAssembly/GlobalISel/gmir/shl.mir | 278 ++++++++++
.../WebAssembly/GlobalISel/gmir/srem.mir | 122 +++++
.../GlobalISel/{legalizer => gmir}/sub.mir | 36 +-
.../GlobalISel/{legalizer => gmir}/trunc.mir | 28 +-
.../WebAssembly/GlobalISel/gmir/udiv.mir | 97 ++++
.../WebAssembly/GlobalISel/gmir/urem.mir | 97 ++++
.../GlobalISel/{legalizer => gmir}/xor.mir | 42 +-
.../WebAssembly/GlobalISel/gmir/zext.mir | 103 ++++
.../GlobalISel/instruction-select/bitwise.mir | 485 ------------------
.../GlobalISel/instruction-select/consts.mir | 76 ---
.../instruction-select/ext-trunc.mir | 186 -------
.../instruction-select/int-arithmetic.mir | 317 ------------
.../WebAssembly/GlobalISel/legalizer/add.mir | 219 --------
.../WebAssembly/GlobalISel/legalizer/ashr.mir | 331 ------------
.../WebAssembly/GlobalISel/legalizer/ctlz.mir | 152 ------
.../GlobalISel/legalizer/ctlz_zero_undef.mir | 152 ------
.../WebAssembly/GlobalISel/legalizer/fshl.mir | 393 --------------
.../WebAssembly/GlobalISel/legalizer/fshr.mir | 389 --------------
.../WebAssembly/GlobalISel/legalizer/lshr.mir | 286 -----------
.../WebAssembly/GlobalISel/legalizer/rotl.mir | 303 -----------
.../WebAssembly/GlobalISel/legalizer/rotr.mir | 303 -----------
.../WebAssembly/GlobalISel/legalizer/sdiv.mir | 126 -----
.../WebAssembly/GlobalISel/legalizer/sext.mir | 138 -----
.../GlobalISel/legalizer/sext_inreg.mir | 181 -------
.../WebAssembly/GlobalISel/legalizer/shl.mir | 278 ----------
.../WebAssembly/GlobalISel/legalizer/srem.mir | 126 -----
.../WebAssembly/GlobalISel/legalizer/udiv.mir | 99 ----
.../WebAssembly/GlobalISel/legalizer/urem.mir | 99 ----
.../WebAssembly/GlobalISel/legalizer/zext.mir | 103 ----
.../GlobalISel/regbankselect/bitwise.mir | 463 -----------------
.../GlobalISel/regbankselect/consts.mir | 72 ---
.../GlobalISel/regbankselect/ext-trunc.mir | 177 -------
.../regbankselect/int-arithmetic.mir | 303 -----------
55 files changed, 3903 insertions(+), 5996 deletions(-)
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/add.mir
rename llvm/test/CodeGen/WebAssembly/GlobalISel/{legalizer => gmir}/and.mir (55%)
rename llvm/test/CodeGen/WebAssembly/GlobalISel/{legalizer => gmir}/anyext.mir (61%)
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ashr.mir
rename llvm/test/CodeGen/WebAssembly/GlobalISel/{legalizer => gmir}/constant.mir (68%)
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ctlz.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ctlz_zero_undef.mir
rename llvm/test/CodeGen/WebAssembly/GlobalISel/{legalizer => gmir}/ctpop.mir (51%)
rename llvm/test/CodeGen/WebAssembly/GlobalISel/{legalizer => gmir}/cttz.mir (51%)
rename llvm/test/CodeGen/WebAssembly/GlobalISel/{legalizer => gmir}/cttz_zero_undef.mir (53%)
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/fshl.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/fshr.mir
rename llvm/test/CodeGen/WebAssembly/GlobalISel/{legalizer => gmir}/implicit_def.mir (73%)
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/lshr.mir
rename llvm/test/CodeGen/WebAssembly/GlobalISel/{legalizer => gmir}/mul.mir (55%)
rename llvm/test/CodeGen/WebAssembly/GlobalISel/{legalizer => gmir}/or.mir (55%)
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/rotl.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/rotr.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sdiv.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sext.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sext_inreg.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/shl.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/srem.mir
rename llvm/test/CodeGen/WebAssembly/GlobalISel/{legalizer => gmir}/sub.mir (55%)
rename llvm/test/CodeGen/WebAssembly/GlobalISel/{legalizer => gmir}/trunc.mir (62%)
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/udiv.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/urem.mir
rename llvm/test/CodeGen/WebAssembly/GlobalISel/{legalizer => gmir}/xor.mir (55%)
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/zext.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/bitwise.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/consts.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/ext-trunc.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/int-arithmetic.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/add.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ashr.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ctlz.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ctlz_zero_undef.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/fshl.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/fshr.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/lshr.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/rotl.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/rotr.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sdiv.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sext.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sext_inreg.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/shl.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/srem.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/udiv.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/urem.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/zext.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/bitwise.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/consts.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/ext-trunc.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/int-arithmetic.mir
diff --git a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyRegisterBankInfo.cpp b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyRegisterBankInfo.cpp
index f7be420b49d2f..ef1b5bcc65a96 100644
--- a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyRegisterBankInfo.cpp
+++ b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyRegisterBankInfo.cpp
@@ -14,6 +14,7 @@
#include "WebAssemblyRegisterBankInfo.h"
#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
#include "WebAssemblyRegisterInfo.h"
+#include "WebAssemblySubtarget.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
@@ -66,6 +67,8 @@ WebAssemblyRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
unsigned Opc = MI.getOpcode();
const MachineFunction &MF = *MI.getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo();
+ const WebAssemblySubtarget &STI = MF.getSubtarget<WebAssemblySubtarget>();
+ const WebAssemblyRegisterInfo &TRI = *STI.getRegisterInfo();
if ((Opc != TargetOpcode::COPY && !isPreISelGenericOpcode(Opc)) ||
Opc == TargetOpcode::G_PHI) {
@@ -134,6 +137,29 @@ WebAssemblyRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
OperandsMapping =
getOperandsMapping({&Op0IntValueMapping, &Op0IntValueMapping, nullptr});
break;
+ case COPY: {
+ Register DstReg = MI.getOperand(0).getReg();
+ Register SrcReg = MI.getOperand(1).getReg();
+
+ const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI);
+ const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI);
+
+ if (!DstRB)
+ DstRB = SrcRB;
+ else if (!SrcRB)
+ SrcRB = DstRB;
+
+ assert(DstRB && SrcRB && "Both RegBank were nullptr");
+
+ if (DstRB != SrcRB) {
+ break; // for now, only allow no-op copies
+ }
+
+ return getInstructionMapping(
+ MappingID, /*Cost=*/1, &Op0IntValueMapping,
+ // We only care about the mapping of the destination for COPY.
+ 1);
+ }
}
if (!OperandsMapping)
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/add.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/add.mir
new file mode 100644
index 0000000000000..679ca0da196db
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/add.mir
@@ -0,0 +1,217 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=-sign-ext -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NO-SIGNEXT
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=+sign-ext -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,SIGNEXT
+
+---
+name: add_i8_zext
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: add_i8_zext
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ADD_I32_:%[0-9]+]]:i32 = ADD_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ADD_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[AND_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_ADD %0, %1
+ %5:i32(s32) = G_ZEXT %4(s8)
+ RETURN %5(s32), implicit-def $arguments
+...
+
+---
+name: add_i8_sext
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: add_i8_sext
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[ADD_I32_:%[0-9]+]]:i32 = ADD_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 24, implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ADD_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: add_i8_sext
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; SIGNEXT-NEXT: [[ADD_I32_:%[0-9]+]]:i32 = ADD_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: [[I32_EXTEND8_S_I32_:%[0-9]+]]:i32 = I32_EXTEND8_S_I32 [[ADD_I32_]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: RETURN [[I32_EXTEND8_S_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_ADD %0, %1
+ %5:i32(s32) = G_SEXT %4(s8)
+ RETURN %5(s32), implicit-def $arguments
+...
+
+---
+name: add_i8_aext
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: add_i8_aext
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ADD_I32_:%[0-9]+]]:i32 = ADD_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[ADD_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_ADD %0, %1
+ %5:i32(s32) = G_ANYEXT %4(s8)
+ RETURN %5(s32), implicit-def $arguments
+...
+
+---
+name: add_i16_zext
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: add_i16_zext
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ADD_I32_:%[0-9]+]]:i32 = ADD_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ADD_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[AND_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_ADD %0, %1
+ %5:i32(s32) = G_ZEXT %4(s16)
+ RETURN %5(s32), implicit-def $arguments
+...
+
+---
+name: add_i16_sext
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: add_i16_sext
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[ADD_I32_:%[0-9]+]]:i32 = ADD_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 16, implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ADD_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: add_i16_sext
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; SIGNEXT-NEXT: [[ADD_I32_:%[0-9]+]]:i32 = ADD_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: [[I32_EXTEND16_S_I32_:%[0-9]+]]:i32 = I32_EXTEND16_S_I32 [[ADD_I32_]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: RETURN [[I32_EXTEND16_S_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_ADD %0, %1
+ %5:i32(s32) = G_SEXT %4(s16)
+ RETURN %5(s32), implicit-def $arguments
+...
+
+---
+name: add_i16_aext
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: add_i16_aext
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ADD_I32_:%[0-9]+]]:i32 = ADD_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[ADD_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_ADD %0, %1
+ %5:i32(s32) = G_ANYEXT %4(s16)
+ RETURN %5(s32), implicit-def $arguments
+...
+
+---
+name: add_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: add_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ADD_I32_:%[0-9]+]]:i32 = ADD_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[ADD_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_ADD %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+
+---
+name: add_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: add_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[ADD_I64_:%[0-9]+]]:i64 = ADD_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[ADD_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_ADD %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/and.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/and.mir
similarity index 55%
rename from llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/and.mir
rename to llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/and.mir
index 52c2de6715dd3..f6b638e577027 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/and.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/and.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: and_i1
@@ -12,10 +12,10 @@ body: |
; CHECK-LABEL: name: and_i1
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]]
- ; CHECK-NEXT: RETURN [[AND]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[AND_I32_]], implicit-def $arguments
%2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s1) = G_TRUNC %2(s32)
%3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
@@ -36,10 +36,10 @@ body: |
; CHECK-LABEL: name: and_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]]
- ; CHECK-NEXT: RETURN [[AND]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[AND_I32_]], implicit-def $arguments
%2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s8) = G_TRUNC %2(s32)
%3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
@@ -60,10 +60,10 @@ body: |
; CHECK-LABEL: name: and_i16
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]]
- ; CHECK-NEXT: RETURN [[AND]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[AND_I32_]], implicit-def $arguments
%2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s16) = G_TRUNC %2(s32)
%3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
@@ -84,10 +84,10 @@ body: |
; CHECK-LABEL: name: and_i32
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]]
- ; CHECK-NEXT: RETURN [[AND]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[AND_I32_]], implicit-def $arguments
%0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
%2:_(s32) = G_AND %1, %0
@@ -105,10 +105,10 @@ body: |
; CHECK-LABEL: name: and_i64
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ARGUMENT_i64_1]], [[ARGUMENT_i64_]]
- ; CHECK-NEXT: RETURN [[AND]](s64), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[ARGUMENT_i64_1]], [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[AND_I64_]], implicit-def $arguments
%0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
%1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
%2:_(s64) = G_AND %1, %0
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/anyext.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/anyext.mir
similarity index 61%
rename from llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/anyext.mir
rename to llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/anyext.mir
index 32148eae33fa3..befdee3ca3181 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/anyext.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/anyext.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: aext_i8_i32
@@ -12,8 +12,8 @@ body: |
; CHECK-LABEL: name: aext_i8_i32
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: RETURN [[ARGUMENT_i32_]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: RETURN [[ARGUMENT_i32_]], implicit-def $arguments
%1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s8) = G_TRUNC %1(s32)
%2:i32(s32) = G_ANYEXT %0(s8)
@@ -30,9 +30,9 @@ body: |
; CHECK-LABEL: name: aext_i8_i64
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:i64(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[ANYEXT]](s64), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I64_EXTEND_U_I32_]], implicit-def $arguments
%1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s8) = G_TRUNC %1(s32)
%2:i64(s64) = G_ANYEXT %0(s8)
@@ -49,8 +49,8 @@ body: |
; CHECK-LABEL: name: aext_i16_i32
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: RETURN [[ARGUMENT_i32_]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: RETURN [[ARGUMENT_i32_]], implicit-def $arguments
%1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s16) = G_TRUNC %1(s32)
%2:i32(s32) = G_ANYEXT %0(s16)
@@ -67,9 +67,9 @@ body: |
; CHECK-LABEL: name: aext_i16_i64
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:i64(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[ANYEXT]](s64), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I64_EXTEND_U_I32_]], implicit-def $arguments
%1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s16) = G_TRUNC %1(s32)
%2:i64(s64) = G_ANYEXT %0(s16)
@@ -86,9 +86,9 @@ body: |
; CHECK-LABEL: name: aext_i32_i64
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:i64(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[ANYEXT]](s64), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I64_EXTEND_U_I32_]], implicit-def $arguments
%0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%1:i64(s64) = G_ANYEXT %0(s32)
RETURN %1(s64), implicit-def $arguments
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ashr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ashr.mir
new file mode 100644
index 0000000000000..ae0fb5d277094
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ashr.mir
@@ -0,0 +1,331 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=-sign-ext -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NO-SIGNEXT
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=+sign-ext -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,SIGNEXT
+
+---
+name: ashr_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: ashr_i8
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 5, implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 24, implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHR_S_I32_1:%[0-9]+]]:i32 = SHR_S_I32 [[SHR_S_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I32_1]], implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: ashr_i8
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 5, implicit-def dead $arguments
+ ; SIGNEXT-NEXT: [[I32_EXTEND8_S_I32_:%[0-9]+]]:i32 = I32_EXTEND8_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[I32_EXTEND8_S_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %1:_(s8) = G_CONSTANT i8 5
+ %3:_(s8) = G_ASHR %0, %1
+ %4:_(s32) = G_ANYEXT %3(s8)
+ RETURN %4(s32), implicit-def $arguments
+
+...
+---
+name: ashrv_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: ashrv_i8
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 24, implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHR_S_I32_1:%[0-9]+]]:i32 = SHR_S_I32 [[SHR_S_I32_]], [[AND_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I32_1]], implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: ashrv_i8
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; SIGNEXT-NEXT: [[I32_EXTEND8_S_I32_:%[0-9]+]]:i32 = I32_EXTEND8_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; SIGNEXT-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[I32_EXTEND8_S_I32_]], [[AND_I32_]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_ASHR %0, %1
+ %5:_(s32) = G_ANYEXT %4(s8)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: ashr_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: ashr_i16
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 13, implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 16, implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHR_S_I32_1:%[0-9]+]]:i32 = SHR_S_I32 [[SHR_S_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I32_1]], implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: ashr_i16
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 13, implicit-def dead $arguments
+ ; SIGNEXT-NEXT: [[I32_EXTEND16_S_I32_:%[0-9]+]]:i32 = I32_EXTEND16_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[I32_EXTEND16_S_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %1:_(s16) = G_CONSTANT i16 13
+ %3:_(s16) = G_ASHR %0, %1
+ %4:_(s32) = G_ANYEXT %3(s16)
+ RETURN %4(s32), implicit-def $arguments
+
+...
+---
+name: ashrv_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: ashrv_i16
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 16, implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHR_S_I32_1:%[0-9]+]]:i32 = SHR_S_I32 [[SHR_S_I32_]], [[AND_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I32_1]], implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: ashrv_i16
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; SIGNEXT-NEXT: [[I32_EXTEND16_S_I32_:%[0-9]+]]:i32 = I32_EXTEND16_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
+ ; SIGNEXT-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[I32_EXTEND16_S_I32_]], [[AND_I32_]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_ASHR %0, %1
+ %5:_(s32) = G_ANYEXT %4(s16)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: ashr_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ashr_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_CONSTANT i32 21
+ %2:_(s32) = G_ASHR %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: ashrv_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ashrv_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_ASHR %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: ashr_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ashr_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s8) = G_CONSTANT i8 21
+ %2:_(s32) = G_ASHR %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: ashrv_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ashrv_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[ARGUMENT_i32_]], [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %2(s32)
+ %3:_(s32) = G_ASHR %0, %1
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: ashr_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ashr_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_S_I64_:%[0-9]+]]:i64 = SHR_S_I64 [[ARGUMENT_i64_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_S_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_CONSTANT i64 37
+ %2:_(s64) = G_ASHR %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: ashrv_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ashrv_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[SHR_S_I64_:%[0-9]+]]:i64 = SHR_S_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_S_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_ASHR %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: ashr_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ashr_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_]], [[CONST_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_S_I64_:%[0-9]+]]:i64 = SHR_S_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_S_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s8) = G_CONSTANT i8 37
+ %2:_(s64) = G_ASHR %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: ashrv_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ashrv_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_S_I64_:%[0-9]+]]:i64 = SHR_S_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_S_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %2(s32)
+ %3:_(s64) = G_ASHR %0, %1
+ RETURN %3(s64), implicit-def $arguments
+
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/constant.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/constant.mir
similarity index 68%
rename from llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/constant.mir
rename to llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/constant.mir
index 41b06f5c5c836..d5bff2a5a80cb 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/constant.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/constant.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: const_i8_zext
@@ -12,8 +12,8 @@ body: |
; CHECK-LABEL: name: const_i8_zext
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: RETURN [[C]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CONST_I32_]], implicit-def $arguments
%0:_(s8) = G_CONSTANT i8 255
%1:_(s32) = G_ZEXT %0(s8)
RETURN %1(s32), implicit-def $arguments
@@ -30,8 +30,8 @@ body: |
; CHECK-LABEL: name: const_i8_sext
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK-NEXT: RETURN [[C]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CONST_I32_]], implicit-def $arguments
%0:_(s8) = G_CONSTANT i8 255
%1:_(s32) = G_SEXT %0(s8)
RETURN %1(s32), implicit-def $arguments
@@ -48,8 +48,8 @@ body: |
; CHECK-LABEL: name: const_i8_aext
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK-NEXT: RETURN [[C]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CONST_I32_]], implicit-def $arguments
%0:_(s8) = G_CONSTANT i8 255
%1:_(s32) = G_ANYEXT %0(s8)
RETURN %1(s32), implicit-def $arguments
@@ -67,8 +67,8 @@ body: |
; CHECK-LABEL: name: const_i16_zext
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: RETURN [[C]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CONST_I32_]], implicit-def $arguments
%0:_(s16) = G_CONSTANT i16 65535
%1:_(s32) = G_ZEXT %0(s16)
RETURN %1(s32), implicit-def $arguments
@@ -85,8 +85,8 @@ body: |
; CHECK-LABEL: name: const_i16_sext
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK-NEXT: RETURN [[C]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CONST_I32_]], implicit-def $arguments
%0:_(s16) = G_CONSTANT i16 65535
%1:_(s32) = G_SEXT %0(s16)
RETURN %1(s32), implicit-def $arguments
@@ -103,8 +103,8 @@ body: |
; CHECK-LABEL: name: const_i16_aext
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK-NEXT: RETURN [[C]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CONST_I32_]], implicit-def $arguments
%0:_(s16) = G_CONSTANT i16 65535
%1:_(s32) = G_ANYEXT %0(s16)
RETURN %1(s32), implicit-def $arguments
@@ -121,8 +121,8 @@ body: |
; CHECK-LABEL: name: const_i32
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK-NEXT: RETURN [[C]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CONST_I32_]], implicit-def $arguments
%0:_(s32) = G_CONSTANT i32 4294967295
RETURN %0(s32), implicit-def $arguments
...
@@ -138,8 +138,8 @@ body: |
; CHECK-LABEL: name: const_i64
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: RETURN [[C]](s64), implicit-def $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 -1, implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CONST_I64_]], implicit-def $arguments
%0:_(s64) = G_CONSTANT i64 18446744073709551615
RETURN %0(s64), implicit-def $arguments
...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ctlz.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ctlz.mir
new file mode 100644
index 0000000000000..4074d5308e403
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ctlz.mir
@@ -0,0 +1,152 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: ctlz_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CLZ_I32_:%[0-9]+]]:i32 = CLZ_I32 [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 24, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SUB_I32_:%[0-9]+]]:i32 = nuw SUB_I32 [[CLZ_I32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SUB_I32_]], implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %1(s32)
+ %2:_(s8) = G_CTLZ %0
+ %3:_(s32) = G_ANYEXT %2(s8)
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: ctlz_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CLZ_I32_:%[0-9]+]]:i32 = CLZ_I32 [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 16, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SUB_I32_:%[0-9]+]]:i32 = nuw SUB_I32 [[CLZ_I32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SUB_I32_]], implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %1(s32)
+ %2:_(s16) = G_CTLZ %0
+ %3:_(s32) = G_ANYEXT %2(s16)
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: ctlz_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CLZ_I32_:%[0-9]+]]:i32 = CLZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CLZ_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_CTLZ %0
+ RETURN %1(s32), implicit-def $arguments
+
+...
+---
+name: ctlz_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CLZ_I32_:%[0-9]+]]:i32 = CLZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CLZ_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s8) = G_CTLZ %0
+ %2:_(s32) = G_ANYEXT %1(s8)
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: ctlz_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CLZ_I64_:%[0-9]+]]:i64 = CLZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CLZ_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_CTLZ %0
+ RETURN %1(s64), implicit-def $arguments
+
+...
+---
+name: ctlz_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CLZ_I64_:%[0-9]+]]:i64 = CLZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[CLZ_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s8) = G_CTLZ %0
+ %2:_(s32) = G_ANYEXT %1(s8)
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: ctlz_i64_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_i64_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CLZ_I64_:%[0-9]+]]:i64 = CLZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[CLZ_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s32) = G_CTLZ %0
+ RETURN %1(s32), implicit-def $arguments
+
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ctlz_zero_undef.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ctlz_zero_undef.mir
new file mode 100644
index 0000000000000..fe238329d0da4
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ctlz_zero_undef.mir
@@ -0,0 +1,152 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: ctlz_zundef_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_zundef_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CLZ_I32_:%[0-9]+]]:i32 = CLZ_I32 [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 24, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SUB_I32_:%[0-9]+]]:i32 = nuw SUB_I32 [[CLZ_I32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SUB_I32_]], implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %1(s32)
+ %2:_(s8) = G_CTLZ_ZERO_UNDEF %0
+ %3:_(s32) = G_ANYEXT %2(s8)
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: ctlz_zundef_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_zundef_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CLZ_I32_:%[0-9]+]]:i32 = CLZ_I32 [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 16, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SUB_I32_:%[0-9]+]]:i32 = nuw SUB_I32 [[CLZ_I32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SUB_I32_]], implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %1(s32)
+ %2:_(s16) = G_CTLZ_ZERO_UNDEF %0
+ %3:_(s32) = G_ANYEXT %2(s16)
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: ctlz_zundef_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_zundef_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CLZ_I32_:%[0-9]+]]:i32 = CLZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CLZ_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_CTLZ_ZERO_UNDEF %0
+ RETURN %1(s32), implicit-def $arguments
+
+...
+---
+name: ctlz_zundef_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_zundef_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CLZ_I32_:%[0-9]+]]:i32 = CLZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CLZ_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s8) = G_CTLZ_ZERO_UNDEF %0
+ %2:_(s32) = G_ANYEXT %1(s8)
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: ctlz_zundef_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_zundef_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CLZ_I64_:%[0-9]+]]:i64 = CLZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CLZ_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_CTLZ_ZERO_UNDEF %0
+ RETURN %1(s64), implicit-def $arguments
+
+...
+---
+name: ctlz_zundef_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_zundef_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CLZ_I64_:%[0-9]+]]:i64 = CLZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[CLZ_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s8) = G_CTLZ_ZERO_UNDEF %0
+ %2:_(s32) = G_ANYEXT %1(s8)
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: ctlz_zundef_i64_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctlz_zundef_i64_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CLZ_I64_:%[0-9]+]]:i64 = CLZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[CLZ_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s32) = G_CTLZ_ZERO_UNDEF %0
+ RETURN %1(s32), implicit-def $arguments
+
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ctpop.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ctpop.mir
similarity index 51%
rename from llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ctpop.mir
rename to llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ctpop.mir
index 3dcbd10b40447..7576ad6c567b0 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ctpop.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ctpop.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: ctpop_i8
@@ -12,11 +12,11 @@ body: |
; CHECK-LABEL: name: ctpop_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
- ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
- ; CHECK-NEXT: RETURN [[CTPOP]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[POPCNT_I32_:%[0-9]+]]:i32 = POPCNT_I32 [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[POPCNT_I32_]], implicit-def $arguments
%1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s8) = G_TRUNC %1(s32)
%2:_(s8) = G_CTPOP %0
@@ -35,11 +35,11 @@ body: |
; CHECK-LABEL: name: ctpop_i16
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
- ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
- ; CHECK-NEXT: RETURN [[CTPOP]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[POPCNT_I32_:%[0-9]+]]:i32 = POPCNT_I32 [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[POPCNT_I32_]], implicit-def $arguments
%1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s16) = G_TRUNC %1(s32)
%2:_(s16) = G_CTPOP %0
@@ -58,9 +58,9 @@ body: |
; CHECK-LABEL: name: ctpop_i32
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[CTPOP]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[POPCNT_I32_:%[0-9]+]]:i32 = POPCNT_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[POPCNT_I32_]], implicit-def $arguments
%0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%1:_(s32) = G_CTPOP %0
RETURN %1(s32), implicit-def $arguments
@@ -77,9 +77,9 @@ body: |
; CHECK-LABEL: name: ctpop_i32_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[CTPOP]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[POPCNT_I32_:%[0-9]+]]:i32 = POPCNT_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[POPCNT_I32_]], implicit-def $arguments
%0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%1:_(s8) = G_CTPOP %0
%2:_(s32) = G_ANYEXT %1(s8)
@@ -97,9 +97,9 @@ body: |
; CHECK-LABEL: name: ctpop_i64
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(s64) = G_CTPOP [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: RETURN [[CTPOP]](s64), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[POPCNT_I64_:%[0-9]+]]:i64 = POPCNT_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[POPCNT_I64_]], implicit-def $arguments
%0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
%1:_(s64) = G_CTPOP %0
RETURN %1(s64), implicit-def $arguments
@@ -116,10 +116,10 @@ body: |
; CHECK-LABEL: name: ctpop_i64_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(s64) = G_CTPOP [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTPOP]](s64)
- ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[POPCNT_I64_:%[0-9]+]]:i64 = POPCNT_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[POPCNT_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
%0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
%1:_(s8) = G_CTPOP %0
%2:_(s32) = G_ANYEXT %1(s8)
@@ -137,10 +137,10 @@ body: |
; CHECK-LABEL: name: ctpop_i64_i32
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(s64) = G_CTPOP [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTPOP]](s64)
- ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[POPCNT_I64_:%[0-9]+]]:i64 = POPCNT_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[POPCNT_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
%0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
%1:_(s32) = G_CTPOP %0
RETURN %1(s32), implicit-def $arguments
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/cttz.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/cttz.mir
similarity index 51%
rename from llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/cttz.mir
rename to llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/cttz.mir
index 2feeb10b39c38..7dc298f9dc402 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/cttz.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/cttz.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: cttz_i8
@@ -12,11 +12,11 @@ body: |
; CHECK-LABEL: name: cttz_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ARGUMENT_i32_]], [[C]]
- ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32)
- ; CHECK-NEXT: RETURN [[CTTZ]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 256, implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = OR_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CTZ_I32_:%[0-9]+]]:i32 = CTZ_I32 [[OR_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CTZ_I32_]], implicit-def $arguments
%1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s8) = G_TRUNC %1(s32)
%2:_(s8) = G_CTTZ %0
@@ -35,11 +35,11 @@ body: |
; CHECK-LABEL: name: cttz_i16
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ARGUMENT_i32_]], [[C]]
- ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32)
- ; CHECK-NEXT: RETURN [[CTTZ]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 65536, implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = OR_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CTZ_I32_:%[0-9]+]]:i32 = CTZ_I32 [[OR_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CTZ_I32_]], implicit-def $arguments
%1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s16) = G_TRUNC %1(s32)
%2:_(s16) = G_CTTZ %0
@@ -58,9 +58,9 @@ body: |
; CHECK-LABEL: name: cttz_i32
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[CTTZ]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CTZ_I32_:%[0-9]+]]:i32 = CTZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CTZ_I32_]], implicit-def $arguments
%0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%1:_(s32) = G_CTTZ %0
RETURN %1(s32), implicit-def $arguments
@@ -77,9 +77,9 @@ body: |
; CHECK-LABEL: name: cttz_i32_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[CTTZ]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CTZ_I32_:%[0-9]+]]:i32 = CTZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CTZ_I32_]], implicit-def $arguments
%0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%1:_(s8) = G_CTTZ %0
%2:_(s32) = G_ANYEXT %1(s8)
@@ -97,9 +97,9 @@ body: |
; CHECK-LABEL: name: cttz_i64
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s64) = G_CTTZ [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: RETURN [[CTTZ]](s64), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTZ_I64_:%[0-9]+]]:i64 = CTZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CTZ_I64_]], implicit-def $arguments
%0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
%1:_(s64) = G_CTTZ %0
RETURN %1(s64), implicit-def $arguments
@@ -116,10 +116,10 @@ body: |
; CHECK-LABEL: name: cttz_i64_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s64) = G_CTTZ [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTTZ]](s64)
- ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTZ_I64_:%[0-9]+]]:i64 = CTZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[CTZ_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
%0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
%1:_(s8) = G_CTTZ %0
%2:_(s32) = G_ANYEXT %1(s8)
@@ -137,10 +137,10 @@ body: |
; CHECK-LABEL: name: cttz_i64_i32
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s64) = G_CTTZ [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTTZ]](s64)
- ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTZ_I64_:%[0-9]+]]:i64 = CTZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[CTZ_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
%0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
%1:_(s32) = G_CTTZ %0
RETURN %1(s32), implicit-def $arguments
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/cttz_zero_undef.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/cttz_zero_undef.mir
similarity index 53%
rename from llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/cttz_zero_undef.mir
rename to llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/cttz_zero_undef.mir
index b76234b48fe10..367d595e88b19 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/cttz_zero_undef.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/cttz_zero_undef.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: cttz_zundef_i8
@@ -12,11 +12,11 @@ body: |
; CHECK-LABEL: name: cttz_zundef_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ARGUMENT_i32_]], [[C]]
- ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32)
- ; CHECK-NEXT: RETURN [[CTTZ]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 256, implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = OR_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CTZ_I32_:%[0-9]+]]:i32 = CTZ_I32 [[OR_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CTZ_I32_]], implicit-def $arguments
%1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s8) = G_TRUNC %1(s32)
%2:_(s8) = G_CTTZ_ZERO_UNDEF %0
@@ -35,11 +35,11 @@ body: |
; CHECK-LABEL: name: cttz_zundef_i16
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ARGUMENT_i32_]], [[C]]
- ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32)
- ; CHECK-NEXT: RETURN [[CTTZ]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 65536, implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = OR_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CTZ_I32_:%[0-9]+]]:i32 = CTZ_I32 [[OR_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CTZ_I32_]], implicit-def $arguments
%1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s16) = G_TRUNC %1(s32)
%2:_(s16) = G_CTTZ_ZERO_UNDEF %0
@@ -58,9 +58,9 @@ body: |
; CHECK-LABEL: name: cttz_zundef_i32
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[CTTZ]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CTZ_I32_:%[0-9]+]]:i32 = CTZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CTZ_I32_]], implicit-def $arguments
%0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%1:_(s32) = G_CTTZ_ZERO_UNDEF %0
RETURN %1(s32), implicit-def $arguments
@@ -77,9 +77,9 @@ body: |
; CHECK-LABEL: name: cttz_zundef_i32_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[CTTZ]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CTZ_I32_:%[0-9]+]]:i32 = CTZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CTZ_I32_]], implicit-def $arguments
%0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%1:_(s8) = G_CTTZ_ZERO_UNDEF %0
%2:_(s32) = G_ANYEXT %1(s8)
@@ -97,9 +97,9 @@ body: |
; CHECK-LABEL: name: cttz_zundef_i64
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s64) = G_CTTZ [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: RETURN [[CTTZ]](s64), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTZ_I64_:%[0-9]+]]:i64 = CTZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CTZ_I64_]], implicit-def $arguments
%0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
%1:_(s64) = G_CTTZ_ZERO_UNDEF %0
RETURN %1(s64), implicit-def $arguments
@@ -116,10 +116,10 @@ body: |
; CHECK-LABEL: name: cttz_zundef_i64_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s64) = G_CTTZ [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTTZ]](s64)
- ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTZ_I64_:%[0-9]+]]:i64 = CTZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[CTZ_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
%0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
%1:_(s8) = G_CTTZ_ZERO_UNDEF %0
%2:_(s32) = G_ANYEXT %1(s8)
@@ -137,10 +137,10 @@ body: |
; CHECK-LABEL: name: cttz_zundef_i64_i32
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:_(s64) = G_CTTZ [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTTZ]](s64)
- ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTZ_I64_:%[0-9]+]]:i64 = CTZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[CTZ_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
%0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
%1:_(s32) = G_CTTZ_ZERO_UNDEF %0
RETURN %1(s32), implicit-def $arguments
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/fshl.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/fshl.mir
new file mode 100644
index 0000000000000..898711486f132
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/fshl.mir
@@ -0,0 +1,382 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: fshl_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshl_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 5, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 3, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_2:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_CONSTANT i8 5
+ %5:_(s8) = G_FSHL %0, %1, %4(s8)
+ %6:_(s32) = G_ANYEXT %5(s8)
+ RETURN %6(s32), implicit-def $arguments
+
+...
+---
+name: fshlv_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshlv_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32 = ARGUMENT_i32 2, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 7, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_2]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_2]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[XOR_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_2:%[0-9]+]]:i32 = CONST_I32 1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_3:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_2:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_3]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_2]], [[CONST_I32_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_4:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_3:%[0-9]+]]:i32 = AND_I32 [[SHR_U_I32_]], [[CONST_I32_4]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_1:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_3]], [[AND_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %3:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %3(s32)
+ %4:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %4(s32)
+ %5:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ %2:_(s8) = G_TRUNC %5(s32)
+ %6:_(s8) = G_FSHL %0, %1, %2(s8)
+ %7:_(s32) = G_ANYEXT %6(s8)
+ RETURN %7(s32), implicit-def $arguments
+
+...
+---
+name: fshl_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshl_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 13, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 3, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_2:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_CONSTANT i16 13
+ %5:_(s16) = G_FSHL %0, %1, %4(s16)
+ %6:_(s32) = G_ANYEXT %5(s16)
+ RETURN %6(s32), implicit-def $arguments
+
+...
+---
+name: fshlv_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshlv_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32 = ARGUMENT_i32 2, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 15, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_2]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_2]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[XOR_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_2:%[0-9]+]]:i32 = CONST_I32 1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_3:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_2:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_3]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_2]], [[CONST_I32_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_4:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_3:%[0-9]+]]:i32 = AND_I32 [[SHR_U_I32_]], [[CONST_I32_4]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_1:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_3]], [[AND_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %3:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %3(s32)
+ %4:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %4(s32)
+ %5:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ %2:_(s16) = G_TRUNC %5(s32)
+ %6:_(s16) = G_FSHL %0, %1, %2(s16)
+ %7:_(s32) = G_ANYEXT %6(s16)
+ RETURN %7(s32), implicit-def $arguments
+
+...
+---
+name: fshl_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshl_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 11, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_CONSTANT i32 21
+ %3:_(s32) = G_FSHL %0, %1, %2(s32)
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: fshlv_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshlv_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32 = ARGUMENT_i32 2, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_2]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_1:%[0-9]+]]:i32 = SHR_U_I32 [[SHR_U_I32_]], [[XOR_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ %3:_(s32) = G_FSHL %0, %1, %2(s32)
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: fshl_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshl_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 11, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s8) = G_CONSTANT i8 21
+ %3:_(s32) = G_FSHL %0, %1, %2(s8)
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: fshlv_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshlv_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32 = ARGUMENT_i32 2, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_2]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_1:%[0-9]+]]:i32 = SHR_U_I32 [[SHR_U_I32_]], [[XOR_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %3:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ %2:_(s8) = G_TRUNC %3(s32)
+ %4:_(s32) = G_FSHL %0, %1, %2(s8)
+ RETURN %4(s32), implicit-def $arguments
+
+...
+---
+name: fshl_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshl_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 27, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[CONST_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = disjoint OR_I64 [[SHL_I64_]], [[SHR_U_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_CONSTANT i64 37
+ %3:_(s64) = G_FSHL %0, %1, %2(s64)
+ RETURN %3(s64), implicit-def $arguments
+
+...
+---
+name: fshlv_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshlv_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_2:%[0-9]+]]:i64 = ARGUMENT_i64 2, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 -1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[XOR_I64_:%[0-9]+]]:i64 = XOR_I64 [[ARGUMENT_i64_2]], [[CONST_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[CONST_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_1:%[0-9]+]]:i64 = SHR_U_I64 [[SHR_U_I64_]], [[XOR_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = disjoint OR_I64 [[SHL_I64_]], [[SHR_U_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:i64(s64) = ARGUMENT_i64 2, implicit $arguments
+ %3:_(s64) = G_FSHL %0, %1, %2(s64)
+ RETURN %3(s64), implicit-def $arguments
+
+...
+---
+name: fshl_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshl_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 21, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_]], [[CONST_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_2:%[0-9]+]]:i64 = CONST_I64 43, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_3:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_1:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_2]], [[CONST_I64_3]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[AND_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = disjoint OR_I64 [[SHL_I64_]], [[SHR_U_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s8) = G_CONSTANT i8 21
+ %3:_(s64) = G_FSHL %0, %1, %2(s8)
+ RETURN %3(s64), implicit-def $arguments
+
+...
+---
+name: fshlv_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshlv_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 2, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 63, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[XOR_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_2:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_1:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_1]], [[CONST_I64_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[AND_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[I64_EXTEND_U_I32_1:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[AND_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_3:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_2:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_1]], [[CONST_I64_3]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_1:%[0-9]+]]:i64 = SHR_U_I64 [[SHR_U_I64_]], [[AND_I64_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = disjoint OR_I64 [[SHL_I64_]], [[SHR_U_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %3:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ %2:_(s8) = G_TRUNC %3(s32)
+ %4:_(s64) = G_FSHL %0, %1, %2(s8)
+ RETURN %4(s64), implicit-def $arguments
+
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/fshr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/fshr.mir
new file mode 100644
index 0000000000000..4684532699357
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/fshr.mir
@@ -0,0 +1,378 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: fshr_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshr_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 5, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 3, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_2:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_CONSTANT i8 5
+ %5:_(s8) = G_FSHR %0, %1, %4(s8)
+ %6:_(s32) = G_ANYEXT %5(s8)
+ RETURN %6(s32), implicit-def $arguments
+
+...
+---
+name: fshrv_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshrv_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32 = ARGUMENT_i32 2, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 7, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_2]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_2]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[XOR_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_2:%[0-9]+]]:i32 = CONST_I32 1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_1:%[0-9]+]]:i32 = SHL_I32 [[SHL_I32_]], [[AND_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_3:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_2:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_3]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_2]], [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_1]], [[SHR_U_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %3:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %3(s32)
+ %4:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %4(s32)
+ %5:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ %2:_(s8) = G_TRUNC %5(s32)
+ %6:_(s8) = G_FSHR %0, %1, %2(s8)
+ %7:_(s32) = G_ANYEXT %6(s8)
+ RETURN %7(s32), implicit-def $arguments
+
+...
+---
+name: fshr_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshr_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 13, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 3, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_2:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_CONSTANT i16 13
+ %5:_(s16) = G_FSHR %0, %1, %4(s16)
+ %6:_(s32) = G_ANYEXT %5(s16)
+ RETURN %6(s32), implicit-def $arguments
+
+...
+---
+name: fshrv_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshrv_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32 = ARGUMENT_i32 2, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 15, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_2]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_2]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[XOR_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_2:%[0-9]+]]:i32 = CONST_I32 1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_1:%[0-9]+]]:i32 = SHL_I32 [[SHL_I32_]], [[AND_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_3:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_2:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_3]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_2]], [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_1]], [[SHR_U_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %3:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %3(s32)
+ %4:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %4(s32)
+ %5:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ %2:_(s16) = G_TRUNC %5(s32)
+ %6:_(s16) = G_FSHR %0, %1, %2(s16)
+ %7:_(s32) = G_ANYEXT %6(s16)
+ RETURN %7(s32), implicit-def $arguments
+
+...
+---
+name: fshr_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshr_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 11, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_1]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_CONSTANT i32 21
+ %3:_(s32) = G_FSHR %0, %1, %2(s32)
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: fshrv_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshrv_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32 = ARGUMENT_i32 2, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_2]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_1:%[0-9]+]]:i32 = SHL_I32 [[SHL_I32_]], [[XOR_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_1]], [[SHR_U_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ %3:_(s32) = G_FSHR %0, %1, %2(s32)
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: fshr_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshr_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 11, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_1]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s8) = G_CONSTANT i8 21
+ %3:_(s32) = G_FSHR %0, %1, %2(s8)
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: fshrv_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshrv_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32 = ARGUMENT_i32 2, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_2]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_1:%[0-9]+]]:i32 = SHL_I32 [[SHL_I32_]], [[XOR_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_1]], [[SHR_U_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %3:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ %2:_(s8) = G_TRUNC %3(s32)
+ %4:_(s32) = G_FSHR %0, %1, %2(s8)
+ RETURN %4(s32), implicit-def $arguments
+
+...
+---
+name: fshr_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshr_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 27, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[CONST_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[CONST_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = disjoint OR_I64 [[SHL_I64_]], [[SHR_U_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_CONSTANT i64 37
+ %3:_(s64) = G_FSHR %0, %1, %2(s64)
+ RETURN %3(s64), implicit-def $arguments
+
+...
+---
+name: fshrv_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshrv_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_2:%[0-9]+]]:i64 = ARGUMENT_i64 2, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 -1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[XOR_I64_:%[0-9]+]]:i64 = XOR_I64 [[ARGUMENT_i64_2]], [[CONST_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[CONST_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_1:%[0-9]+]]:i64 = SHL_I64 [[SHL_I64_]], [[XOR_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[ARGUMENT_i64_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = disjoint OR_I64 [[SHL_I64_1]], [[SHR_U_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:i64(s64) = ARGUMENT_i64 2, implicit $arguments
+ %3:_(s64) = G_FSHR %0, %1, %2(s64)
+ RETURN %3(s64), implicit-def $arguments
+
+...
+---
+name: fshr_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshr_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 43, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_]], [[CONST_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_2:%[0-9]+]]:i64 = CONST_I64 21, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_3:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_1:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_2]], [[CONST_I64_3]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[AND_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = disjoint OR_I64 [[SHL_I64_]], [[SHR_U_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s8) = G_CONSTANT i8 21
+ %3:_(s64) = G_FSHR %0, %1, %2(s8)
+ RETURN %3(s64), implicit-def $arguments
+
+...
+---
+name: fshrv_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshrv_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 2, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 63, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[XOR_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_]], [[CONST_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[AND_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_2:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_1:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_1:%[0-9]+]]:i64 = SHL_I64 [[SHL_I64_]], [[AND_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[I64_EXTEND_U_I32_1:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_3:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_2:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_1]], [[CONST_I64_3]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[AND_I64_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = disjoint OR_I64 [[SHL_I64_1]], [[SHR_U_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %3:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ %2:_(s8) = G_TRUNC %3(s32)
+ %4:_(s64) = G_FSHR %0, %1, %2(s8)
+ RETURN %4(s64), implicit-def $arguments
+
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/implicit_def.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/implicit_def.mir
similarity index 73%
rename from llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/implicit_def.mir
rename to llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/implicit_def.mir
index 4b6685214a963..579087e7ec3f4 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/implicit_def.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/implicit_def.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: implicit_def_i8
@@ -12,8 +12,8 @@ body: |
; CHECK-LABEL: name: implicit_def_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: RETURN [[DEF]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:i32 = IMPLICIT_DEF
+ ; CHECK-NEXT: RETURN [[DEF]], implicit-def $arguments
%0:_(s8) = G_IMPLICIT_DEF
%1:_(s32) = G_ANYEXT %0(s8)
RETURN %1(s32), implicit-def $arguments
@@ -30,8 +30,8 @@ body: |
; CHECK-LABEL: name: implicit_def_i16
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: RETURN [[DEF]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:i32 = IMPLICIT_DEF
+ ; CHECK-NEXT: RETURN [[DEF]], implicit-def $arguments
%0:_(s16) = G_IMPLICIT_DEF
%1:_(s32) = G_ANYEXT %0(s16)
RETURN %1(s32), implicit-def $arguments
@@ -48,8 +48,8 @@ body: |
; CHECK-LABEL: name: implicit_def_i32
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: RETURN [[DEF]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:i32 = IMPLICIT_DEF
+ ; CHECK-NEXT: RETURN [[DEF]], implicit-def $arguments
%0:_(s32) = G_IMPLICIT_DEF
RETURN %0(s32), implicit-def $arguments
...
@@ -65,8 +65,8 @@ body: |
; CHECK-LABEL: name: implicit_def_i64
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; CHECK-NEXT: RETURN [[DEF]](s64), implicit-def $arguments
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:i64 = IMPLICIT_DEF
+ ; CHECK-NEXT: RETURN [[DEF]], implicit-def $arguments
%0:_(s64) = G_IMPLICIT_DEF
RETURN %0(s64), implicit-def $arguments
...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/lshr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/lshr.mir
new file mode 100644
index 0000000000000..c7905072acf67
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/lshr.mir
@@ -0,0 +1,286 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: lshr_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshr_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 5, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_U_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %1:_(s8) = G_CONSTANT i8 5
+ %3:_(s8) = G_LSHR %0, %1
+ %4:_(s32) = G_ANYEXT %3(s8)
+ RETURN %4(s32), implicit-def $arguments
+
+...
+---
+name: lshrv_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshrv_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_]], [[AND_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_U_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_LSHR %0, %1
+ %5:_(s32) = G_ANYEXT %4(s8)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: lshr_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshr_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 13, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_U_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %1:_(s16) = G_CONSTANT i16 13
+ %3:_(s16) = G_LSHR %0, %1
+ %4:_(s32) = G_ANYEXT %3(s16)
+ RETURN %4(s32), implicit-def $arguments
+
+...
+---
+name: lshrv_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshrv_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_]], [[AND_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_U_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_LSHR %0, %1
+ %5:_(s32) = G_ANYEXT %4(s16)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: lshr_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshr_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_U_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_CONSTANT i32 21
+ %2:_(s32) = G_LSHR %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: lshrv_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshrv_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_U_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_LSHR %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: lshr_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshr_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_U_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s8) = G_CONSTANT i8 21
+ %2:_(s32) = G_LSHR %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: lshrv_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshrv_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_]], [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_U_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %2(s32)
+ %3:_(s32) = G_LSHR %0, %1
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: lshr_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshr_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_U_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_CONSTANT i64 37
+ %2:_(s64) = G_LSHR %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: lshrv_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshrv_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_U_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_LSHR %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: lshr_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshr_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_]], [[CONST_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_U_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s8) = G_CONSTANT i8 37
+ %2:_(s64) = G_LSHR %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: lshrv_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshrv_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_U_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %2(s32)
+ %3:_(s64) = G_LSHR %0, %1
+ RETURN %3(s64), implicit-def $arguments
+
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/mul.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/mul.mir
similarity index 55%
rename from llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/mul.mir
rename to llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/mul.mir
index 537d8f9fcf52d..a690750c25d28 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/mul.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/mul.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: mul_i8
@@ -12,11 +12,10 @@ body: |
; CHECK-LABEL: name: mul_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[MUL]](s32)
- ; CHECK-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[MUL_I32_:%[0-9]+]]:i32 = MUL_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[MUL_I32_]], implicit-def $arguments
%2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s8) = G_TRUNC %2(s32)
%3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
@@ -36,11 +35,10 @@ body: |
; CHECK-LABEL: name: mul_i16
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[MUL]](s32)
- ; CHECK-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[MUL_I32_:%[0-9]+]]:i32 = MUL_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[MUL_I32_]], implicit-def $arguments
%2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s16) = G_TRUNC %2(s32)
%3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
@@ -60,10 +58,10 @@ body: |
; CHECK-LABEL: name: mul_i32
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: RETURN [[MUL]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[MUL_I32_:%[0-9]+]]:i32 = MUL_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[MUL_I32_]], implicit-def $arguments
%0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
%2:_(s32) = G_MUL %0, %1
@@ -80,10 +78,10 @@ body: |
; CHECK-LABEL: name: mul_i64
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
- ; CHECK-NEXT: RETURN [[MUL]](s64), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[MUL_I64_:%[0-9]+]]:i64 = MUL_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[MUL_I64_]], implicit-def $arguments
%0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
%1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
%2:_(s64) = G_MUL %0, %1
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/or.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/or.mir
similarity index 55%
rename from llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/or.mir
rename to llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/or.mir
index d86bd04d2e455..fbb3f5e507a95 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/or.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/or.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: or_i1
@@ -12,10 +12,10 @@ body: |
; CHECK-LABEL: name: or_i1
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = OR_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
%2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s1) = G_TRUNC %2(s32)
%3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
@@ -36,10 +36,10 @@ body: |
; CHECK-LABEL: name: or_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = OR_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
%2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s8) = G_TRUNC %2(s32)
%3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
@@ -60,10 +60,10 @@ body: |
; CHECK-LABEL: name: or_i16
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = OR_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
%2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s16) = G_TRUNC %2(s32)
%3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
@@ -84,10 +84,10 @@ body: |
; CHECK-LABEL: name: or_i32
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = OR_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
%0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
%2:_(s32) = G_OR %1, %0
@@ -105,10 +105,10 @@ body: |
; CHECK-LABEL: name: or_i64
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ARGUMENT_i64_1]], [[ARGUMENT_i64_]]
- ; CHECK-NEXT: RETURN [[OR]](s64), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = OR_I64 [[ARGUMENT_i64_1]], [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
%0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
%1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
%2:_(s64) = G_OR %1, %0
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/rotl.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/rotl.mir
new file mode 100644
index 0000000000000..4166c01a404cc
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/rotl.mir
@@ -0,0 +1,303 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+
+---
+name: rotl_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotl_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 5, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 3, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_2:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %1:_(s8) = G_CONSTANT i8 5
+ %3:_(s8) = G_ROTL %0, %1
+ %4:_(s32) = G_ANYEXT %3(s8)
+ RETURN %4(s32), implicit-def $arguments
+
+...
+---
+name: rotlv_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotlv_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 0, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 7, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SUB_I32_:%[0-9]+]]:i32 = SUB_I32 [[CONST_I32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[SUB_I32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_2:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_2:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_2]], [[AND_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_ROTL %0, %1
+ %5:_(s32) = G_ANYEXT %4(s8)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: rotl_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotl_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 13, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 3, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_2:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %1:_(s16) = G_CONSTANT i16 13
+ %3:_(s16) = G_ROTL %0, %1
+ %4:_(s32) = G_ANYEXT %3(s16)
+ RETURN %4(s32), implicit-def $arguments
+
+...
+---
+name: rotlv_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotlv_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 0, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 15, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SUB_I32_:%[0-9]+]]:i32 = SUB_I32 [[CONST_I32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[SUB_I32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_2:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_2:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_2]], [[AND_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_ROTL %0, %1
+ %5:_(s32) = G_ANYEXT %4(s16)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: rotl_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotl_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
+ ; CHECK-NEXT: [[ROTL_I32_:%[0-9]+]]:i32 = ROTL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[ROTL_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_CONSTANT i32 21
+ %2:_(s32) = G_ROTL %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: rotlv_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotlv_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ROTL_I32_:%[0-9]+]]:i32 = ROTL_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[ROTL_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_ROTL %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: rotl_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotl_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
+ ; CHECK-NEXT: [[ROTL_I32_:%[0-9]+]]:i32 = ROTL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[ROTL_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s8) = G_CONSTANT i8 21
+ %2:_(s32) = G_ROTL %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: rotlv_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotlv_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[ROTL_I32_:%[0-9]+]]:i32 = ROTL_I32 [[ARGUMENT_i32_]], [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[ROTL_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %2(s32)
+ %3:_(s32) = G_ROTL %0, %1
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: rotl_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotl_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
+ ; CHECK-NEXT: [[ROTL_I64_:%[0-9]+]]:i64 = ROTL_I64 [[ARGUMENT_i64_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[ROTL_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_CONSTANT i64 37
+ %2:_(s64) = G_ROTL %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: rotlv_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotlv_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[ROTL_I64_:%[0-9]+]]:i64 = ROTL_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[ROTL_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_ROTL %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: rotl_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotl_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_]], [[CONST_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[ROTL_I64_:%[0-9]+]]:i64 = ROTL_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[ROTL_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s8) = G_CONSTANT i8 37
+ %2:_(s64) = G_ROTL %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: rotlv_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotlv_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[ROTL_I64_:%[0-9]+]]:i64 = ROTL_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[ROTL_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %2(s32)
+ %3:_(s64) = G_ROTL %0, %1
+ RETURN %3(s64), implicit-def $arguments
+
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/rotr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/rotr.mir
new file mode 100644
index 0000000000000..f08ae2a04544c
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/rotr.mir
@@ -0,0 +1,303 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+
+---
+name: rotr_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotr_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 5, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_2:%[0-9]+]]:i32 = CONST_I32 3, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHR_U_I32_]], [[SHL_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %1:_(s8) = G_CONSTANT i8 5
+ %3:_(s8) = G_ROTR %0, %1
+ %4:_(s32) = G_ANYEXT %3(s8)
+ RETURN %4(s32), implicit-def $arguments
+
+...
+---
+name: rotrv_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotrv_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 0, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 7, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SUB_I32_:%[0-9]+]]:i32 = SUB_I32 [[CONST_I32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_2:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_1]], [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_2:%[0-9]+]]:i32 = AND_I32 [[SUB_I32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[AND_I32_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHR_U_I32_]], [[SHL_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_ROTR %0, %1
+ %5:_(s32) = G_ANYEXT %4(s8)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: rotr_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotr_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 13, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_2:%[0-9]+]]:i32 = CONST_I32 3, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHR_U_I32_]], [[SHL_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %1:_(s16) = G_CONSTANT i16 13
+ %3:_(s16) = G_ROTR %0, %1
+ %4:_(s32) = G_ANYEXT %3(s16)
+ RETURN %4(s32), implicit-def $arguments
+
+...
+---
+name: rotrv_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotrv_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 0, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 15, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SUB_I32_:%[0-9]+]]:i32 = SUB_I32 [[CONST_I32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_2:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_1]], [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_2:%[0-9]+]]:i32 = AND_I32 [[SUB_I32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[AND_I32_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHR_U_I32_]], [[SHL_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_ROTR %0, %1
+ %5:_(s32) = G_ANYEXT %4(s16)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: rotr_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotr_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
+ ; CHECK-NEXT: [[ROTR_I32_:%[0-9]+]]:i32 = ROTR_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[ROTR_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_CONSTANT i32 21
+ %2:_(s32) = G_ROTR %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: rotrv_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotrv_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ROTR_I32_:%[0-9]+]]:i32 = ROTR_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[ROTR_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_ROTR %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: rotr_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotr_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
+ ; CHECK-NEXT: [[ROTR_I32_:%[0-9]+]]:i32 = ROTR_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[ROTR_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s8) = G_CONSTANT i8 21
+ %2:_(s32) = G_ROTR %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: rotrv_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotrv_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[ROTR_I32_:%[0-9]+]]:i32 = ROTR_I32 [[ARGUMENT_i32_]], [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[ROTR_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %2(s32)
+ %3:_(s32) = G_ROTR %0, %1
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: rotr_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotr_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
+ ; CHECK-NEXT: [[ROTR_I64_:%[0-9]+]]:i64 = ROTR_I64 [[ARGUMENT_i64_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[ROTR_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_CONSTANT i64 37
+ %2:_(s64) = G_ROTR %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: rotrv_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotrv_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[ROTR_I64_:%[0-9]+]]:i64 = ROTR_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[ROTR_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_ROTR %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: rotr_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotr_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_]], [[CONST_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[ROTR_I64_:%[0-9]+]]:i64 = ROTR_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[ROTR_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s8) = G_CONSTANT i8 37
+ %2:_(s64) = G_ROTR %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: rotrv_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: rotrv_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[ROTR_I64_:%[0-9]+]]:i64 = ROTR_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[ROTR_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %2(s32)
+ %3:_(s64) = G_ROTR %0, %1
+ RETURN %3(s64), implicit-def $arguments
+
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sdiv.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sdiv.mir
new file mode 100644
index 0000000000000..0806622b99192
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sdiv.mir
@@ -0,0 +1,122 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=-sign-ext -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NO-SIGNEXT
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=+sign-ext -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,SIGNEXT
+
+---
+name: sdiv_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: sdiv_i8
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 24, implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 24, implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHL_I32_1:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHR_S_I32_1:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_1]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[DIV_S_I32_:%[0-9]+]]:i32 = DIV_S_I32 [[SHR_S_I32_]], [[SHR_S_I32_1]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: RETURN [[DIV_S_I32_]], implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: sdiv_i8
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; SIGNEXT-NEXT: [[I32_EXTEND8_S_I32_:%[0-9]+]]:i32 = I32_EXTEND8_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: [[I32_EXTEND8_S_I32_1:%[0-9]+]]:i32 = I32_EXTEND8_S_I32 [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: [[DIV_S_I32_:%[0-9]+]]:i32 = DIV_S_I32 [[I32_EXTEND8_S_I32_]], [[I32_EXTEND8_S_I32_1]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: RETURN [[DIV_S_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_SDIV %0, %1
+ %5:i32(s32) = G_ANYEXT %4(s8)
+ RETURN %5(s32), implicit-def $arguments
+...
+---
+name: sdiv_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: sdiv_i16
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 16, implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 16, implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHL_I32_1:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHR_S_I32_1:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_1]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[DIV_S_I32_:%[0-9]+]]:i32 = DIV_S_I32 [[SHR_S_I32_]], [[SHR_S_I32_1]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: RETURN [[DIV_S_I32_]], implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: sdiv_i16
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; SIGNEXT-NEXT: [[I32_EXTEND16_S_I32_:%[0-9]+]]:i32 = I32_EXTEND16_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: [[I32_EXTEND16_S_I32_1:%[0-9]+]]:i32 = I32_EXTEND16_S_I32 [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: [[DIV_S_I32_:%[0-9]+]]:i32 = DIV_S_I32 [[I32_EXTEND16_S_I32_]], [[I32_EXTEND16_S_I32_1]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: RETURN [[DIV_S_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_SDIV %0, %1
+ %5:i32(s32) = G_ANYEXT %4(s16)
+ RETURN %5(s32), implicit-def $arguments
+...
+---
+name: sdiv_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sdiv_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[DIV_S_I32_:%[0-9]+]]:i32 = DIV_S_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[DIV_S_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_SDIV %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: sdiv_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sdiv_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[DIV_S_I64_:%[0-9]+]]:i64 = DIV_S_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[DIV_S_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_SDIV %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sext.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sext.mir
new file mode 100644
index 0000000000000..8c8e58b5e4a46
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sext.mir
@@ -0,0 +1,138 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=-sign-ext -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NO-SIGNEXT
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=+sign-ext -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,SIGNEXT
+
+---
+name: sext_i8_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: sext_i8_i32
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 24, implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: sext_i8_i32
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[I32_EXTEND8_S_I32_:%[0-9]+]]:i32 = I32_EXTEND8_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: RETURN [[I32_EXTEND8_S_I32_]], implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %1(s32)
+ %2:i32(s32) = G_SEXT %0(s8)
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: sext_i8_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: sext_i8_i64
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 56, implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHR_S_I64_:%[0-9]+]]:i64 = SHR_S_I64 [[SHL_I64_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I64_]], implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: sext_i8_i64
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: [[I64_EXTEND8_S_I64_:%[0-9]+]]:i64 = I64_EXTEND8_S_I64 [[I64_EXTEND_U_I32_]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: RETURN [[I64_EXTEND8_S_I64_]], implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %1(s32)
+ %2:i64(s64) = G_SEXT %0(s8)
+ RETURN %2(s64), implicit-def $arguments
+...
+---
+name: sext_i16_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: sext_i16_i32
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 16, implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: sext_i16_i32
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[I32_EXTEND16_S_I32_:%[0-9]+]]:i32 = I32_EXTEND16_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: RETURN [[I32_EXTEND16_S_I32_]], implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %1(s32)
+ %2:i32(s32) = G_SEXT %0(s16)
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: sext_i16_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: sext_i16_i64
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 48, implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHR_S_I64_:%[0-9]+]]:i64 = SHR_S_I64 [[SHL_I64_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I64_]], implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: sext_i16_i64
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: [[I64_EXTEND16_S_I64_:%[0-9]+]]:i64 = I64_EXTEND16_S_I64 [[I64_EXTEND_U_I32_]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: RETURN [[I64_EXTEND16_S_I64_]], implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %1(s32)
+ %2:i64(s64) = G_SEXT %0(s16)
+ RETURN %2(s64), implicit-def $arguments
+...
+---
+name: sext_i32_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sext_i32_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[I64_EXTEND_S_I32_:%[0-9]+]]:i64 = I64_EXTEND_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I64_EXTEND_S_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i64(s64) = G_SEXT %0(s32)
+ RETURN %1(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sext_inreg.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sext_inreg.mir
new file mode 100644
index 0000000000000..b9d904ae3f7a9
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sext_inreg.mir
@@ -0,0 +1,181 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=-sign-ext -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NO-SIGNEXT
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=+sign-ext -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,SIGNEXT
+
+---
+name: sext_inreg_i1_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sext_inreg_i1_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 31, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 %1, [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_SEXT_INREG %1(s32), 1
+ RETURN %1(s32), implicit-def $arguments
+...
+---
+name: sext_inreg_i8_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: sext_inreg_i8_i32
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 24, implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 %1, [[CONST_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: sext_inreg_i8_i32
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[I32_EXTEND8_S_I32_:%[0-9]+]]:i32 = I32_EXTEND8_S_I32 [[I32_EXTEND8_S_I32_]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: RETURN [[I32_EXTEND8_S_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_SEXT_INREG %1(s32), 8
+ RETURN %1(s32), implicit-def $arguments
+...
+---
+name: sext_inreg_i16_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: sext_inreg_i16_i32
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 16, implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 %1, [[CONST_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: sext_inreg_i16_i32
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[I32_EXTEND16_S_I32_:%[0-9]+]]:i32 = I32_EXTEND16_S_I32 [[I32_EXTEND16_S_I32_]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: RETURN [[I32_EXTEND16_S_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_SEXT_INREG %1(s32), 16
+ RETURN %1(s32), implicit-def $arguments
+...
+
+---
+name: sext_inreg_i1_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: sext_inreg_i1_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 63, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 %1, [[CONST_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_S_I64_:%[0-9]+]]:i64 = SHR_S_I64 [[SHL_I64_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_S_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_SEXT_INREG %1(s64), 1
+ RETURN %1(s64), implicit-def $arguments
+...
+---
+name: sext_inreg_i8_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: sext_inreg_i8_i64
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 56, implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 %1, [[CONST_I64_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHR_S_I64_:%[0-9]+]]:i64 = SHR_S_I64 [[SHL_I64_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I64_]], implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: sext_inreg_i8_i64
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[I64_EXTEND8_S_I64_:%[0-9]+]]:i64 = I64_EXTEND8_S_I64 [[I64_EXTEND8_S_I64_]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: RETURN [[I64_EXTEND8_S_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_SEXT_INREG %1(s64), 8
+ RETURN %1(s64), implicit-def $arguments
+...
+---
+name: sext_inreg_i16_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: sext_inreg_i16_i64
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 48, implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 %1, [[CONST_I64_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHR_S_I64_:%[0-9]+]]:i64 = SHR_S_I64 [[SHL_I64_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I64_]], implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: sext_inreg_i16_i64
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[I64_EXTEND16_S_I64_:%[0-9]+]]:i64 = I64_EXTEND16_S_I64 [[I64_EXTEND16_S_I64_]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: RETURN [[I64_EXTEND16_S_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_SEXT_INREG %1(s64), 16
+ RETURN %1(s64), implicit-def $arguments
+...
+
+---
+name: sext_inreg_i32_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: sext_inreg_i32_i64
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 32, implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 %1, [[CONST_I64_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHR_S_I64_:%[0-9]+]]:i64 = SHR_S_I64 [[SHL_I64_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I64_]], implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: sext_inreg_i32_i64
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[I64_EXTEND32_S_I64_:%[0-9]+]]:i64 = I64_EXTEND32_S_I64 [[I64_EXTEND32_S_I64_]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: RETURN [[I64_EXTEND32_S_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_SEXT_INREG %1(s64), 32
+ RETURN %1(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/shl.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/shl.mir
new file mode 100644
index 0000000000000..c61312d799163
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/shl.mir
@@ -0,0 +1,278 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: shl_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shl_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 5, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHL_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %1:_(s8) = G_CONSTANT i8 5
+ %3:_(s8) = G_SHL %0, %1
+ %4:_(s32) = G_ANYEXT %3(s8)
+ RETURN %4(s32), implicit-def $arguments
+
+...
+---
+name: shlv_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shlv_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHL_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_SHL %0, %1
+ %5:_(s32) = G_ANYEXT %4(s8)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: shl_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shl_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 13, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHL_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %1:_(s16) = G_CONSTANT i16 13
+ %3:_(s16) = G_SHL %0, %1
+ %4:_(s32) = G_ANYEXT %3(s16)
+ RETURN %4(s32), implicit-def $arguments
+
+...
+---
+name: shlv_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shlv_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHL_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_SHL %0, %1
+ %5:_(s32) = G_ANYEXT %4(s16)
+ RETURN %5(s32), implicit-def $arguments
+
+...
+---
+name: shl_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shl_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHL_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s32) = G_CONSTANT i32 21
+ %2:_(s32) = G_SHL %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: shlv_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shlv_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHL_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_SHL %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: shl_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shl_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHL_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s8) = G_CONSTANT i8 21
+ %2:_(s32) = G_SHL %0, %1
+ RETURN %2(s32), implicit-def $arguments
+
+...
+---
+name: shlv_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shlv_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHL_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %2(s32)
+ %3:_(s32) = G_SHL %0, %1
+ RETURN %3(s32), implicit-def $arguments
+
+...
+---
+name: shl_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shl_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHL_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s64) = G_CONSTANT i64 37
+ %2:_(s64) = G_SHL %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: shlv_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shlv_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHL_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_SHL %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: shl_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shl_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_]], [[CONST_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHL_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s8) = G_CONSTANT i8 37
+ %2:_(s64) = G_SHL %0, %1
+ RETURN %2(s64), implicit-def $arguments
+
+...
+---
+name: shlv_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shlv_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHL_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %2(s32)
+ %3:_(s64) = G_SHL %0, %1
+ RETURN %3(s64), implicit-def $arguments
+
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/srem.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/srem.mir
new file mode 100644
index 0000000000000..4c9ef32cc6783
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/srem.mir
@@ -0,0 +1,122 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=-sign-ext -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NO-SIGNEXT
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=+sign-ext -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,SIGNEXT
+
+---
+name: srem_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: srem_i8
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 24, implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 24, implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHL_I32_1:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHR_S_I32_1:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_1]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[REM_S_I32_:%[0-9]+]]:i32 = REM_S_I32 [[SHR_S_I32_]], [[SHR_S_I32_1]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: RETURN [[REM_S_I32_]], implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: srem_i8
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; SIGNEXT-NEXT: [[I32_EXTEND8_S_I32_:%[0-9]+]]:i32 = I32_EXTEND8_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: [[I32_EXTEND8_S_I32_1:%[0-9]+]]:i32 = I32_EXTEND8_S_I32 [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: [[REM_S_I32_:%[0-9]+]]:i32 = REM_S_I32 [[I32_EXTEND8_S_I32_]], [[I32_EXTEND8_S_I32_1]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: RETURN [[REM_S_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_SREM %0, %1
+ %5:i32(s32) = G_ANYEXT %4(s8)
+ RETURN %5(s32), implicit-def $arguments
+...
+---
+name: srem_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; NO-SIGNEXT-LABEL: name: srem_i16
+ ; NO-SIGNEXT: liveins: $arguments
+ ; NO-SIGNEXT-NEXT: {{ $}}
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 16, implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 16, implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHL_I32_1:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[SHR_S_I32_1:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_1]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: [[REM_S_I32_:%[0-9]+]]:i32 = REM_S_I32 [[SHR_S_I32_]], [[SHR_S_I32_1]], implicit-def dead $arguments
+ ; NO-SIGNEXT-NEXT: RETURN [[REM_S_I32_]], implicit-def $arguments
+ ;
+ ; SIGNEXT-LABEL: name: srem_i16
+ ; SIGNEXT: liveins: $arguments
+ ; SIGNEXT-NEXT: {{ $}}
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; SIGNEXT-NEXT: [[I32_EXTEND16_S_I32_:%[0-9]+]]:i32 = I32_EXTEND16_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: [[I32_EXTEND16_S_I32_1:%[0-9]+]]:i32 = I32_EXTEND16_S_I32 [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: [[REM_S_I32_:%[0-9]+]]:i32 = REM_S_I32 [[I32_EXTEND16_S_I32_]], [[I32_EXTEND16_S_I32_1]], implicit-def dead $arguments
+ ; SIGNEXT-NEXT: RETURN [[REM_S_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_SREM %0, %1
+ %5:i32(s32) = G_ANYEXT %4(s16)
+ RETURN %5(s32), implicit-def $arguments
+...
+---
+name: srem_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: srem_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[REM_S_I32_:%[0-9]+]]:i32 = REM_S_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[REM_S_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_SREM %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: srem_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: srem_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[REM_S_I64_:%[0-9]+]]:i64 = REM_S_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[REM_S_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_SREM %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sub.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sub.mir
similarity index 55%
rename from llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sub.mir
rename to llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sub.mir
index 97770cb6280cb..d47a893852d70 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sub.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sub.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: sub_i8
@@ -12,11 +12,10 @@ body: |
; CHECK-LABEL: name: sub_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[SUB]](s32)
- ; CHECK-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[SUB_I32_:%[0-9]+]]:i32 = SUB_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SUB_I32_]], implicit-def $arguments
%2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s8) = G_TRUNC %2(s32)
%3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
@@ -36,11 +35,10 @@ body: |
; CHECK-LABEL: name: sub_i16
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[SUB]](s32)
- ; CHECK-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[SUB_I32_:%[0-9]+]]:i32 = SUB_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SUB_I32_]], implicit-def $arguments
%2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s16) = G_TRUNC %2(s32)
%3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
@@ -60,10 +58,10 @@ body: |
; CHECK-LABEL: name: sub_i32
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: RETURN [[SUB]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[SUB_I32_:%[0-9]+]]:i32 = SUB_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SUB_I32_]], implicit-def $arguments
%0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
%2:_(s32) = G_SUB %0, %1
@@ -80,10 +78,10 @@ body: |
; CHECK-LABEL: name: sub_i64
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
- ; CHECK-NEXT: RETURN [[SUB]](s64), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[SUB_I64_:%[0-9]+]]:i64 = SUB_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SUB_I64_]], implicit-def $arguments
%0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
%1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
%2:_(s64) = G_SUB %0, %1
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/trunc.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/trunc.mir
similarity index 62%
rename from llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/trunc.mir
rename to llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/trunc.mir
index c9dfd3175e6d6..f9b73d1d9d7d4 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/trunc.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/trunc.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: trunc_i32_i8
@@ -12,8 +12,8 @@ body: |
; CHECK-LABEL: name: trunc_i32_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: RETURN [[ARGUMENT_i32_]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: RETURN [[ARGUMENT_i32_]], implicit-def $arguments
%1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s8) = G_TRUNC %1(s32)
%2:i32(s32) = G_ANYEXT %0(s8)
@@ -30,8 +30,8 @@ body: |
; CHECK-LABEL: name: trunc_i32_i16
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: RETURN [[ARGUMENT_i32_]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: RETURN [[ARGUMENT_i32_]], implicit-def $arguments
%1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s16) = G_TRUNC %1(s32)
%2:i32(s32) = G_ANYEXT %0(s16)
@@ -48,9 +48,9 @@ body: |
; CHECK-LABEL: name: trunc_i64_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:i32(s32) = G_TRUNC [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
%1:i64(s64) = ARGUMENT_i64 0, implicit $arguments
%0:_(s8) = G_TRUNC %1(s64)
%2:i32(s32) = G_ANYEXT %0(s8)
@@ -67,9 +67,9 @@ body: |
; CHECK-LABEL: name: trunc_i64_i16
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:i32(s32) = G_TRUNC [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
%1:i64(s64) = ARGUMENT_i64 0, implicit $arguments
%0:_(s16) = G_TRUNC %1(s64)
%2:i32(s32) = G_ANYEXT %0(s16)
@@ -86,9 +86,9 @@ body: |
; CHECK-LABEL: name: trunc_i64_i32
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
%1:i64(s64) = ARGUMENT_i64 0, implicit $arguments
%0:_(s32) = G_TRUNC %1(s64)
RETURN %0(s32), implicit-def $arguments
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/udiv.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/udiv.mir
new file mode 100644
index 0000000000000..29de1db5e286b
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/udiv.mir
@@ -0,0 +1,97 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: udiv_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: udiv_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[DIV_U_I32_:%[0-9]+]]:i32 = DIV_U_I32 [[AND_I32_]], [[AND_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[DIV_U_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_UDIV %0, %1
+ %5:i32(s32) = G_ANYEXT %4(s8)
+ RETURN %5(s32), implicit-def $arguments
+...
+---
+name: udiv_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: udiv_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[DIV_U_I32_:%[0-9]+]]:i32 = DIV_U_I32 [[AND_I32_]], [[AND_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[DIV_U_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_UDIV %0, %1
+ %5:i32(s32) = G_ANYEXT %4(s16)
+ RETURN %5(s32), implicit-def $arguments
+...
+---
+name: udiv_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: udiv_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[DIV_U_I32_:%[0-9]+]]:i32 = DIV_U_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[DIV_U_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_UDIV %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: udiv_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: udiv_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[DIV_U_I64_:%[0-9]+]]:i64 = DIV_U_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[DIV_U_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_UDIV %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/urem.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/urem.mir
new file mode 100644
index 0000000000000..033a9dbfa0671
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/urem.mir
@@ -0,0 +1,97 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: urem_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: urem_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[REM_U_I32_:%[0-9]+]]:i32 = REM_U_I32 [[AND_I32_]], [[AND_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[REM_U_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_UREM %0, %1
+ %5:i32(s32) = G_ANYEXT %4(s8)
+ RETURN %5(s32), implicit-def $arguments
+...
+---
+name: urem_i16
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: urem_i16
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[REM_U_I32_:%[0-9]+]]:i32 = REM_U_I32 [[AND_I32_]], [[AND_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[REM_U_I32_]], implicit-def $arguments
+ %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_UREM %0, %1
+ %5:i32(s32) = G_ANYEXT %4(s16)
+ RETURN %5(s32), implicit-def $arguments
+...
+---
+name: urem_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: urem_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[REM_U_I32_:%[0-9]+]]:i32 = REM_U_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[REM_U_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s32) = G_UREM %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: urem_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: urem_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[REM_U_I64_:%[0-9]+]]:i64 = REM_U_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[REM_U_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s64) = G_UREM %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/xor.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/xor.mir
similarity index 55%
rename from llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/xor.mir
rename to llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/xor.mir
index 1bc7ace2b3e7f..921d7a30a8070 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/xor.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/xor.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: xor_i1
@@ -12,10 +12,10 @@ body: |
; CHECK-LABEL: name: xor_i1
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]]
- ; CHECK-NEXT: RETURN [[XOR]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[XOR_I32_]], implicit-def $arguments
%2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s1) = G_TRUNC %2(s32)
%3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
@@ -36,10 +36,10 @@ body: |
; CHECK-LABEL: name: xor_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]]
- ; CHECK-NEXT: RETURN [[XOR]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[XOR_I32_]], implicit-def $arguments
%2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s8) = G_TRUNC %2(s32)
%3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
@@ -60,10 +60,10 @@ body: |
; CHECK-LABEL: name: xor_i16
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]]
- ; CHECK-NEXT: RETURN [[XOR]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[XOR_I32_]], implicit-def $arguments
%2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%0:_(s16) = G_TRUNC %2(s32)
%3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
@@ -84,10 +84,10 @@ body: |
; CHECK-LABEL: name: xor_i32
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]]
- ; CHECK-NEXT: RETURN [[XOR]](s32), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[XOR_I32_]], implicit-def $arguments
%0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
%1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
%2:_(s32) = G_XOR %1, %0
@@ -105,10 +105,10 @@ body: |
; CHECK-LABEL: name: xor_i64
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ARGUMENT_i64_1]], [[ARGUMENT_i64_]]
- ; CHECK-NEXT: RETURN [[XOR]](s64), implicit-def $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[XOR_I64_:%[0-9]+]]:i64 = XOR_I64 [[ARGUMENT_i64_1]], [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[XOR_I64_]], implicit-def $arguments
%0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
%1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
%2:_(s64) = G_XOR %1, %0
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/zext.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/zext.mir
new file mode 100644
index 0000000000000..5e0079d181b71
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/zext.mir
@@ -0,0 +1,103 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: zext_i8_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: zext_i8_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[AND_I32_]], implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %1(s32)
+ %2:i32(s32) = G_ZEXT %0(s8)
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: zext_i8_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: zext_i8_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[AND_I64_]], implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s8) = G_TRUNC %1(s32)
+ %2:i64(s64) = G_ZEXT %0(s8)
+ RETURN %2(s64), implicit-def $arguments
+...
+---
+name: zext_i16_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: zext_i16_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[AND_I32_]], implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %1(s32)
+ %2:i32(s32) = G_ZEXT %0(s16)
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: zext_i16_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: zext_i16_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 65535, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[AND_I64_]], implicit-def $arguments
+ %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %0:_(s16) = G_TRUNC %1(s32)
+ %2:i64(s64) = G_ZEXT %0(s16)
+ RETURN %2(s64), implicit-def $arguments
+...
+---
+name: zext_i32_i64
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: zext_i32_i64
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I64_EXTEND_U_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i64(s64) = G_ZEXT %0(s32)
+ RETURN %1(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/bitwise.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/bitwise.mir
deleted file mode 100644
index 2af53ff71ce2d..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/bitwise.mir
+++ /dev/null
@@ -1,485 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: and_i32
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: and_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[AND_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:i32regbank(s32) = G_AND %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: and_i64
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: and_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[AND_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:i64regbank(s64) = G_AND %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
-
----
-name: or_i32
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: or_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = OR_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:i32regbank(s32) = G_OR %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: or_i64
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: or_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = OR_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:i64regbank(s64) = G_OR %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
-
----
-name: xor_i32
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: xor_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[XOR_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:i32regbank(s32) = G_XOR %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: xor_i64
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: xor_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[XOR_I64_:%[0-9]+]]:i64 = XOR_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[XOR_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:i64regbank(s64) = G_XOR %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
-
----
-name: shl_i32
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shl_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 5, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHL_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32regbank(s32) = G_CONSTANT i32 5
- %2:i32regbank(s32) = G_SHL %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: shl_i64
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shl_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[CONST_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHL_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64regbank(s64) = G_CONSTANT i64 37
- %2:i64regbank(s64) = G_SHL %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
-
----
-name: ashr_i32
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ashr_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 5, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32regbank(s32) = G_CONSTANT i32 5
- %2:i32regbank(s32) = G_ASHR %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: ashr_i64
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ashr_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_S_I64_:%[0-9]+]]:i64 = SHR_S_I64 [[ARGUMENT_i64_]], [[CONST_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHR_S_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64regbank(s64) = G_CONSTANT i64 37
- %2:i64regbank(s64) = G_ASHR %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
-
----
-name: lshr_i32
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshr_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 5, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHR_U_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32regbank(s32) = G_CONSTANT i32 5
- %2:i32regbank(s32) = G_LSHR %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: lshr_i64
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshr_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_]], [[CONST_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHR_U_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64regbank(s64) = G_CONSTANT i64 37
- %2:i64regbank(s64) = G_LSHR %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
-
----
-name: ctlz_i32
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CLZ_I32_:%[0-9]+]]:i32 = CLZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CLZ_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32regbank(s32) = G_CTLZ %0
- RETURN %1(s32), implicit-def $arguments
-...
----
-name: ctlz_i64
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CLZ_I64_:%[0-9]+]]:i64 = CLZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CLZ_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64regbank(s64) = G_CTLZ %0
- RETURN %1(s64), implicit-def $arguments
-...
-
----
-name: cttz_i32
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: cttz_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CTZ_I32_:%[0-9]+]]:i32 = CTZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CTZ_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32regbank(s32) = G_CTTZ %0
- RETURN %1(s32), implicit-def $arguments
-...
----
-name: cttz_i64
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: cttz_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTZ_I64_:%[0-9]+]]:i64 = CTZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CTZ_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64regbank(s64) = G_CTTZ %0
- RETURN %1(s64), implicit-def $arguments
-...
-
----
-name: ctpop_i32
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctpop_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[POPCNT_I32_:%[0-9]+]]:i32 = POPCNT_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[POPCNT_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32regbank(s32) = G_CTPOP %0
- RETURN %1(s32), implicit-def $arguments
-...
----
-name: ctpop_i64
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctpop_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[POPCNT_I64_:%[0-9]+]]:i64 = POPCNT_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[POPCNT_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64regbank(s64) = G_CTPOP %0
- RETURN %1(s64), implicit-def $arguments
-...
-
----
-name: rotl_i32
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotl_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ROTL_I32_:%[0-9]+]]:i32 = ROTL_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[ROTL_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:i32regbank(s32) = G_ROTL %0, %1(s32)
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: rotl_i64
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotl_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[ROTL_I64_:%[0-9]+]]:i64 = ROTL_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[ROTL_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:i64regbank(s64) = G_ROTL %0, %1(s64)
- RETURN %2(s64), implicit-def $arguments
-...
-
----
-name: rotr_i32
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotr_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ROTR_I32_:%[0-9]+]]:i32 = ROTR_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[ROTR_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:i32regbank(s32) = G_ROTR %0, %1(s32)
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: rotr_i64
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotr_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[ROTR_I64_:%[0-9]+]]:i64 = ROTR_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[ROTR_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:i64regbank(s64) = G_ROTR %0, %1(s64)
- RETURN %2(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/consts.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/consts.mir
deleted file mode 100644
index f3ee685d18a85..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/consts.mir
+++ /dev/null
@@ -1,76 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: const_i32
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: const_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 0, implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CONST_I32_]], implicit-def $arguments
- %0:i32regbank(s32) = G_CONSTANT i32 0
- RETURN %0(s32), implicit-def $arguments
-...
----
-name: const_i64
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: const_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 0, implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CONST_I64_]], implicit-def $arguments
- %0:i64regbank(s64) = G_CONSTANT i64 0
- RETURN %0(s64), implicit-def $arguments
-...
-
----
-name: implicit_i32
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: implicit_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:i32 = IMPLICIT_DEF
- ; CHECK-NEXT: RETURN [[DEF]], implicit-def $arguments
- %0:i32regbank(s32) = G_IMPLICIT_DEF
- RETURN %0(s32), implicit-def $arguments
-...
----
-name: implicit_i64
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: implicit_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:i64 = IMPLICIT_DEF
- ; CHECK-NEXT: RETURN [[DEF]], implicit-def $arguments
- %0:i64regbank(s64) = G_IMPLICIT_DEF
- RETURN %0(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/ext-trunc.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/ext-trunc.mir
deleted file mode 100644
index 6c150bd2884cf..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/ext-trunc.mir
+++ /dev/null
@@ -1,186 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: anyext
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: anyext
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[I64_EXTEND_U_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i64regbank(s64) = G_ANYEXT %0
- RETURN %1(s64), implicit-def $arguments
-...
----
-name: sext
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sext
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[I64_EXTEND_S_I32_:%[0-9]+]]:i64 = I64_EXTEND_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[I64_EXTEND_S_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i64regbank(s64) = G_SEXT %0
- RETURN %1(s64), implicit-def $arguments
-...
----
-name: zext
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: zext
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[I64_EXTEND_U_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i64regbank(s64) = G_ZEXT %0
- RETURN %1(s64), implicit-def $arguments
-...
----
-name: trunc
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: trunc
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i32regbank(s32) = G_TRUNC %0
- RETURN %1(s32), implicit-def $arguments
-...
-
----
-name: sext_inreg_i32_8
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sext_inreg_i32_8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[I32_EXTEND8_S_I32_:%[0-9]+]]:i32 = I32_EXTEND8_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[I32_EXTEND8_S_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32regbank(s32) = G_SEXT_INREG %0, 8
- RETURN %1(s32), implicit-def $arguments
-...
----
-name: sext_inreg_i64_8
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sext_inreg_i64_8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[I64_EXTEND8_S_I64_:%[0-9]+]]:i64 = I64_EXTEND8_S_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[I64_EXTEND8_S_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64regbank(s64) = G_SEXT_INREG %0, 8
- RETURN %1(s64), implicit-def $arguments
-...
-
----
-name: sext_inreg_i32_16
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sext_inreg_i32_16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[I32_EXTEND16_S_I32_:%[0-9]+]]:i32 = I32_EXTEND16_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[I32_EXTEND16_S_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32regbank(s32) = G_SEXT_INREG %0, 16
- RETURN %1(s32), implicit-def $arguments
-...
----
-name: sext_inreg_i64_16
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sext_inreg_i64_16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[I64_EXTEND16_S_I64_:%[0-9]+]]:i64 = I64_EXTEND16_S_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[I64_EXTEND16_S_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64regbank(s64) = G_SEXT_INREG %0, 16
- RETURN %1(s64), implicit-def $arguments
-...
-
----
-name: sext_inreg_i64_32
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sext_inreg_i64_32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[I64_EXTEND32_S_I64_:%[0-9]+]]:i64 = I64_EXTEND32_S_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[I64_EXTEND32_S_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64regbank(s64) = G_SEXT_INREG %0, 32
- RETURN %1(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/int-arithmetic.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/int-arithmetic.mir
deleted file mode 100644
index 2d13318da5a84..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/int-arithmetic.mir
+++ /dev/null
@@ -1,317 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: add_i32
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: add_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ADD_I32_:%[0-9]+]]:i32 = ADD_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[ADD_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:i32regbank(s32) = G_ADD %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: add_i64
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: add_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[ADD_I64_:%[0-9]+]]:i64 = ADD_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[ADD_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:i64regbank(s64) = G_ADD %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
-
----
-name: sub_i32
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sub_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[SUB_I32_:%[0-9]+]]:i32 = SUB_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SUB_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:i32regbank(s32) = G_SUB %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: sub_i64
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sub_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[SUB_I64_:%[0-9]+]]:i64 = SUB_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SUB_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:i64regbank(s64) = G_SUB %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
-
----
-name: mul_i32
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: mul_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[MUL_I32_:%[0-9]+]]:i32 = MUL_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[MUL_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:i32regbank(s32) = G_MUL %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: mul_i64
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: mul_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[MUL_I64_:%[0-9]+]]:i64 = MUL_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[MUL_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:i64regbank(s64) = G_MUL %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
-
----
-name: udiv_i32
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: udiv_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[DIV_U_I32_:%[0-9]+]]:i32 = DIV_U_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[DIV_U_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:i32regbank(s32) = G_UDIV %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: udiv_i64
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: udiv_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[DIV_U_I64_:%[0-9]+]]:i64 = DIV_U_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[DIV_U_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:i64regbank(s64) = G_UDIV %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
-
----
-name: sdiv_i32
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sdiv_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[DIV_S_I32_:%[0-9]+]]:i32 = DIV_S_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[DIV_S_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:i32regbank(s32) = G_SDIV %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: sdiv_i64
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sdiv_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[DIV_S_I64_:%[0-9]+]]:i64 = DIV_S_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[DIV_S_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:i64regbank(s64) = G_SDIV %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
-
----
-name: urem_i32
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: urem_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[REM_U_I32_:%[0-9]+]]:i32 = REM_U_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[REM_U_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:i32regbank(s32) = G_UREM %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: urem_i64
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: urem_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[REM_U_I64_:%[0-9]+]]:i64 = REM_U_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[REM_U_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:i64regbank(s64) = G_UREM %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
-
----
-name: srem_i32
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: srem_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[REM_S_I32_:%[0-9]+]]:i32 = REM_S_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[REM_S_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:i32regbank(s32) = G_SREM %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: srem_i64
-alignment: 1
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: srem_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[REM_S_I64_:%[0-9]+]]:i64 = REM_S_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[REM_S_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:i64regbank(s64) = G_SREM %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/add.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/add.mir
deleted file mode 100644
index 8865e0e730f61..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/add.mir
+++ /dev/null
@@ -1,219 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=-sign-ext -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NO-SIGNEXT
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=+sign-ext -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,SIGNEXT
-
----
-name: add_i8_zext
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: add_i8_zext
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:i32(s32) = G_AND [[ADD]], [[C]]
- ; CHECK-NEXT: RETURN [[AND]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_ADD %0, %1
- %5:i32(s32) = G_ZEXT %4(s8)
- RETURN %5(s32), implicit-def $arguments
-...
-
----
-name: add_i8_sext
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: add_i8_sext
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ADD]], [[C]](s32)
- ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:i32(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; NO-SIGNEXT-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: add_i8_sext
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; SIGNEXT-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:i32(s32) = G_SEXT_INREG [[ADD]], 8
- ; SIGNEXT-NEXT: RETURN [[SEXT_INREG]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_ADD %0, %1
- %5:i32(s32) = G_SEXT %4(s8)
- RETURN %5(s32), implicit-def $arguments
-...
-
----
-name: add_i8_aext
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: add_i8_aext
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[ADD]](s32)
- ; CHECK-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_ADD %0, %1
- %5:i32(s32) = G_ANYEXT %4(s8)
- RETURN %5(s32), implicit-def $arguments
-...
-
----
-name: add_i16_zext
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: add_i16_zext
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:i32(s32) = G_AND [[ADD]], [[C]]
- ; CHECK-NEXT: RETURN [[AND]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_ADD %0, %1
- %5:i32(s32) = G_ZEXT %4(s16)
- RETURN %5(s32), implicit-def $arguments
-...
-
----
-name: add_i16_sext
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: add_i16_sext
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ADD]], [[C]](s32)
- ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:i32(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; NO-SIGNEXT-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: add_i16_sext
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; SIGNEXT-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:i32(s32) = G_SEXT_INREG [[ADD]], 16
- ; SIGNEXT-NEXT: RETURN [[SEXT_INREG]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_ADD %0, %1
- %5:i32(s32) = G_SEXT %4(s16)
- RETURN %5(s32), implicit-def $arguments
-...
-
----
-name: add_i16_aext
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: add_i16_aext
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[ADD]](s32)
- ; CHECK-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_ADD %0, %1
- %5:i32(s32) = G_ANYEXT %4(s16)
- RETURN %5(s32), implicit-def $arguments
-...
-
----
-name: add_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: add_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: RETURN [[ADD]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_ADD %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
-
----
-name: add_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: add_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
- ; CHECK-NEXT: RETURN [[ADD]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_ADD %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ashr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ashr.mir
deleted file mode 100644
index e38b3b87c9e8d..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ashr.mir
+++ /dev/null
@@ -1,331 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=-sign-ext -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NO-SIGNEXT
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=+sign-ext -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,SIGNEXT
-
----
-name: ashr_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: ashr_i8
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; NO-SIGNEXT-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C1]](s32)
- ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
- ; NO-SIGNEXT-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C]](s32)
- ; NO-SIGNEXT-NEXT: RETURN [[ASHR1]](s32), implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: ashr_i8
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ARGUMENT_i32_]], 8
- ; SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
- ; SIGNEXT-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %1:_(s8) = G_CONSTANT i8 5
- %3:_(s8) = G_ASHR %0, %1
- %4:_(s32) = G_ANYEXT %3(s8)
- RETURN %4(s32), implicit-def $arguments
-
-...
----
-name: ashrv_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: ashrv_i8
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
- ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; NO-SIGNEXT-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; NO-SIGNEXT-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C1]]
- ; NO-SIGNEXT-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
- ; NO-SIGNEXT-NEXT: RETURN [[ASHR1]](s32), implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: ashrv_i8
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ARGUMENT_i32_]], 8
- ; SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SIGNEXT-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C]]
- ; SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
- ; SIGNEXT-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_ASHR %0, %1
- %5:_(s32) = G_ANYEXT %4(s8)
- RETURN %5(s32), implicit-def $arguments
-
-...
----
-name: ashr_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: ashr_i16
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
- ; NO-SIGNEXT-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C1]](s32)
- ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
- ; NO-SIGNEXT-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C]](s32)
- ; NO-SIGNEXT-NEXT: RETURN [[ASHR1]](s32), implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: ashr_i16
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
- ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ARGUMENT_i32_]], 16
- ; SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
- ; SIGNEXT-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %1:_(s16) = G_CONSTANT i16 13
- %3:_(s16) = G_ASHR %0, %1
- %4:_(s32) = G_ANYEXT %3(s16)
- RETURN %4(s32), implicit-def $arguments
-
-...
----
-name: ashrv_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: ashrv_i16
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
- ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; NO-SIGNEXT-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; NO-SIGNEXT-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C1]]
- ; NO-SIGNEXT-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
- ; NO-SIGNEXT-NEXT: RETURN [[ASHR1]](s32), implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: ashrv_i16
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ARGUMENT_i32_]], 16
- ; SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SIGNEXT-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C]]
- ; SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
- ; SIGNEXT-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_ASHR %0, %1
- %5:_(s32) = G_ANYEXT %4(s16)
- RETURN %5(s32), implicit-def $arguments
-
-...
----
-name: ashr_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ashr_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ARGUMENT_i32_]], [[C]](s32)
- ; CHECK-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_CONSTANT i32 21
- %2:_(s32) = G_ASHR %0, %1
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: ashrv_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ashrv_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]](s32)
- ; CHECK-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_ASHR %0, %1
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: ashr_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ashr_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ARGUMENT_i32_]], [[C]](s32)
- ; CHECK-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s8) = G_CONSTANT i8 21
- %2:_(s32) = G_ASHR %0, %1
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: ashrv_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ashrv_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C]]
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ARGUMENT_i32_]], [[AND]](s32)
- ; CHECK-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %2(s32)
- %3:_(s32) = G_ASHR %0, %1
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: ashr_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ashr_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[ARGUMENT_i64_]], [[C]](s64)
- ; CHECK-NEXT: RETURN [[ASHR]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_CONSTANT i64 37
- %2:_(s64) = G_ASHR %0, %1
- RETURN %2(s64), implicit-def $arguments
-
-...
----
-name: ashrv_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ashrv_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]](s64)
- ; CHECK-NEXT: RETURN [[ASHR]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_ASHR %0, %1
- RETURN %2(s64), implicit-def $arguments
-
-...
----
-name: ashr_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ashr_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[C]], [[C1]]
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[ARGUMENT_i64_]], [[AND]](s64)
- ; CHECK-NEXT: RETURN [[ASHR]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s8) = G_CONSTANT i8 37
- %2:_(s64) = G_ASHR %0, %1
- RETURN %2(s64), implicit-def $arguments
-
-...
----
-name: ashrv_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ashrv_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[ARGUMENT_i64_]], [[AND]](s64)
- ; CHECK-NEXT: RETURN [[ASHR]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %2(s32)
- %3:_(s64) = G_ASHR %0, %1
- RETURN %3(s64), implicit-def $arguments
-
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ctlz.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ctlz.mir
deleted file mode 100644
index 39e1531194711..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ctlz.mir
+++ /dev/null
@@ -1,152 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: ctlz_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
- ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = nuw G_SUB [[CTLZ]], [[C1]]
- ; CHECK-NEXT: RETURN [[SUB]](s32), implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %1(s32)
- %2:_(s8) = G_CTLZ %0
- %3:_(s32) = G_ANYEXT %2(s8)
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: ctlz_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
- ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = nuw G_SUB [[CTLZ]], [[C1]]
- ; CHECK-NEXT: RETURN [[SUB]](s32), implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %1(s32)
- %2:_(s16) = G_CTLZ %0
- %3:_(s32) = G_ANYEXT %2(s16)
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: ctlz_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[CTLZ]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_CTLZ %0
- RETURN %1(s32), implicit-def $arguments
-
-...
----
-name: ctlz_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[CTLZ]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s8) = G_CTLZ %0
- %2:_(s32) = G_ANYEXT %1(s8)
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: ctlz_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: RETURN [[CTLZ]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_CTLZ %0
- RETURN %1(s64), implicit-def $arguments
-
-...
----
-name: ctlz_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTLZ]](s64)
- ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s8) = G_CTLZ %0
- %2:_(s32) = G_ANYEXT %1(s8)
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: ctlz_i64_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_i64_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTLZ]](s64)
- ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s32) = G_CTLZ %0
- RETURN %1(s32), implicit-def $arguments
-
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ctlz_zero_undef.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ctlz_zero_undef.mir
deleted file mode 100644
index e00396d20b7e3..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/ctlz_zero_undef.mir
+++ /dev/null
@@ -1,152 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: ctlz_zundef_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_zundef_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
- ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = nuw G_SUB [[CTLZ]], [[C1]]
- ; CHECK-NEXT: RETURN [[SUB]](s32), implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %1(s32)
- %2:_(s8) = G_CTLZ_ZERO_UNDEF %0
- %3:_(s32) = G_ANYEXT %2(s8)
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: ctlz_zundef_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_zundef_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
- ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = nuw G_SUB [[CTLZ]], [[C1]]
- ; CHECK-NEXT: RETURN [[SUB]](s32), implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %1(s32)
- %2:_(s16) = G_CTLZ_ZERO_UNDEF %0
- %3:_(s32) = G_ANYEXT %2(s16)
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: ctlz_zundef_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_zundef_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[CTLZ]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_CTLZ_ZERO_UNDEF %0
- RETURN %1(s32), implicit-def $arguments
-
-...
----
-name: ctlz_zundef_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_zundef_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[CTLZ]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s8) = G_CTLZ_ZERO_UNDEF %0
- %2:_(s32) = G_ANYEXT %1(s8)
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: ctlz_zundef_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_zundef_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: RETURN [[CTLZ]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_CTLZ_ZERO_UNDEF %0
- RETURN %1(s64), implicit-def $arguments
-
-...
----
-name: ctlz_zundef_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_zundef_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTLZ]](s64)
- ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s8) = G_CTLZ_ZERO_UNDEF %0
- %2:_(s32) = G_ANYEXT %1(s8)
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: ctlz_zundef_i64_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_zundef_i64_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CTLZ]](s64)
- ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s32) = G_CTLZ_ZERO_UNDEF %0
- RETURN %1(s32), implicit-def $arguments
-
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/fshl.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/fshl.mir
deleted file mode 100644
index 3aa32c39ee15f..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/fshl.mir
+++ /dev/null
@@ -1,393 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
-
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: fshl_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshl_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C2]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_CONSTANT i8 5
- %5:_(s8) = G_FSHL %0, %1, %4(s8)
- %6:_(s32) = G_ANYEXT %5(s8)
- RETURN %6(s32), implicit-def $arguments
-
-...
----
-name: fshlv_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshlv_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_2]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_2]], [[C1]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[AND]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C3]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C2]](s32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
- ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR1]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
- %3:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %3(s32)
- %4:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %4(s32)
- %5:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- %2:_(s8) = G_TRUNC %5(s32)
- %6:_(s8) = G_FSHL %0, %1, %2(s8)
- %7:_(s32) = G_ANYEXT %6(s8)
- RETURN %7(s32), implicit-def $arguments
-
-...
----
-name: fshl_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshl_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C2]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_CONSTANT i16 13
- %5:_(s16) = G_FSHL %0, %1, %4(s16)
- %6:_(s32) = G_ANYEXT %5(s16)
- RETURN %6(s32), implicit-def $arguments
-
-...
----
-name: fshlv_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshlv_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_2]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_2]], [[C1]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[AND]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C3]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C2]](s32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
- ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR1]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
- %3:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %3(s32)
- %4:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %4(s32)
- %5:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- %2:_(s16) = G_TRUNC %5(s32)
- %6:_(s16) = G_FSHL %0, %1, %2(s16)
- %7:_(s32) = G_ANYEXT %6(s16)
- RETURN %7(s32), implicit-def $arguments
-
-...
----
-name: fshl_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshl_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ARGUMENT_i32_1]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_CONSTANT i32 21
- %3:_(s32) = G_FSHL %0, %1, %2(s32)
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: fshlv_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshlv_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_2]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_2]], [[C1]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[AND]](s32)
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ARGUMENT_i32_1]], [[C2]](s32)
- ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[AND1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR1]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- %3:_(s32) = G_FSHL %0, %1, %2(s32)
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: fshl_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshl_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ARGUMENT_i32_1]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s8) = G_CONSTANT i8 21
- %3:_(s32) = G_FSHL %0, %1, %2(s8)
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: fshlv_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshlv_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_2]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_2]], [[C1]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[AND]](s32)
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ARGUMENT_i32_1]], [[C2]](s32)
- ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[AND1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR1]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %3:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- %2:_(s8) = G_TRUNC %3(s32)
- %4:_(s32) = G_FSHL %0, %1, %2(s8)
- RETURN %4(s32), implicit-def $arguments
-
-...
----
-name: fshl_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshl_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 27
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ARGUMENT_i64_]], [[C]](s64)
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ARGUMENT_i64_1]], [[C1]](s64)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL]], [[LSHR]]
- ; CHECK-NEXT: RETURN [[OR]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_CONSTANT i64 37
- %3:_(s64) = G_FSHL %0, %1, %2(s64)
- RETURN %3(s64), implicit-def $arguments
-
-...
----
-name: fshlv_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshlv_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_2:%[0-9]+]]:i64(s64) = ARGUMENT_i64 2, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ARGUMENT_i64_2]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ARGUMENT_i64_2]], [[C1]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ARGUMENT_i64_]], [[AND]](s64)
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ARGUMENT_i64_1]], [[C2]](s64)
- ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[LSHR]], [[AND1]](s64)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL]], [[LSHR1]]
- ; CHECK-NEXT: RETURN [[OR]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:i64(s64) = ARGUMENT_i64 2, implicit $arguments
- %3:_(s64) = G_FSHL %0, %1, %2(s64)
- RETURN %3(s64), implicit-def $arguments
-
-...
----
-name: fshl_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshl_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 21
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[C]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ARGUMENT_i64_]], [[AND]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 43
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[C2]], [[C3]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ARGUMENT_i64_1]], [[AND1]](s64)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL]], [[LSHR]]
- ; CHECK-NEXT: RETURN [[OR]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s8) = G_CONSTANT i8 21
- %3:_(s64) = G_FSHL %0, %1, %2(s8)
- RETURN %3(s64), implicit-def $arguments
-
-...
----
-name: fshlv_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshlv_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_]], [[C1]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C2]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ARGUMENT_i64_]], [[AND2]](s64)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[C3]], [[C4]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ARGUMENT_i64_1]], [[AND3]](s64)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[AND1]](s32)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ANYEXT1]], [[C5]]
- ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[LSHR]], [[AND4]](s64)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL]], [[LSHR1]]
- ; CHECK-NEXT: RETURN [[OR]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %3:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- %2:_(s8) = G_TRUNC %3(s32)
- %4:_(s64) = G_FSHL %0, %1, %2(s8)
- RETURN %4(s64), implicit-def $arguments
-
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/fshr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/fshr.mir
deleted file mode 100644
index 0437c51d310c9..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/fshr.mir
+++ /dev/null
@@ -1,389 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
-
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: fshr_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshr_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C1]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C2]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_CONSTANT i8 5
- %5:_(s8) = G_FSHR %0, %1, %4(s8)
- %6:_(s32) = G_ANYEXT %5(s8)
- RETURN %6(s32), implicit-def $arguments
-
-...
----
-name: fshrv_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshrv_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_2]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_2]], [[C1]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C2]](s32)
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C3]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL1]], [[LSHR]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
- %3:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %3(s32)
- %4:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %4(s32)
- %5:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- %2:_(s8) = G_TRUNC %5(s32)
- %6:_(s8) = G_FSHR %0, %1, %2(s8)
- %7:_(s32) = G_ANYEXT %6(s8)
- RETURN %7(s32), implicit-def $arguments
-
-...
----
-name: fshr_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshr_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C1]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C2]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_CONSTANT i16 13
- %5:_(s16) = G_FSHR %0, %1, %4(s16)
- %6:_(s32) = G_ANYEXT %5(s16)
- RETURN %6(s32), implicit-def $arguments
-
-...
----
-name: fshrv_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshrv_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_2]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_2]], [[C1]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C2]](s32)
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C3]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL1]], [[LSHR]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
- %3:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %3(s32)
- %4:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %4(s32)
- %5:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- %2:_(s16) = G_TRUNC %5(s32)
- %6:_(s16) = G_FSHR %0, %1, %2(s16)
- %7:_(s32) = G_ANYEXT %6(s16)
- RETURN %7(s32), implicit-def $arguments
-
-...
----
-name: fshr_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshr_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C1]](s32)
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ARGUMENT_i32_1]], [[C]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_CONSTANT i32 21
- %3:_(s32) = G_FSHR %0, %1, %2(s32)
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: fshrv_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshrv_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_2]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_2]], [[C1]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C2]](s32)
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32)
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ARGUMENT_i32_1]], [[AND]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL1]], [[LSHR]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- %3:_(s32) = G_FSHR %0, %1, %2(s32)
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: fshr_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshr_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C1]](s32)
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ARGUMENT_i32_1]], [[C]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s8) = G_CONSTANT i8 21
- %3:_(s32) = G_FSHR %0, %1, %2(s8)
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: fshrv_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshrv_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_2]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_2]], [[C1]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C2]](s32)
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32)
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ARGUMENT_i32_1]], [[AND]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL1]], [[LSHR]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %3:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- %2:_(s8) = G_TRUNC %3(s32)
- %4:_(s32) = G_FSHR %0, %1, %2(s8)
- RETURN %4(s32), implicit-def $arguments
-
-...
----
-name: fshr_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshr_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 27
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ARGUMENT_i64_]], [[C1]](s64)
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ARGUMENT_i64_1]], [[C]](s64)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL]], [[LSHR]]
- ; CHECK-NEXT: RETURN [[OR]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_CONSTANT i64 37
- %3:_(s64) = G_FSHR %0, %1, %2(s64)
- RETURN %3(s64), implicit-def $arguments
-
-...
----
-name: fshrv_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshrv_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_2:%[0-9]+]]:i64(s64) = ARGUMENT_i64 2, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ARGUMENT_i64_2]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ARGUMENT_i64_2]], [[C1]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ARGUMENT_i64_]], [[C2]](s64)
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SHL]], [[AND1]](s64)
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ARGUMENT_i64_1]], [[AND]](s64)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL1]], [[LSHR]]
- ; CHECK-NEXT: RETURN [[OR]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:i64(s64) = ARGUMENT_i64 2, implicit $arguments
- %3:_(s64) = G_FSHR %0, %1, %2(s64)
- RETURN %3(s64), implicit-def $arguments
-
-...
----
-name: fshr_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshr_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 43
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[C]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ARGUMENT_i64_]], [[AND]](s64)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 21
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[C2]], [[C3]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ARGUMENT_i64_1]], [[AND1]](s64)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL]], [[LSHR]]
- ; CHECK-NEXT: RETURN [[OR]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s8) = G_CONSTANT i8 21
- %3:_(s64) = G_FSHR %0, %1, %2(s8)
- RETURN %3(s64), implicit-def $arguments
-
-...
----
-name: fshrv_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshrv_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ARGUMENT_i32_]], [[C1]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[C2]], [[C3]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ARGUMENT_i64_]], [[AND2]](s64)
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND1]](s32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C4]]
- ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SHL]], [[AND3]](s64)
- ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[AND]](s32)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ANYEXT1]], [[C5]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ARGUMENT_i64_1]], [[AND4]](s64)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL1]], [[LSHR]]
- ; CHECK-NEXT: RETURN [[OR]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %3:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- %2:_(s8) = G_TRUNC %3(s32)
- %4:_(s64) = G_FSHR %0, %1, %2(s8)
- RETURN %4(s64), implicit-def $arguments
-
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/lshr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/lshr.mir
deleted file mode 100644
index f8150c9cfd7a4..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/lshr.mir
+++ /dev/null
@@ -1,286 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: lshr_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshr_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C1]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)
- ; CHECK-NEXT: RETURN [[LSHR]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %1:_(s8) = G_CONSTANT i8 5
- %3:_(s8) = G_LSHR %0, %1
- %4:_(s32) = G_ANYEXT %3(s8)
- RETURN %4(s32), implicit-def $arguments
-
-...
----
-name: lshrv_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshrv_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C1]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[AND1]](s32)
- ; CHECK-NEXT: RETURN [[LSHR]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_LSHR %0, %1
- %5:_(s32) = G_ANYEXT %4(s8)
- RETURN %5(s32), implicit-def $arguments
-
-...
----
-name: lshr_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshr_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C1]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)
- ; CHECK-NEXT: RETURN [[LSHR]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %1:_(s16) = G_CONSTANT i16 13
- %3:_(s16) = G_LSHR %0, %1
- %4:_(s32) = G_ANYEXT %3(s16)
- RETURN %4(s32), implicit-def $arguments
-
-...
----
-name: lshrv_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshrv_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C1]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[AND1]](s32)
- ; CHECK-NEXT: RETURN [[LSHR]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_LSHR %0, %1
- %5:_(s32) = G_ANYEXT %4(s16)
- RETURN %5(s32), implicit-def $arguments
-
-...
----
-name: lshr_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshr_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ARGUMENT_i32_]], [[C]](s32)
- ; CHECK-NEXT: RETURN [[LSHR]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_CONSTANT i32 21
- %2:_(s32) = G_LSHR %0, %1
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: lshrv_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshrv_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]](s32)
- ; CHECK-NEXT: RETURN [[LSHR]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_LSHR %0, %1
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: lshr_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshr_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ARGUMENT_i32_]], [[C]](s32)
- ; CHECK-NEXT: RETURN [[LSHR]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s8) = G_CONSTANT i8 21
- %2:_(s32) = G_LSHR %0, %1
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: lshrv_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshrv_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ARGUMENT_i32_]], [[AND]](s32)
- ; CHECK-NEXT: RETURN [[LSHR]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %2(s32)
- %3:_(s32) = G_LSHR %0, %1
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: lshr_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshr_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ARGUMENT_i64_]], [[C]](s64)
- ; CHECK-NEXT: RETURN [[LSHR]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_CONSTANT i64 37
- %2:_(s64) = G_LSHR %0, %1
- RETURN %2(s64), implicit-def $arguments
-
-...
----
-name: lshrv_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshrv_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]](s64)
- ; CHECK-NEXT: RETURN [[LSHR]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_LSHR %0, %1
- RETURN %2(s64), implicit-def $arguments
-
-...
----
-name: lshr_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshr_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[C]], [[C1]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ARGUMENT_i64_]], [[AND]](s64)
- ; CHECK-NEXT: RETURN [[LSHR]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s8) = G_CONSTANT i8 37
- %2:_(s64) = G_LSHR %0, %1
- RETURN %2(s64), implicit-def $arguments
-
-...
----
-name: lshrv_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshrv_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ARGUMENT_i64_]], [[AND]](s64)
- ; CHECK-NEXT: RETURN [[LSHR]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %2(s32)
- %3:_(s64) = G_LSHR %0, %1
- RETURN %3(s64), implicit-def $arguments
-
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/rotl.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/rotl.mir
deleted file mode 100644
index 82c1bcf76ae5b..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/rotl.mir
+++ /dev/null
@@ -1,303 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
-
-
----
-name: rotl_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotl_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C2]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %1:_(s8) = G_CONSTANT i8 5
- %3:_(s8) = G_ROTL %0, %1
- %4:_(s32) = G_ANYEXT %3(s8)
- RETURN %4(s32), implicit-def $arguments
-
-...
----
-name: rotlv_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotlv_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[AND]](s32)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C2]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_ROTL %0, %1
- %5:_(s32) = G_ANYEXT %4(s8)
- RETURN %5(s32), implicit-def $arguments
-
-...
----
-name: rotl_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotl_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C2]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %1:_(s16) = G_CONSTANT i16 13
- %3:_(s16) = G_ROTL %0, %1
- %4:_(s32) = G_ANYEXT %3(s16)
- RETURN %4(s32), implicit-def $arguments
-
-...
----
-name: rotlv_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotlv_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[AND]](s32)
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C2]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND1]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[SHL]], [[LSHR]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_ROTL %0, %1
- %5:_(s32) = G_ANYEXT %4(s16)
- RETURN %5(s32), implicit-def $arguments
-
-...
----
-name: rotl_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotl_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
- ; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[ARGUMENT_i32_]], [[C]](s32)
- ; CHECK-NEXT: RETURN [[ROTL]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_CONSTANT i32 21
- %2:_(s32) = G_ROTL %0, %1
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: rotlv_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotlv_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]](s32)
- ; CHECK-NEXT: RETURN [[ROTL]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_ROTL %0, %1
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: rotl_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotl_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
- ; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[ARGUMENT_i32_]], [[C]](s32)
- ; CHECK-NEXT: RETURN [[ROTL]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s8) = G_CONSTANT i8 21
- %2:_(s32) = G_ROTL %0, %1
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: rotlv_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotlv_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C]]
- ; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[ARGUMENT_i32_]], [[AND]](s32)
- ; CHECK-NEXT: RETURN [[ROTL]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %2(s32)
- %3:_(s32) = G_ROTL %0, %1
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: rotl_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotl_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
- ; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(s64) = G_ROTL [[ARGUMENT_i64_]], [[C]](s64)
- ; CHECK-NEXT: RETURN [[ROTL]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_CONSTANT i64 37
- %2:_(s64) = G_ROTL %0, %1
- RETURN %2(s64), implicit-def $arguments
-
-...
----
-name: rotlv_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotlv_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(s64) = G_ROTL [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]](s64)
- ; CHECK-NEXT: RETURN [[ROTL]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_ROTL %0, %1
- RETURN %2(s64), implicit-def $arguments
-
-...
----
-name: rotl_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotl_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[C]], [[C1]]
- ; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(s64) = G_ROTL [[ARGUMENT_i64_]], [[AND]](s64)
- ; CHECK-NEXT: RETURN [[ROTL]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s8) = G_CONSTANT i8 37
- %2:_(s64) = G_ROTL %0, %1
- RETURN %2(s64), implicit-def $arguments
-
-...
----
-name: rotlv_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotlv_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
- ; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(s64) = G_ROTL [[ARGUMENT_i64_]], [[AND]](s64)
- ; CHECK-NEXT: RETURN [[ROTL]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %2(s32)
- %3:_(s64) = G_ROTL %0, %1
- RETURN %3(s64), implicit-def $arguments
-
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/rotr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/rotr.mir
deleted file mode 100644
index e8fc7e5db324e..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/rotr.mir
+++ /dev/null
@@ -1,303 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
-
-
----
-name: rotr_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotr_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C1]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C2]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[LSHR]], [[SHL]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %1:_(s8) = G_CONSTANT i8 5
- %3:_(s8) = G_ROTR %0, %1
- %4:_(s32) = G_ANYEXT %3(s8)
- RETURN %4(s32), implicit-def $arguments
-
-...
----
-name: rotrv_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotrv_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C1]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C2]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[AND2]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[LSHR]], [[SHL]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_ROTR %0, %1
- %5:_(s32) = G_ANYEXT %4(s8)
- RETURN %5(s32), implicit-def $arguments
-
-...
----
-name: rotr_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotr_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C1]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C2]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[LSHR]], [[SHL]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %1:_(s16) = G_CONSTANT i16 13
- %3:_(s16) = G_ROTR %0, %1
- %4:_(s32) = G_ANYEXT %3(s16)
- RETURN %4(s32), implicit-def $arguments
-
-...
----
-name: rotrv_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotrv_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C1]]
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C2]]
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
- ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[AND2]](s32)
- ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = disjoint G_OR [[LSHR]], [[SHL]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_ROTR %0, %1
- %5:_(s32) = G_ANYEXT %4(s16)
- RETURN %5(s32), implicit-def $arguments
-
-...
----
-name: rotr_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotr_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
- ; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[ARGUMENT_i32_]], [[C]](s32)
- ; CHECK-NEXT: RETURN [[ROTR]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_CONSTANT i32 21
- %2:_(s32) = G_ROTR %0, %1
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: rotrv_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotrv_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]](s32)
- ; CHECK-NEXT: RETURN [[ROTR]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_ROTR %0, %1
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: rotr_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotr_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
- ; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[ARGUMENT_i32_]], [[C]](s32)
- ; CHECK-NEXT: RETURN [[ROTR]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s8) = G_CONSTANT i8 21
- %2:_(s32) = G_ROTR %0, %1
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: rotrv_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotrv_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C]]
- ; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[ARGUMENT_i32_]], [[AND]](s32)
- ; CHECK-NEXT: RETURN [[ROTR]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %2(s32)
- %3:_(s32) = G_ROTR %0, %1
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: rotr_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotr_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
- ; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(s64) = G_ROTR [[ARGUMENT_i64_]], [[C]](s64)
- ; CHECK-NEXT: RETURN [[ROTR]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_CONSTANT i64 37
- %2:_(s64) = G_ROTR %0, %1
- RETURN %2(s64), implicit-def $arguments
-
-...
----
-name: rotrv_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotrv_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(s64) = G_ROTR [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]](s64)
- ; CHECK-NEXT: RETURN [[ROTR]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_ROTR %0, %1
- RETURN %2(s64), implicit-def $arguments
-
-...
----
-name: rotr_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotr_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[C]], [[C1]]
- ; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(s64) = G_ROTR [[ARGUMENT_i64_]], [[AND]](s64)
- ; CHECK-NEXT: RETURN [[ROTR]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s8) = G_CONSTANT i8 37
- %2:_(s64) = G_ROTR %0, %1
- RETURN %2(s64), implicit-def $arguments
-
-...
----
-name: rotrv_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotrv_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
- ; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(s64) = G_ROTR [[ARGUMENT_i64_]], [[AND]](s64)
- ; CHECK-NEXT: RETURN [[ROTR]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %2(s32)
- %3:_(s64) = G_ROTR %0, %1
- RETURN %3(s64), implicit-def $arguments
-
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sdiv.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sdiv.mir
deleted file mode 100644
index e7d3581e1c1b7..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sdiv.mir
+++ /dev/null
@@ -1,126 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=-sign-ext -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NO-SIGNEXT
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=+sign-ext -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,SIGNEXT
-
----
-name: sdiv_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: sdiv_i8
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
- ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; NO-SIGNEXT-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; NO-SIGNEXT-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_1]], [[C1]](s32)
- ; NO-SIGNEXT-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
- ; NO-SIGNEXT-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
- ; NO-SIGNEXT-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[SDIV]](s32)
- ; NO-SIGNEXT-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: sdiv_i8
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ARGUMENT_i32_]], 8
- ; SIGNEXT-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ARGUMENT_i32_1]], 8
- ; SIGNEXT-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
- ; SIGNEXT-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[SDIV]](s32)
- ; SIGNEXT-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_SDIV %0, %1
- %5:i32(s32) = G_ANYEXT %4(s8)
- RETURN %5(s32), implicit-def $arguments
-...
----
-name: sdiv_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: sdiv_i16
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
- ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; NO-SIGNEXT-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; NO-SIGNEXT-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_1]], [[C1]](s32)
- ; NO-SIGNEXT-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
- ; NO-SIGNEXT-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
- ; NO-SIGNEXT-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[SDIV]](s32)
- ; NO-SIGNEXT-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: sdiv_i16
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ARGUMENT_i32_]], 16
- ; SIGNEXT-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ARGUMENT_i32_1]], 16
- ; SIGNEXT-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
- ; SIGNEXT-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[SDIV]](s32)
- ; SIGNEXT-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_SDIV %0, %1
- %5:i32(s32) = G_ANYEXT %4(s16)
- RETURN %5(s32), implicit-def $arguments
-...
----
-name: sdiv_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sdiv_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: RETURN [[SDIV]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_SDIV %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: sdiv_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sdiv_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
- ; CHECK-NEXT: RETURN [[SDIV]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_SDIV %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sext.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sext.mir
deleted file mode 100644
index 7c9c704284356..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sext.mir
+++ /dev/null
@@ -1,138 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=-sign-ext -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NO-SIGNEXT
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=+sign-ext -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,SIGNEXT
-
----
-name: sext_i8_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: sext_i8_i32
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
- ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:i32(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; NO-SIGNEXT-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: sext_i8_i32
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:i32(s32) = G_SEXT_INREG [[ARGUMENT_i32_]], 8
- ; SIGNEXT-NEXT: RETURN [[SEXT_INREG]](s32), implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %1(s32)
- %2:i32(s32) = G_SEXT %0(s8)
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: sext_i8_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: sext_i8_i64
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
- ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
- ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C]](s64)
- ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:i64(s64) = G_ASHR [[SHL]], [[C]](s64)
- ; NO-SIGNEXT-NEXT: RETURN [[ASHR]](s64), implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: sext_i8_i64
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
- ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:i64(s64) = G_SEXT_INREG [[ANYEXT]], 8
- ; SIGNEXT-NEXT: RETURN [[SEXT_INREG]](s64), implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %1(s32)
- %2:i64(s64) = G_SEXT %0(s8)
- RETURN %2(s64), implicit-def $arguments
-...
----
-name: sext_i16_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: sext_i16_i32
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
- ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:i32(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; NO-SIGNEXT-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: sext_i16_i32
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:i32(s32) = G_SEXT_INREG [[ARGUMENT_i32_]], 16
- ; SIGNEXT-NEXT: RETURN [[SEXT_INREG]](s32), implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %1(s32)
- %2:i32(s32) = G_SEXT %0(s16)
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: sext_i16_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: sext_i16_i64
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
- ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
- ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C]](s64)
- ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:i64(s64) = G_ASHR [[SHL]], [[C]](s64)
- ; NO-SIGNEXT-NEXT: RETURN [[ASHR]](s64), implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: sext_i16_i64
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
- ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:i64(s64) = G_SEXT_INREG [[ANYEXT]], 16
- ; SIGNEXT-NEXT: RETURN [[SEXT_INREG]](s64), implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %1(s32)
- %2:i64(s64) = G_SEXT %0(s16)
- RETURN %2(s64), implicit-def $arguments
-...
----
-name: sext_i32_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sext_i32_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:i64(s64) = G_SEXT [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[SEXT]](s64), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i64(s64) = G_SEXT %0(s32)
- RETURN %1(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sext_inreg.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sext_inreg.mir
deleted file mode 100644
index 2d5daf7b906f3..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/sext_inreg.mir
+++ /dev/null
@@ -1,181 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=-sign-ext -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NO-SIGNEXT
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=+sign-ext -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,SIGNEXT
-
----
-name: sext_inreg_i1_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sext_inreg_i1_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %1, [[C]](s32)
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; CHECK-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_SEXT_INREG %1(s32), 1
- RETURN %1(s32), implicit-def $arguments
-...
----
-name: sext_inreg_i8_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: sext_inreg_i8_i32
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %1, [[C]](s32)
- ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; NO-SIGNEXT-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: sext_inreg_i8_i32
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SEXT_INREG]], 8
- ; SIGNEXT-NEXT: RETURN [[SEXT_INREG]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_SEXT_INREG %1(s32), 8
- RETURN %1(s32), implicit-def $arguments
-...
----
-name: sext_inreg_i16_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: sext_inreg_i16_i32
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %1, [[C]](s32)
- ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; NO-SIGNEXT-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: sext_inreg_i16_i32
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SEXT_INREG]], 16
- ; SIGNEXT-NEXT: RETURN [[SEXT_INREG]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_SEXT_INREG %1(s32), 16
- RETURN %1(s32), implicit-def $arguments
-...
-
----
-name: sext_inreg_i1_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sext_inreg_i1_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL %1, [[C]](s64)
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
- ; CHECK-NEXT: RETURN [[ASHR]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_SEXT_INREG %1(s64), 1
- RETURN %1(s64), implicit-def $arguments
-...
----
-name: sext_inreg_i8_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: sext_inreg_i8_i64
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
- ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL %1, [[C]](s64)
- ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
- ; NO-SIGNEXT-NEXT: RETURN [[ASHR]](s64), implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: sext_inreg_i8_i64
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SEXT_INREG]], 8
- ; SIGNEXT-NEXT: RETURN [[SEXT_INREG]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_SEXT_INREG %1(s64), 8
- RETURN %1(s64), implicit-def $arguments
-...
----
-name: sext_inreg_i16_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: sext_inreg_i16_i64
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
- ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL %1, [[C]](s64)
- ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
- ; NO-SIGNEXT-NEXT: RETURN [[ASHR]](s64), implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: sext_inreg_i16_i64
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SEXT_INREG]], 16
- ; SIGNEXT-NEXT: RETURN [[SEXT_INREG]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_SEXT_INREG %1(s64), 16
- RETURN %1(s64), implicit-def $arguments
-...
-
----
-name: sext_inreg_i32_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: sext_inreg_i32_i64
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL %1, [[C]](s64)
- ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
- ; NO-SIGNEXT-NEXT: RETURN [[ASHR]](s64), implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: sext_inreg_i32_i64
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SEXT_INREG]], 32
- ; SIGNEXT-NEXT: RETURN [[SEXT_INREG]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_SEXT_INREG %1(s64), 32
- RETURN %1(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/shl.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/shl.mir
deleted file mode 100644
index 25c75c551a1e7..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/shl.mir
+++ /dev/null
@@ -1,278 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: shl_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shl_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
- ; CHECK-NEXT: RETURN [[SHL]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %1:_(s8) = G_CONSTANT i8 5
- %3:_(s8) = G_SHL %0, %1
- %4:_(s32) = G_ANYEXT %3(s8)
- RETURN %4(s32), implicit-def $arguments
-
-...
----
-name: shlv_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shlv_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[AND]](s32)
- ; CHECK-NEXT: RETURN [[SHL]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_SHL %0, %1
- %5:_(s32) = G_ANYEXT %4(s8)
- RETURN %5(s32), implicit-def $arguments
-
-...
----
-name: shl_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shl_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
- ; CHECK-NEXT: RETURN [[SHL]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %1:_(s16) = G_CONSTANT i16 13
- %3:_(s16) = G_SHL %0, %1
- %4:_(s32) = G_ANYEXT %3(s16)
- RETURN %4(s32), implicit-def $arguments
-
-...
----
-name: shlv_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shlv_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[AND]](s32)
- ; CHECK-NEXT: RETURN [[SHL]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_SHL %0, %1
- %5:_(s32) = G_ANYEXT %4(s16)
- RETURN %5(s32), implicit-def $arguments
-
-...
----
-name: shl_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shl_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
- ; CHECK-NEXT: RETURN [[SHL]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_CONSTANT i32 21
- %2:_(s32) = G_SHL %0, %1
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: shlv_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shlv_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]](s32)
- ; CHECK-NEXT: RETURN [[SHL]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_SHL %0, %1
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: shl_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shl_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
- ; CHECK-NEXT: RETURN [[SHL]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s8) = G_CONSTANT i8 21
- %2:_(s32) = G_SHL %0, %1
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: shlv_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shlv_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[AND]](s32)
- ; CHECK-NEXT: RETURN [[SHL]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %2(s32)
- %3:_(s32) = G_SHL %0, %1
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: shl_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shl_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ARGUMENT_i64_]], [[C]](s64)
- ; CHECK-NEXT: RETURN [[SHL]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_CONSTANT i64 37
- %2:_(s64) = G_SHL %0, %1
- RETURN %2(s64), implicit-def $arguments
-
-...
----
-name: shlv_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shlv_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]](s64)
- ; CHECK-NEXT: RETURN [[SHL]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_SHL %0, %1
- RETURN %2(s64), implicit-def $arguments
-
-...
----
-name: shl_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shl_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 37
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[C]], [[C1]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ARGUMENT_i64_]], [[AND]](s64)
- ; CHECK-NEXT: RETURN [[SHL]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s8) = G_CONSTANT i8 37
- %2:_(s64) = G_SHL %0, %1
- RETURN %2(s64), implicit-def $arguments
-
-...
----
-name: shlv_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shlv_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ARGUMENT_i64_]], [[AND]](s64)
- ; CHECK-NEXT: RETURN [[SHL]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %2(s32)
- %3:_(s64) = G_SHL %0, %1
- RETURN %3(s64), implicit-def $arguments
-
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/srem.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/srem.mir
deleted file mode 100644
index e6d9d2c5bad2d..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/srem.mir
+++ /dev/null
@@ -1,126 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=-sign-ext -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NO-SIGNEXT
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=+sign-ext -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,SIGNEXT
-
----
-name: srem_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: srem_i8
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
- ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; NO-SIGNEXT-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; NO-SIGNEXT-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_1]], [[C1]](s32)
- ; NO-SIGNEXT-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
- ; NO-SIGNEXT-NEXT: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
- ; NO-SIGNEXT-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[SREM]](s32)
- ; NO-SIGNEXT-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: srem_i8
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ARGUMENT_i32_]], 8
- ; SIGNEXT-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ARGUMENT_i32_1]], 8
- ; SIGNEXT-NEXT: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[SEXT_INREG]], [[SEXT_INREG1]]
- ; SIGNEXT-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[SREM]](s32)
- ; SIGNEXT-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_SREM %0, %1
- %5:i32(s32) = G_ANYEXT %4(s8)
- RETURN %5(s32), implicit-def $arguments
-...
----
-name: srem_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: srem_i16
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; NO-SIGNEXT-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
- ; NO-SIGNEXT-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; NO-SIGNEXT-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; NO-SIGNEXT-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ARGUMENT_i32_1]], [[C1]](s32)
- ; NO-SIGNEXT-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
- ; NO-SIGNEXT-NEXT: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
- ; NO-SIGNEXT-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[SREM]](s32)
- ; NO-SIGNEXT-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: srem_i16
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; SIGNEXT-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ARGUMENT_i32_]], 16
- ; SIGNEXT-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ARGUMENT_i32_1]], 16
- ; SIGNEXT-NEXT: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[SEXT_INREG]], [[SEXT_INREG1]]
- ; SIGNEXT-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[SREM]](s32)
- ; SIGNEXT-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_SREM %0, %1
- %5:i32(s32) = G_ANYEXT %4(s16)
- RETURN %5(s32), implicit-def $arguments
-...
----
-name: srem_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: srem_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: RETURN [[SREM]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_SREM %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: srem_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: srem_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[SREM:%[0-9]+]]:_(s64) = G_SREM [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
- ; CHECK-NEXT: RETURN [[SREM]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_SREM %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/udiv.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/udiv.mir
deleted file mode 100644
index 9d547bf0a110a..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/udiv.mir
+++ /dev/null
@@ -1,99 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: udiv_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: udiv_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C1]]
- ; CHECK-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[UDIV]](s32)
- ; CHECK-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_UDIV %0, %1
- %5:i32(s32) = G_ANYEXT %4(s8)
- RETURN %5(s32), implicit-def $arguments
-...
----
-name: udiv_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: udiv_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C1]]
- ; CHECK-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[UDIV]](s32)
- ; CHECK-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_UDIV %0, %1
- %5:i32(s32) = G_ANYEXT %4(s16)
- RETURN %5(s32), implicit-def $arguments
-...
----
-name: udiv_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: udiv_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: RETURN [[UDIV]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_UDIV %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: udiv_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: udiv_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
- ; CHECK-NEXT: RETURN [[UDIV]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_UDIV %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/urem.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/urem.mir
deleted file mode 100644
index 068023509eb07..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/urem.mir
+++ /dev/null
@@ -1,99 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: urem_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: urem_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C1]]
- ; CHECK-NEXT: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[AND]], [[AND1]]
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[UREM]](s32)
- ; CHECK-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_UREM %0, %1
- %5:i32(s32) = G_ANYEXT %4(s8)
- RETURN %5(s32), implicit-def $arguments
-...
----
-name: urem_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: urem_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ARGUMENT_i32_1]], [[C1]]
- ; CHECK-NEXT: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[AND]], [[AND1]]
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:i32(s32) = COPY [[UREM]](s32)
- ; CHECK-NEXT: RETURN [[COPY]](s32), implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_UREM %0, %1
- %5:i32(s32) = G_ANYEXT %4(s16)
- RETURN %5(s32), implicit-def $arguments
-...
----
-name: urem_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: urem_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: RETURN [[UREM]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_UREM %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: urem_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: urem_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[UREM:%[0-9]+]]:_(s64) = G_UREM [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
- ; CHECK-NEXT: RETURN [[UREM]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_UREM %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/zext.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/zext.mir
deleted file mode 100644
index 71c494bc17dc7..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/zext.mir
+++ /dev/null
@@ -1,103 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: zext_i8_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: zext_i8_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:i32(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
- ; CHECK-NEXT: RETURN [[AND]](s32), implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %1(s32)
- %2:i32(s32) = G_ZEXT %0(s8)
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: zext_i8_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: zext_i8_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK-NEXT: [[AND:%[0-9]+]]:i64(s64) = G_AND [[ANYEXT]], [[C]]
- ; CHECK-NEXT: RETURN [[AND]](s64), implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %1(s32)
- %2:i64(s64) = G_ZEXT %0(s8)
- RETURN %2(s64), implicit-def $arguments
-...
----
-name: zext_i16_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: zext_i16_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:i32(s32) = G_AND [[ARGUMENT_i32_]], [[C]]
- ; CHECK-NEXT: RETURN [[AND]](s32), implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %1(s32)
- %2:i32(s32) = G_ZEXT %0(s16)
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: zext_i16_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: zext_i16_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
- ; CHECK-NEXT: [[AND:%[0-9]+]]:i64(s64) = G_AND [[ANYEXT]], [[C]]
- ; CHECK-NEXT: RETURN [[AND]](s64), implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %1(s32)
- %2:i64(s64) = G_ZEXT %0(s16)
- RETURN %2(s64), implicit-def $arguments
-...
----
-name: zext_i32_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: zext_i32_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:i64(s64) = G_ZEXT [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[ZEXT]](s64), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i64(s64) = G_ZEXT %0(s32)
- RETURN %1(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/bitwise.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/bitwise.mir
deleted file mode 100644
index 9657732d43aaf..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/bitwise.mir
+++ /dev/null
@@ -1,463 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: and_i32
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: and_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[AND:%[0-9]+]]:i32regbank(s32) = G_AND [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: RETURN [[AND]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_AND %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: and_i64
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: and_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[AND:%[0-9]+]]:i64regbank(s64) = G_AND [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
- ; CHECK-NEXT: RETURN [[AND]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_AND %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
-
----
-name: or_i32
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: or_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[OR:%[0-9]+]]:i32regbank(s32) = G_OR [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: RETURN [[OR]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_OR %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: or_i64
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: or_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[OR:%[0-9]+]]:i64regbank(s64) = G_OR [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
- ; CHECK-NEXT: RETURN [[OR]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_OR %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
-
----
-name: xor_i32
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: xor_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:i32regbank(s32) = G_XOR [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: RETURN [[XOR]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_XOR %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: xor_i64
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: xor_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:i64regbank(s64) = G_XOR [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
- ; CHECK-NEXT: RETURN [[XOR]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_XOR %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
-
----
-name: shl_i32
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shl_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:i32regbank(s32) = G_CONSTANT i32 5
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:i32regbank(s32) = G_SHL [[ARGUMENT_i32_]], [[C]](s32)
- ; CHECK-NEXT: RETURN [[SHL]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_CONSTANT i32 5
- %2:_(s32) = G_SHL %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: shl_i64
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shl_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:i64regbank(s64) = G_CONSTANT i64 37
- ; CHECK-NEXT: [[SHL:%[0-9]+]]:i64regbank(s64) = G_SHL [[ARGUMENT_i64_]], [[C]](s64)
- ; CHECK-NEXT: RETURN [[SHL]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_CONSTANT i64 37
- %2:_(s64) = G_SHL %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
-
----
-name: ashr_i32
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ashr_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:i32regbank(s32) = G_CONSTANT i32 5
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:i32regbank(s32) = G_ASHR [[ARGUMENT_i32_]], [[C]](s32)
- ; CHECK-NEXT: RETURN [[ASHR]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_CONSTANT i32 5
- %2:_(s32) = G_ASHR %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: ashr_i64
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ashr_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:i64regbank(s64) = G_CONSTANT i64 37
- ; CHECK-NEXT: [[ASHR:%[0-9]+]]:i64regbank(s64) = G_ASHR [[ARGUMENT_i64_]], [[C]](s64)
- ; CHECK-NEXT: RETURN [[ASHR]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_CONSTANT i64 37
- %2:_(s64) = G_ASHR %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
-
----
-name: lshr_i32
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshr_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:i32regbank(s32) = G_CONSTANT i32 5
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:i32regbank(s32) = G_LSHR [[ARGUMENT_i32_]], [[C]](s32)
- ; CHECK-NEXT: RETURN [[LSHR]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_CONSTANT i32 5
- %2:_(s32) = G_LSHR %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: lshr_i64
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshr_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[C:%[0-9]+]]:i64regbank(s64) = G_CONSTANT i64 37
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:i64regbank(s64) = G_LSHR [[ARGUMENT_i64_]], [[C]](s64)
- ; CHECK-NEXT: RETURN [[LSHR]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_CONSTANT i64 37
- %2:_(s64) = G_LSHR %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
-
----
-name: ctlz_i32
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:i32regbank(s32) = G_CTLZ [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[CTLZ]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_CTLZ %0
- RETURN %1(s32), implicit-def $arguments
-...
----
-name: ctlz_i64
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTLZ:%[0-9]+]]:i64regbank(s64) = G_CTLZ [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: RETURN [[CTLZ]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_CTLZ %0
- RETURN %1(s64), implicit-def $arguments
-...
-
----
-name: cttz_i32
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: cttz_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:i32regbank(s32) = G_CTTZ [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[CTTZ]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_CTTZ %0
- RETURN %1(s32), implicit-def $arguments
-...
----
-name: cttz_i64
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: cttz_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTTZ:%[0-9]+]]:i64regbank(s64) = G_CTTZ [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: RETURN [[CTTZ]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_CTTZ %0
- RETURN %1(s64), implicit-def $arguments
-...
-
----
-name: ctpop_i32
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctpop_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:i32regbank(s32) = G_CTPOP [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[CTPOP]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_CTPOP %0
- RETURN %1(s32), implicit-def $arguments
-...
----
-name: ctpop_i64
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctpop_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:i64regbank(s64) = G_CTPOP [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: RETURN [[CTPOP]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_CTPOP %0
- RETURN %1(s64), implicit-def $arguments
-...
-
----
-name: rotl_i32
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotl_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ROTL:%[0-9]+]]:i32regbank(s32) = G_ROTL [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]](s32)
- ; CHECK-NEXT: RETURN [[ROTL]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_ROTL %0, %1(s32)
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: rotl_i64
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotl_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[ROTL:%[0-9]+]]:i64regbank(s64) = G_ROTL [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]](s64)
- ; CHECK-NEXT: RETURN [[ROTL]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_ROTL %0, %1(s64)
- RETURN %2(s64), implicit-def $arguments
-...
-
----
-name: rotr_i32
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotr_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ROTR:%[0-9]+]]:i32regbank(s32) = G_ROTR [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]](s32)
- ; CHECK-NEXT: RETURN [[ROTR]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_ROTR %0, %1(s32)
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: rotr_i64
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: rotr_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[ROTR:%[0-9]+]]:i64regbank(s64) = G_ROTR [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]](s64)
- ; CHECK-NEXT: RETURN [[ROTR]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_ROTR %0, %1(s64)
- RETURN %2(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/consts.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/consts.mir
deleted file mode 100644
index 3cf45bbcf3702..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/consts.mir
+++ /dev/null
@@ -1,72 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: const_i32
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: const_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:i32regbank(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: RETURN [[C]](s32), implicit-def $arguments
- %0:_(s32) = G_CONSTANT i32 0
- RETURN %0(s32), implicit-def $arguments
-...
----
-name: const_i64
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: const_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[C:%[0-9]+]]:i64regbank(s64) = G_CONSTANT i64 0
- ; CHECK-NEXT: RETURN [[C]](s64), implicit-def $arguments
- %0:_(s64) = G_CONSTANT i64 0
- RETURN %0(s64), implicit-def $arguments
-...
-
----
-name: implicit_i32
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: implicit_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:i32regbank(s32) = G_IMPLICIT_DEF
- ; CHECK-NEXT: RETURN [[DEF]](s32), implicit-def $arguments
- %0:_(s32) = G_IMPLICIT_DEF
- RETURN %0(s32), implicit-def $arguments
-...
----
-name: implicit_i64
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: implicit_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:i64regbank(s64) = G_IMPLICIT_DEF
- ; CHECK-NEXT: RETURN [[DEF]](s64), implicit-def $arguments
- %0:_(s64) = G_IMPLICIT_DEF
- RETURN %0(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/ext-trunc.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/ext-trunc.mir
deleted file mode 100644
index a95bb61143547..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/ext-trunc.mir
+++ /dev/null
@@ -1,177 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: anyext
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: anyext
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:i64regbank(s64) = G_ANYEXT [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[ANYEXT]](s64), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s64) = G_ANYEXT %0
- RETURN %1(s64), implicit-def $arguments
-...
----
-name: sext
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sext
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[SEXT:%[0-9]+]]:i64regbank(s64) = G_SEXT [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[SEXT]](s64), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s64) = G_SEXT %0
- RETURN %1(s64), implicit-def $arguments
-...
----
-name: zext
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: zext
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:i64regbank(s64) = G_ZEXT [[ARGUMENT_i32_]](s32)
- ; CHECK-NEXT: RETURN [[ZEXT]](s64), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s64) = G_ZEXT %0
- RETURN %1(s64), implicit-def $arguments
-...
----
-name: trunc
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: trunc
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:i32regbank(s32) = G_TRUNC [[ARGUMENT_i64_]](s64)
- ; CHECK-NEXT: RETURN [[TRUNC]](s32), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s32) = G_TRUNC %0
- RETURN %1(s32), implicit-def $arguments
-...
-
----
-name: sext_inreg_i32_8
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sext_inreg_i32_8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:i32regbank(s32) = G_SEXT_INREG [[ARGUMENT_i32_]], 8
- ; CHECK-NEXT: RETURN [[SEXT_INREG]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_SEXT_INREG %0, 8
- RETURN %1(s32), implicit-def $arguments
-...
----
-name: sext_inreg_i64_8
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sext_inreg_i64_8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:i64regbank(s64) = G_SEXT_INREG [[ARGUMENT_i64_]], 8
- ; CHECK-NEXT: RETURN [[SEXT_INREG]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_SEXT_INREG %0, 8
- RETURN %1(s64), implicit-def $arguments
-...
-
----
-name: sext_inreg_i32_16
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sext_inreg_i32_16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:i32regbank(s32) = G_SEXT_INREG [[ARGUMENT_i32_]], 16
- ; CHECK-NEXT: RETURN [[SEXT_INREG]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_SEXT_INREG %0, 16
- RETURN %1(s32), implicit-def $arguments
-...
----
-name: sext_inreg_i64_16
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sext_inreg_i64_16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:i64regbank(s64) = G_SEXT_INREG [[ARGUMENT_i64_]], 16
- ; CHECK-NEXT: RETURN [[SEXT_INREG]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_SEXT_INREG %0, 16
- RETURN %1(s64), implicit-def $arguments
-...
-
----
-name: sext_inreg_i64_32
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sext_inreg_i64_32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:i64regbank(s64) = G_SEXT_INREG [[ARGUMENT_i64_]], 32
- ; CHECK-NEXT: RETURN [[SEXT_INREG]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_SEXT_INREG %0, 32
- RETURN %1(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/int-arithmetic.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/int-arithmetic.mir
deleted file mode 100644
index a2118b9744051..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/int-arithmetic.mir
+++ /dev/null
@@ -1,303 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: add_i32
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: add_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:i32regbank(s32) = G_ADD [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: RETURN [[ADD]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_ADD %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: add_i64
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: add_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[ADD:%[0-9]+]]:i64regbank(s64) = G_ADD [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
- ; CHECK-NEXT: RETURN [[ADD]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_ADD %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
-
----
-name: sub_i32
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sub_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:i32regbank(s32) = G_SUB [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: RETURN [[SUB]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_SUB %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: sub_i64
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sub_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[SUB:%[0-9]+]]:i64regbank(s64) = G_SUB [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
- ; CHECK-NEXT: RETURN [[SUB]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_SUB %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
-
----
-name: mul_i32
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: mul_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:i32regbank(s32) = G_MUL [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: RETURN [[MUL]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_MUL %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: mul_i64
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: mul_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[MUL:%[0-9]+]]:i64regbank(s64) = G_MUL [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
- ; CHECK-NEXT: RETURN [[MUL]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_MUL %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
-
----
-name: udiv_i32
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: udiv_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[UDIV:%[0-9]+]]:i32regbank(s32) = G_UDIV [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: RETURN [[UDIV]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_UDIV %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: udiv_i64
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: udiv_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[UDIV:%[0-9]+]]:i64regbank(s64) = G_UDIV [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
- ; CHECK-NEXT: RETURN [[UDIV]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_UDIV %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
-
----
-name: sdiv_i32
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sdiv_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[SDIV:%[0-9]+]]:i32regbank(s32) = G_SDIV [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: RETURN [[SDIV]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_SDIV %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: sdiv_i64
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sdiv_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[SDIV:%[0-9]+]]:i64regbank(s64) = G_SDIV [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
- ; CHECK-NEXT: RETURN [[SDIV]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_SDIV %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
-
----
-name: urem_i32
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: urem_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[UREM:%[0-9]+]]:i32regbank(s32) = G_UREM [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: RETURN [[UREM]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_UREM %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: urem_i64
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: urem_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[UREM:%[0-9]+]]:i64regbank(s64) = G_UREM [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
- ; CHECK-NEXT: RETURN [[UREM]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_UREM %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
-
----
-name: srem_i32
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: srem_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[SREM:%[0-9]+]]:i32regbank(s32) = G_SREM [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]]
- ; CHECK-NEXT: RETURN [[SREM]](s32), implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_SREM %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: srem_i64
-alignment: 1
-legalized: true
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: srem_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[SREM:%[0-9]+]]:i64regbank(s64) = G_SREM [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]]
- ; CHECK-NEXT: RETURN [[SREM]](s64), implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_SREM %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
>From b99afa19b594f9522dcc424a9067b5e7df45a155 Mon Sep 17 00:00:00 2001
From: Demetrius Kanios <demetrius at kanios.net>
Date: Wed, 8 Apr 2026 14:09:55 -0700
Subject: [PATCH 6/7] Migrate most new tests to LLVM IR
---
.../WebAssembly/GlobalISel/gmir/add.mir | 217 ----------
.../WebAssembly/GlobalISel/gmir/and.mir | 116 ------
.../WebAssembly/GlobalISel/gmir/ashr.mir | 331 ---------------
.../WebAssembly/GlobalISel/gmir/constant.mir | 145 -------
.../GlobalISel/gmir/ctlz_zero_undef.mir | 152 -------
.../WebAssembly/GlobalISel/gmir/ctpop.mir | 148 -------
.../GlobalISel/gmir/cttz_zero_undef.mir | 148 -------
.../WebAssembly/GlobalISel/gmir/fshl.mir | 382 ------------------
.../WebAssembly/GlobalISel/gmir/fshr.mir | 378 -----------------
.../WebAssembly/GlobalISel/gmir/lshr.mir | 286 -------------
.../WebAssembly/GlobalISel/gmir/mul.mir | 89 ----
.../WebAssembly/GlobalISel/gmir/or.mir | 117 ------
.../WebAssembly/GlobalISel/gmir/sdiv.mir | 122 ------
.../WebAssembly/GlobalISel/gmir/sext.mir | 138 -------
.../GlobalISel/gmir/sext_inreg.mir | 181 ---------
.../WebAssembly/GlobalISel/gmir/shl.mir | 278 -------------
.../WebAssembly/GlobalISel/gmir/srem.mir | 122 ------
.../WebAssembly/GlobalISel/gmir/sub.mir | 89 ----
.../WebAssembly/GlobalISel/gmir/trunc.mir | 95 -----
.../WebAssembly/GlobalISel/gmir/udiv.mir | 97 -----
.../WebAssembly/GlobalISel/gmir/urem.mir | 97 -----
.../WebAssembly/GlobalISel/gmir/xor.mir | 116 ------
.../WebAssembly/GlobalISel/gmir/zext.mir | 103 -----
.../GlobalISel/instructions/add.ll | 141 +++++++
.../GlobalISel/instructions/and.ll | 64 +++
.../{gmir => instructions}/anyext.mir | 3 +-
.../GlobalISel/instructions/ashr.ll | 183 +++++++++
.../GlobalISel/instructions/ashr.mir | 93 +++++
.../GlobalISel/instructions/constant.ll | 85 ++++
.../GlobalISel/instructions/ctlz.ll | 113 ++++++
.../{gmir => instructions}/ctlz.mir | 103 ++---
.../GlobalISel/instructions/ctpop.ll | 57 +++
.../GlobalISel/instructions/ctpop.mir | 62 +++
.../GlobalISel/instructions/cttz.ll | 105 +++++
.../{gmir => instructions}/cttz.mir | 97 ++---
.../GlobalISel/instructions/fshl.ll | 221 ++++++++++
.../GlobalISel/instructions/fshl.mir | 128 ++++++
.../GlobalISel/instructions/fshr.ll | 201 +++++++++
.../GlobalISel/instructions/fshr.mir | 128 ++++++
.../{gmir => instructions}/implicit_def.mir | 0
.../GlobalISel/instructions/lshr.ll | 118 ++++++
.../GlobalISel/instructions/lshr.mir | 93 +++++
.../GlobalISel/instructions/mul.ll | 52 +++
.../WebAssembly/GlobalISel/instructions/or.ll | 64 +++
.../{gmir => instructions}/rotl.mir | 0
.../{gmir => instructions}/rotr.mir | 0
.../GlobalISel/instructions/sdiv.ll | 56 +++
.../GlobalISel/instructions/sext.ll | 154 +++++++
.../GlobalISel/instructions/shl.ll | 104 +++++
.../GlobalISel/instructions/shl.mir | 93 +++++
.../GlobalISel/instructions/srem.ll | 56 +++
.../GlobalISel/instructions/sub.ll | 52 +++
.../GlobalISel/instructions/trunc.ll | 75 ++++
.../GlobalISel/instructions/udiv.ll | 60 +++
.../GlobalISel/instructions/urem.ll | 60 +++
.../GlobalISel/instructions/xor.ll | 64 +++
.../GlobalISel/instructions/zext.ll | 88 ++++
57 files changed, 2843 insertions(+), 4077 deletions(-)
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/add.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/and.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ashr.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/constant.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ctlz_zero_undef.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ctpop.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/cttz_zero_undef.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/fshl.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/fshr.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/lshr.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/mul.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/or.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sdiv.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sext.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sext_inreg.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/shl.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/srem.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sub.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/trunc.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/udiv.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/urem.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/xor.mir
delete mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/zext.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/add.ll
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/and.ll
rename llvm/test/CodeGen/WebAssembly/GlobalISel/{gmir => instructions}/anyext.mir (97%)
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.ll
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/constant.ll
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctlz.ll
rename llvm/test/CodeGen/WebAssembly/GlobalISel/{gmir => instructions}/ctlz.mir (60%)
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctpop.ll
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctpop.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/cttz.ll
rename llvm/test/CodeGen/WebAssembly/GlobalISel/{gmir => instructions}/cttz.mir (65%)
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshl.ll
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshl.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshr.ll
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshr.mir
rename llvm/test/CodeGen/WebAssembly/GlobalISel/{gmir => instructions}/implicit_def.mir (100%)
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.ll
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/mul.ll
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/or.ll
rename llvm/test/CodeGen/WebAssembly/GlobalISel/{gmir => instructions}/rotl.mir (100%)
rename llvm/test/CodeGen/WebAssembly/GlobalISel/{gmir => instructions}/rotr.mir (100%)
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/sdiv.ll
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/sext.ll
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.ll
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.mir
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/srem.ll
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/sub.ll
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/trunc.ll
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/udiv.ll
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/urem.ll
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/xor.ll
create mode 100644 llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/zext.ll
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/add.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/add.mir
deleted file mode 100644
index 679ca0da196db..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/add.mir
+++ /dev/null
@@ -1,217 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=-sign-ext -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NO-SIGNEXT
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=+sign-ext -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,SIGNEXT
-
----
-name: add_i8_zext
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: add_i8_zext
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ADD_I32_:%[0-9]+]]:i32 = ADD_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ADD_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[AND_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_ADD %0, %1
- %5:i32(s32) = G_ZEXT %4(s8)
- RETURN %5(s32), implicit-def $arguments
-...
-
----
-name: add_i8_sext
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: add_i8_sext
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[ADD_I32_:%[0-9]+]]:i32 = ADD_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 24, implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ADD_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: add_i8_sext
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; SIGNEXT-NEXT: [[ADD_I32_:%[0-9]+]]:i32 = ADD_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: [[I32_EXTEND8_S_I32_:%[0-9]+]]:i32 = I32_EXTEND8_S_I32 [[ADD_I32_]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: RETURN [[I32_EXTEND8_S_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_ADD %0, %1
- %5:i32(s32) = G_SEXT %4(s8)
- RETURN %5(s32), implicit-def $arguments
-...
-
----
-name: add_i8_aext
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: add_i8_aext
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ADD_I32_:%[0-9]+]]:i32 = ADD_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[ADD_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_ADD %0, %1
- %5:i32(s32) = G_ANYEXT %4(s8)
- RETURN %5(s32), implicit-def $arguments
-...
-
----
-name: add_i16_zext
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: add_i16_zext
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ADD_I32_:%[0-9]+]]:i32 = ADD_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ADD_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[AND_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_ADD %0, %1
- %5:i32(s32) = G_ZEXT %4(s16)
- RETURN %5(s32), implicit-def $arguments
-...
-
----
-name: add_i16_sext
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: add_i16_sext
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[ADD_I32_:%[0-9]+]]:i32 = ADD_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 16, implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ADD_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: add_i16_sext
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; SIGNEXT-NEXT: [[ADD_I32_:%[0-9]+]]:i32 = ADD_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: [[I32_EXTEND16_S_I32_:%[0-9]+]]:i32 = I32_EXTEND16_S_I32 [[ADD_I32_]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: RETURN [[I32_EXTEND16_S_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_ADD %0, %1
- %5:i32(s32) = G_SEXT %4(s16)
- RETURN %5(s32), implicit-def $arguments
-...
-
----
-name: add_i16_aext
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: add_i16_aext
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ADD_I32_:%[0-9]+]]:i32 = ADD_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[ADD_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_ADD %0, %1
- %5:i32(s32) = G_ANYEXT %4(s16)
- RETURN %5(s32), implicit-def $arguments
-...
-
----
-name: add_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: add_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ADD_I32_:%[0-9]+]]:i32 = ADD_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[ADD_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_ADD %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
-
----
-name: add_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: add_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[ADD_I64_:%[0-9]+]]:i64 = ADD_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[ADD_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_ADD %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/and.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/and.mir
deleted file mode 100644
index f6b638e577027..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/and.mir
+++ /dev/null
@@ -1,116 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: and_i1
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: and_i1
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[AND_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s1) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s1) = G_TRUNC %3(s32)
- %4:_(s1) = G_AND %1, %0
- %5:_(s32) = G_ANYEXT %4(s1)
- RETURN %5(s32), implicit-def $arguments
-
-...
----
-name: and_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: and_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[AND_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_AND %1, %0
- %5:_(s32) = G_ANYEXT %4(s8)
- RETURN %5(s32), implicit-def $arguments
-
-...
----
-name: and_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: and_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[AND_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_AND %1, %0
- %5:_(s32) = G_ANYEXT %4(s16)
- RETURN %5(s32), implicit-def $arguments
-
-...
----
-name: and_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: and_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[AND_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_AND %1, %0
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: and_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: and_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[ARGUMENT_i64_1]], [[ARGUMENT_i64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[AND_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_AND %1, %0
- RETURN %2(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ashr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ashr.mir
deleted file mode 100644
index ae0fb5d277094..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ashr.mir
+++ /dev/null
@@ -1,331 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=-sign-ext -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NO-SIGNEXT
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=+sign-ext -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,SIGNEXT
-
----
-name: ashr_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: ashr_i8
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 5, implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 24, implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_1]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHR_S_I32_1:%[0-9]+]]:i32 = SHR_S_I32 [[SHR_S_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I32_1]], implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: ashr_i8
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 5, implicit-def dead $arguments
- ; SIGNEXT-NEXT: [[I32_EXTEND8_S_I32_:%[0-9]+]]:i32 = I32_EXTEND8_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[I32_EXTEND8_S_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %1:_(s8) = G_CONSTANT i8 5
- %3:_(s8) = G_ASHR %0, %1
- %4:_(s32) = G_ANYEXT %3(s8)
- RETURN %4(s32), implicit-def $arguments
-
-...
----
-name: ashrv_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: ashrv_i8
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 24, implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHR_S_I32_1:%[0-9]+]]:i32 = SHR_S_I32 [[SHR_S_I32_]], [[AND_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I32_1]], implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: ashrv_i8
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; SIGNEXT-NEXT: [[I32_EXTEND8_S_I32_:%[0-9]+]]:i32 = I32_EXTEND8_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
- ; SIGNEXT-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[I32_EXTEND8_S_I32_]], [[AND_I32_]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_ASHR %0, %1
- %5:_(s32) = G_ANYEXT %4(s8)
- RETURN %5(s32), implicit-def $arguments
-
-...
----
-name: ashr_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: ashr_i16
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 13, implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 16, implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_1]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHR_S_I32_1:%[0-9]+]]:i32 = SHR_S_I32 [[SHR_S_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I32_1]], implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: ashr_i16
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 13, implicit-def dead $arguments
- ; SIGNEXT-NEXT: [[I32_EXTEND16_S_I32_:%[0-9]+]]:i32 = I32_EXTEND16_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[I32_EXTEND16_S_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %1:_(s16) = G_CONSTANT i16 13
- %3:_(s16) = G_ASHR %0, %1
- %4:_(s32) = G_ANYEXT %3(s16)
- RETURN %4(s32), implicit-def $arguments
-
-...
----
-name: ashrv_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: ashrv_i16
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 16, implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHR_S_I32_1:%[0-9]+]]:i32 = SHR_S_I32 [[SHR_S_I32_]], [[AND_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I32_1]], implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: ashrv_i16
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; SIGNEXT-NEXT: [[I32_EXTEND16_S_I32_:%[0-9]+]]:i32 = I32_EXTEND16_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
- ; SIGNEXT-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[I32_EXTEND16_S_I32_]], [[AND_I32_]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_ASHR %0, %1
- %5:_(s32) = G_ANYEXT %4(s16)
- RETURN %5(s32), implicit-def $arguments
-
-...
----
-name: ashr_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ashr_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_CONSTANT i32 21
- %2:_(s32) = G_ASHR %0, %1
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: ashrv_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ashrv_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_ASHR %0, %1
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: ashr_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ashr_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s8) = G_CONSTANT i8 21
- %2:_(s32) = G_ASHR %0, %1
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: ashrv_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ashrv_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[ARGUMENT_i32_]], [[AND_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %2(s32)
- %3:_(s32) = G_ASHR %0, %1
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: ashr_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ashr_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_S_I64_:%[0-9]+]]:i64 = SHR_S_I64 [[ARGUMENT_i64_]], [[CONST_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHR_S_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_CONSTANT i64 37
- %2:_(s64) = G_ASHR %0, %1
- RETURN %2(s64), implicit-def $arguments
-
-...
----
-name: ashrv_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ashrv_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[SHR_S_I64_:%[0-9]+]]:i64 = SHR_S_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHR_S_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_ASHR %0, %1
- RETURN %2(s64), implicit-def $arguments
-
-...
----
-name: ashr_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ashr_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_]], [[CONST_I64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_S_I64_:%[0-9]+]]:i64 = SHR_S_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHR_S_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s8) = G_CONSTANT i8 37
- %2:_(s64) = G_ASHR %0, %1
- RETURN %2(s64), implicit-def $arguments
-
-...
----
-name: ashrv_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ashrv_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_S_I64_:%[0-9]+]]:i64 = SHR_S_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHR_S_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %2(s32)
- %3:_(s64) = G_ASHR %0, %1
- RETURN %3(s64), implicit-def $arguments
-
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/constant.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/constant.mir
deleted file mode 100644
index d5bff2a5a80cb..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/constant.mir
+++ /dev/null
@@ -1,145 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: const_i8_zext
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: const_i8_zext
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CONST_I32_]], implicit-def $arguments
- %0:_(s8) = G_CONSTANT i8 255
- %1:_(s32) = G_ZEXT %0(s8)
- RETURN %1(s32), implicit-def $arguments
-...
-
----
-name: const_i8_sext
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: const_i8_sext
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CONST_I32_]], implicit-def $arguments
- %0:_(s8) = G_CONSTANT i8 255
- %1:_(s32) = G_SEXT %0(s8)
- RETURN %1(s32), implicit-def $arguments
-...
-
----
-name: const_i8_aext
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: const_i8_aext
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CONST_I32_]], implicit-def $arguments
- %0:_(s8) = G_CONSTANT i8 255
- %1:_(s32) = G_ANYEXT %0(s8)
- RETURN %1(s32), implicit-def $arguments
-...
-
-
----
-name: const_i16_zext
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: const_i16_zext
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CONST_I32_]], implicit-def $arguments
- %0:_(s16) = G_CONSTANT i16 65535
- %1:_(s32) = G_ZEXT %0(s16)
- RETURN %1(s32), implicit-def $arguments
-...
-
----
-name: const_i16_sext
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: const_i16_sext
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CONST_I32_]], implicit-def $arguments
- %0:_(s16) = G_CONSTANT i16 65535
- %1:_(s32) = G_SEXT %0(s16)
- RETURN %1(s32), implicit-def $arguments
-...
-
----
-name: const_i16_aext
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: const_i16_aext
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CONST_I32_]], implicit-def $arguments
- %0:_(s16) = G_CONSTANT i16 65535
- %1:_(s32) = G_ANYEXT %0(s16)
- RETURN %1(s32), implicit-def $arguments
-...
-
----
-name: const_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: const_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CONST_I32_]], implicit-def $arguments
- %0:_(s32) = G_CONSTANT i32 4294967295
- RETURN %0(s32), implicit-def $arguments
-...
-
----
-name: const_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: const_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 -1, implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CONST_I64_]], implicit-def $arguments
- %0:_(s64) = G_CONSTANT i64 18446744073709551615
- RETURN %0(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ctlz_zero_undef.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ctlz_zero_undef.mir
deleted file mode 100644
index fe238329d0da4..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ctlz_zero_undef.mir
+++ /dev/null
@@ -1,152 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: ctlz_zundef_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_zundef_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CLZ_I32_:%[0-9]+]]:i32 = CLZ_I32 [[AND_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 24, implicit-def dead $arguments
- ; CHECK-NEXT: [[SUB_I32_:%[0-9]+]]:i32 = nuw SUB_I32 [[CLZ_I32_]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SUB_I32_]], implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %1(s32)
- %2:_(s8) = G_CTLZ_ZERO_UNDEF %0
- %3:_(s32) = G_ANYEXT %2(s8)
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: ctlz_zundef_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_zundef_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CLZ_I32_:%[0-9]+]]:i32 = CLZ_I32 [[AND_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 16, implicit-def dead $arguments
- ; CHECK-NEXT: [[SUB_I32_:%[0-9]+]]:i32 = nuw SUB_I32 [[CLZ_I32_]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SUB_I32_]], implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %1(s32)
- %2:_(s16) = G_CTLZ_ZERO_UNDEF %0
- %3:_(s32) = G_ANYEXT %2(s16)
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: ctlz_zundef_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_zundef_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CLZ_I32_:%[0-9]+]]:i32 = CLZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CLZ_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_CTLZ_ZERO_UNDEF %0
- RETURN %1(s32), implicit-def $arguments
-
-...
----
-name: ctlz_zundef_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_zundef_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CLZ_I32_:%[0-9]+]]:i32 = CLZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CLZ_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s8) = G_CTLZ_ZERO_UNDEF %0
- %2:_(s32) = G_ANYEXT %1(s8)
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: ctlz_zundef_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_zundef_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CLZ_I64_:%[0-9]+]]:i64 = CLZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CLZ_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_CTLZ_ZERO_UNDEF %0
- RETURN %1(s64), implicit-def $arguments
-
-...
----
-name: ctlz_zundef_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_zundef_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CLZ_I64_:%[0-9]+]]:i64 = CLZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[CLZ_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s8) = G_CTLZ_ZERO_UNDEF %0
- %2:_(s32) = G_ANYEXT %1(s8)
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: ctlz_zundef_i64_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_zundef_i64_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CLZ_I64_:%[0-9]+]]:i64 = CLZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[CLZ_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s32) = G_CTLZ_ZERO_UNDEF %0
- RETURN %1(s32), implicit-def $arguments
-
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ctpop.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ctpop.mir
deleted file mode 100644
index 7576ad6c567b0..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ctpop.mir
+++ /dev/null
@@ -1,148 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: ctpop_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctpop_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[POPCNT_I32_:%[0-9]+]]:i32 = POPCNT_I32 [[AND_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[POPCNT_I32_]], implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %1(s32)
- %2:_(s8) = G_CTPOP %0
- %3:_(s32) = G_ANYEXT %2(s8)
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: ctpop_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctpop_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[POPCNT_I32_:%[0-9]+]]:i32 = POPCNT_I32 [[AND_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[POPCNT_I32_]], implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %1(s32)
- %2:_(s16) = G_CTPOP %0
- %3:_(s32) = G_ANYEXT %2(s16)
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: ctpop_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctpop_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[POPCNT_I32_:%[0-9]+]]:i32 = POPCNT_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[POPCNT_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_CTPOP %0
- RETURN %1(s32), implicit-def $arguments
-
-...
----
-name: ctpop_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctpop_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[POPCNT_I32_:%[0-9]+]]:i32 = POPCNT_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[POPCNT_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s8) = G_CTPOP %0
- %2:_(s32) = G_ANYEXT %1(s8)
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: ctpop_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctpop_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[POPCNT_I64_:%[0-9]+]]:i64 = POPCNT_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[POPCNT_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_CTPOP %0
- RETURN %1(s64), implicit-def $arguments
-
-...
----
-name: ctpop_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctpop_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[POPCNT_I64_:%[0-9]+]]:i64 = POPCNT_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[POPCNT_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s8) = G_CTPOP %0
- %2:_(s32) = G_ANYEXT %1(s8)
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: ctpop_i64_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctpop_i64_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[POPCNT_I64_:%[0-9]+]]:i64 = POPCNT_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[POPCNT_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s32) = G_CTPOP %0
- RETURN %1(s32), implicit-def $arguments
-
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/cttz_zero_undef.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/cttz_zero_undef.mir
deleted file mode 100644
index 367d595e88b19..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/cttz_zero_undef.mir
+++ /dev/null
@@ -1,148 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: cttz_zundef_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: cttz_zundef_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 256, implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = OR_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CTZ_I32_:%[0-9]+]]:i32 = CTZ_I32 [[OR_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CTZ_I32_]], implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %1(s32)
- %2:_(s8) = G_CTTZ_ZERO_UNDEF %0
- %3:_(s32) = G_ANYEXT %2(s8)
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: cttz_zundef_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: cttz_zundef_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 65536, implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = OR_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CTZ_I32_:%[0-9]+]]:i32 = CTZ_I32 [[OR_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CTZ_I32_]], implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %1(s32)
- %2:_(s16) = G_CTTZ_ZERO_UNDEF %0
- %3:_(s32) = G_ANYEXT %2(s16)
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: cttz_zundef_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: cttz_zundef_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CTZ_I32_:%[0-9]+]]:i32 = CTZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CTZ_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_CTTZ_ZERO_UNDEF %0
- RETURN %1(s32), implicit-def $arguments
-
-...
----
-name: cttz_zundef_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: cttz_zundef_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CTZ_I32_:%[0-9]+]]:i32 = CTZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CTZ_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s8) = G_CTTZ_ZERO_UNDEF %0
- %2:_(s32) = G_ANYEXT %1(s8)
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: cttz_zundef_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: cttz_zundef_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTZ_I64_:%[0-9]+]]:i64 = CTZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CTZ_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_CTTZ_ZERO_UNDEF %0
- RETURN %1(s64), implicit-def $arguments
-
-...
----
-name: cttz_zundef_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: cttz_zundef_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTZ_I64_:%[0-9]+]]:i64 = CTZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[CTZ_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s8) = G_CTTZ_ZERO_UNDEF %0
- %2:_(s32) = G_ANYEXT %1(s8)
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: cttz_zundef_i64_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: cttz_zundef_i64_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTZ_I64_:%[0-9]+]]:i64 = CTZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[CTZ_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s32) = G_CTTZ_ZERO_UNDEF %0
- RETURN %1(s32), implicit-def $arguments
-
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/fshl.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/fshl.mir
deleted file mode 100644
index 898711486f132..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/fshl.mir
+++ /dev/null
@@ -1,382 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: fshl_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshl_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 5, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 3, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_2:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_2]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_CONSTANT i8 5
- %5:_(s8) = G_FSHL %0, %1, %4(s8)
- %6:_(s32) = G_ANYEXT %5(s8)
- RETURN %6(s32), implicit-def $arguments
-
-...
----
-name: fshlv_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshlv_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32 = ARGUMENT_i32 2, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 7, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_2]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
- ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_2]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[XOR_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_2:%[0-9]+]]:i32 = CONST_I32 1, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[AND_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_3:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_2:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_3]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_2]], [[CONST_I32_2]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_4:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_3:%[0-9]+]]:i32 = AND_I32 [[SHR_U_I32_]], [[CONST_I32_4]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_1:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_3]], [[AND_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
- %3:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %3(s32)
- %4:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %4(s32)
- %5:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- %2:_(s8) = G_TRUNC %5(s32)
- %6:_(s8) = G_FSHL %0, %1, %2(s8)
- %7:_(s32) = G_ANYEXT %6(s8)
- RETURN %7(s32), implicit-def $arguments
-
-...
----
-name: fshl_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshl_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 13, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 3, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_2:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_2]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_CONSTANT i16 13
- %5:_(s16) = G_FSHL %0, %1, %4(s16)
- %6:_(s32) = G_ANYEXT %5(s16)
- RETURN %6(s32), implicit-def $arguments
-
-...
----
-name: fshlv_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshlv_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32 = ARGUMENT_i32 2, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 15, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_2]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
- ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_2]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[XOR_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_2:%[0-9]+]]:i32 = CONST_I32 1, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[AND_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_3:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_2:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_3]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_2]], [[CONST_I32_2]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_4:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_3:%[0-9]+]]:i32 = AND_I32 [[SHR_U_I32_]], [[CONST_I32_4]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_1:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_3]], [[AND_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
- %3:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %3(s32)
- %4:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %4(s32)
- %5:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- %2:_(s16) = G_TRUNC %5(s32)
- %6:_(s16) = G_FSHL %0, %1, %2(s16)
- %7:_(s32) = G_ANYEXT %6(s16)
- RETURN %7(s32), implicit-def $arguments
-
-...
----
-name: fshl_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshl_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 11, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_CONSTANT i32 21
- %3:_(s32) = G_FSHL %0, %1, %2(s32)
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: fshlv_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshlv_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32 = ARGUMENT_i32 2, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
- ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_2]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 1, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_2]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_1:%[0-9]+]]:i32 = SHR_U_I32 [[SHR_U_I32_]], [[XOR_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- %3:_(s32) = G_FSHL %0, %1, %2(s32)
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: fshl_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshl_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 11, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s8) = G_CONSTANT i8 21
- %3:_(s32) = G_FSHL %0, %1, %2(s8)
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: fshlv_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshlv_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32 = ARGUMENT_i32 2, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
- ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_2]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 1, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_2]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_1:%[0-9]+]]:i32 = SHR_U_I32 [[SHR_U_I32_]], [[XOR_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %3:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- %2:_(s8) = G_TRUNC %3(s32)
- %4:_(s32) = G_FSHL %0, %1, %2(s8)
- RETURN %4(s32), implicit-def $arguments
-
-...
----
-name: fshl_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshl_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 27, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[CONST_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[CONST_I64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = disjoint OR_I64 [[SHL_I64_]], [[SHR_U_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_CONSTANT i64 37
- %3:_(s64) = G_FSHL %0, %1, %2(s64)
- RETURN %3(s64), implicit-def $arguments
-
-...
----
-name: fshlv_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshlv_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_2:%[0-9]+]]:i64 = ARGUMENT_i64 2, implicit $arguments
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 -1, implicit-def dead $arguments
- ; CHECK-NEXT: [[XOR_I64_:%[0-9]+]]:i64 = XOR_I64 [[ARGUMENT_i64_2]], [[CONST_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 1, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_2]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[CONST_I64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I64_1:%[0-9]+]]:i64 = SHR_U_I64 [[SHR_U_I64_]], [[XOR_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = disjoint OR_I64 [[SHL_I64_]], [[SHR_U_I64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:i64(s64) = ARGUMENT_i64 2, implicit $arguments
- %3:_(s64) = G_FSHL %0, %1, %2(s64)
- RETURN %3(s64), implicit-def $arguments
-
-...
----
-name: fshl_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshl_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 21, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_]], [[CONST_I64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_2:%[0-9]+]]:i64 = CONST_I64 43, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_3:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_1:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_2]], [[CONST_I64_3]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[AND_I64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = disjoint OR_I64 [[SHL_I64_]], [[SHR_U_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s8) = G_CONSTANT i8 21
- %3:_(s64) = G_FSHL %0, %1, %2(s8)
- RETURN %3(s64), implicit-def $arguments
-
-...
----
-name: fshlv_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshlv_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 2, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 63, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
- ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[XOR_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[AND_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 1, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_2:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_1:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_1]], [[CONST_I64_2]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[AND_I64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[I64_EXTEND_U_I32_1:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[AND_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_3:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_2:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_1]], [[CONST_I64_3]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I64_1:%[0-9]+]]:i64 = SHR_U_I64 [[SHR_U_I64_]], [[AND_I64_2]], implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = disjoint OR_I64 [[SHL_I64_]], [[SHR_U_I64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %3:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- %2:_(s8) = G_TRUNC %3(s32)
- %4:_(s64) = G_FSHL %0, %1, %2(s8)
- RETURN %4(s64), implicit-def $arguments
-
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/fshr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/fshr.mir
deleted file mode 100644
index 4684532699357..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/fshr.mir
+++ /dev/null
@@ -1,378 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: fshr_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshr_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 5, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 3, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_2:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_2]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_CONSTANT i8 5
- %5:_(s8) = G_FSHR %0, %1, %4(s8)
- %6:_(s32) = G_ANYEXT %5(s8)
- RETURN %6(s32), implicit-def $arguments
-
-...
----
-name: fshrv_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshrv_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32 = ARGUMENT_i32 2, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 7, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_2]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
- ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_2]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[XOR_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_2:%[0-9]+]]:i32 = CONST_I32 1, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_2]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_1:%[0-9]+]]:i32 = SHL_I32 [[SHL_I32_]], [[AND_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_3:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_2:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_3]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_2]], [[AND_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_1]], [[SHR_U_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
- %3:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %3(s32)
- %4:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %4(s32)
- %5:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- %2:_(s8) = G_TRUNC %5(s32)
- %6:_(s8) = G_FSHR %0, %1, %2(s8)
- %7:_(s32) = G_ANYEXT %6(s8)
- RETURN %7(s32), implicit-def $arguments
-
-...
----
-name: fshr_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshr_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 13, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 3, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_2:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_2]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_CONSTANT i16 13
- %5:_(s16) = G_FSHR %0, %1, %4(s16)
- %6:_(s32) = G_ANYEXT %5(s16)
- RETURN %6(s32), implicit-def $arguments
-
-...
----
-name: fshrv_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshrv_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32 = ARGUMENT_i32 2, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 15, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_2]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
- ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_2]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[XOR_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_2:%[0-9]+]]:i32 = CONST_I32 1, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_2]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_1:%[0-9]+]]:i32 = SHL_I32 [[SHL_I32_]], [[AND_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_3:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_2:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_3]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_2]], [[AND_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_1]], [[SHR_U_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
- %3:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %3(s32)
- %4:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %4(s32)
- %5:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- %2:_(s16) = G_TRUNC %5(s32)
- %6:_(s16) = G_FSHR %0, %1, %2(s16)
- %7:_(s32) = G_ANYEXT %6(s16)
- RETURN %7(s32), implicit-def $arguments
-
-...
----
-name: fshr_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshr_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 11, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_1]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_CONSTANT i32 21
- %3:_(s32) = G_FSHR %0, %1, %2(s32)
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: fshrv_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshrv_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32 = ARGUMENT_i32 2, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
- ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_2]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 1, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_1:%[0-9]+]]:i32 = SHL_I32 [[SHL_I32_]], [[XOR_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_2]], implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_1]], [[SHR_U_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- %3:_(s32) = G_FSHR %0, %1, %2(s32)
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: fshr_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshr_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 11, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_1]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s8) = G_CONSTANT i8 21
- %3:_(s32) = G_FSHR %0, %1, %2(s8)
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: fshrv_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshrv_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32 = ARGUMENT_i32 2, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
- ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_2]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 1, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_1:%[0-9]+]]:i32 = SHL_I32 [[SHL_I32_]], [[XOR_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_2]], implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_1]], [[SHR_U_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %3:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- %2:_(s8) = G_TRUNC %3(s32)
- %4:_(s32) = G_FSHR %0, %1, %2(s8)
- RETURN %4(s32), implicit-def $arguments
-
-...
----
-name: fshr_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshr_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 27, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[CONST_I64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[CONST_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = disjoint OR_I64 [[SHL_I64_]], [[SHR_U_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_CONSTANT i64 37
- %3:_(s64) = G_FSHR %0, %1, %2(s64)
- RETURN %3(s64), implicit-def $arguments
-
-...
----
-name: fshrv_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshrv_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_2:%[0-9]+]]:i64 = ARGUMENT_i64 2, implicit $arguments
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 -1, implicit-def dead $arguments
- ; CHECK-NEXT: [[XOR_I64_:%[0-9]+]]:i64 = XOR_I64 [[ARGUMENT_i64_2]], [[CONST_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 1, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[CONST_I64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I64_1:%[0-9]+]]:i64 = SHL_I64 [[SHL_I64_]], [[XOR_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[ARGUMENT_i64_2]], implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = disjoint OR_I64 [[SHL_I64_1]], [[SHR_U_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:i64(s64) = ARGUMENT_i64 2, implicit $arguments
- %3:_(s64) = G_FSHR %0, %1, %2(s64)
- RETURN %3(s64), implicit-def $arguments
-
-...
----
-name: fshr_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshr_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 43, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_]], [[CONST_I64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_2:%[0-9]+]]:i64 = CONST_I64 21, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_3:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_1:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_2]], [[CONST_I64_3]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[AND_I64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = disjoint OR_I64 [[SHL_I64_]], [[SHR_U_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s8) = G_CONSTANT i8 21
- %3:_(s64) = G_FSHR %0, %1, %2(s8)
- RETURN %3(s64), implicit-def $arguments
-
-...
----
-name: fshrv_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: fshrv_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 2, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 63, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
- ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[XOR_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 1, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_]], [[CONST_I64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[AND_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_2:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_1:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_2]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I64_1:%[0-9]+]]:i64 = SHL_I64 [[SHL_I64_]], [[AND_I64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[I64_EXTEND_U_I32_1:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[AND_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_3:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_2:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_1]], [[CONST_I64_3]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[AND_I64_2]], implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = disjoint OR_I64 [[SHL_I64_1]], [[SHR_U_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %3:i32(s32) = ARGUMENT_i32 2, implicit $arguments
- %2:_(s8) = G_TRUNC %3(s32)
- %4:_(s64) = G_FSHR %0, %1, %2(s8)
- RETURN %4(s64), implicit-def $arguments
-
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/lshr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/lshr.mir
deleted file mode 100644
index c7905072acf67..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/lshr.mir
+++ /dev/null
@@ -1,286 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: lshr_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshr_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 5, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHR_U_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %1:_(s8) = G_CONSTANT i8 5
- %3:_(s8) = G_LSHR %0, %1
- %4:_(s32) = G_ANYEXT %3(s8)
- RETURN %4(s32), implicit-def $arguments
-
-...
----
-name: lshrv_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshrv_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_]], [[AND_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHR_U_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_LSHR %0, %1
- %5:_(s32) = G_ANYEXT %4(s8)
- RETURN %5(s32), implicit-def $arguments
-
-...
----
-name: lshr_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshr_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 13, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHR_U_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %1:_(s16) = G_CONSTANT i16 13
- %3:_(s16) = G_LSHR %0, %1
- %4:_(s32) = G_ANYEXT %3(s16)
- RETURN %4(s32), implicit-def $arguments
-
-...
----
-name: lshrv_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshrv_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[AND_I32_]], [[AND_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHR_U_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_LSHR %0, %1
- %5:_(s32) = G_ANYEXT %4(s16)
- RETURN %5(s32), implicit-def $arguments
-
-...
----
-name: lshr_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshr_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHR_U_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_CONSTANT i32 21
- %2:_(s32) = G_LSHR %0, %1
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: lshrv_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshrv_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHR_U_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_LSHR %0, %1
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: lshr_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshr_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHR_U_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s8) = G_CONSTANT i8 21
- %2:_(s32) = G_LSHR %0, %1
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: lshrv_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshrv_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_]], [[AND_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHR_U_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %2(s32)
- %3:_(s32) = G_LSHR %0, %1
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: lshr_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshr_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_]], [[CONST_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHR_U_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_CONSTANT i64 37
- %2:_(s64) = G_LSHR %0, %1
- RETURN %2(s64), implicit-def $arguments
-
-...
----
-name: lshrv_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshrv_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHR_U_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_LSHR %0, %1
- RETURN %2(s64), implicit-def $arguments
-
-...
----
-name: lshr_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshr_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_]], [[CONST_I64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHR_U_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s8) = G_CONSTANT i8 37
- %2:_(s64) = G_LSHR %0, %1
- RETURN %2(s64), implicit-def $arguments
-
-...
----
-name: lshrv_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: lshrv_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHR_U_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %2(s32)
- %3:_(s64) = G_LSHR %0, %1
- RETURN %3(s64), implicit-def $arguments
-
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/mul.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/mul.mir
deleted file mode 100644
index a690750c25d28..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/mul.mir
+++ /dev/null
@@ -1,89 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: mul_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: mul_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[MUL_I32_:%[0-9]+]]:i32 = MUL_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[MUL_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_MUL %0, %1
- %5:i32(s32) = G_ANYEXT %4(s8)
- RETURN %5(s32), implicit-def $arguments
-...
----
-name: mul_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: mul_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[MUL_I32_:%[0-9]+]]:i32 = MUL_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[MUL_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_MUL %0, %1
- %5:i32(s32) = G_ANYEXT %4(s16)
- RETURN %5(s32), implicit-def $arguments
-...
----
-name: mul_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: mul_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[MUL_I32_:%[0-9]+]]:i32 = MUL_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[MUL_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_MUL %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: mul_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: mul_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[MUL_I64_:%[0-9]+]]:i64 = MUL_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[MUL_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_MUL %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/or.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/or.mir
deleted file mode 100644
index fbb3f5e507a95..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/or.mir
+++ /dev/null
@@ -1,117 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: or_i1
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: or_i1
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = OR_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s1) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s1) = G_TRUNC %3(s32)
- %4:_(s1) = G_OR %1, %0
- %5:_(s32) = G_ANYEXT %4(s1)
- RETURN %5(s32), implicit-def $arguments
-
-...
----
-name: or_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: or_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = OR_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_OR %1, %0
- %5:_(s32) = G_ANYEXT %4(s8)
- RETURN %5(s32), implicit-def $arguments
-
-...
----
-name: or_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: or_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = OR_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_OR %1, %0
- %5:_(s32) = G_ANYEXT %4(s16)
- RETURN %5(s32), implicit-def $arguments
-
-...
----
-name: or_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: or_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = OR_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_OR %1, %0
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: or_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: or_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = OR_I64 [[ARGUMENT_i64_1]], [[ARGUMENT_i64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_OR %1, %0
- RETURN %2(s64), implicit-def $arguments
-
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sdiv.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sdiv.mir
deleted file mode 100644
index 0806622b99192..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sdiv.mir
+++ /dev/null
@@ -1,122 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=-sign-ext -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NO-SIGNEXT
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=+sign-ext -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,SIGNEXT
-
----
-name: sdiv_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: sdiv_i8
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 24, implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 24, implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHL_I32_1:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHR_S_I32_1:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_1]], [[CONST_I32_1]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[DIV_S_I32_:%[0-9]+]]:i32 = DIV_S_I32 [[SHR_S_I32_]], [[SHR_S_I32_1]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: RETURN [[DIV_S_I32_]], implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: sdiv_i8
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; SIGNEXT-NEXT: [[I32_EXTEND8_S_I32_:%[0-9]+]]:i32 = I32_EXTEND8_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: [[I32_EXTEND8_S_I32_1:%[0-9]+]]:i32 = I32_EXTEND8_S_I32 [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: [[DIV_S_I32_:%[0-9]+]]:i32 = DIV_S_I32 [[I32_EXTEND8_S_I32_]], [[I32_EXTEND8_S_I32_1]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: RETURN [[DIV_S_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_SDIV %0, %1
- %5:i32(s32) = G_ANYEXT %4(s8)
- RETURN %5(s32), implicit-def $arguments
-...
----
-name: sdiv_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: sdiv_i16
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 16, implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 16, implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHL_I32_1:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHR_S_I32_1:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_1]], [[CONST_I32_1]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[DIV_S_I32_:%[0-9]+]]:i32 = DIV_S_I32 [[SHR_S_I32_]], [[SHR_S_I32_1]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: RETURN [[DIV_S_I32_]], implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: sdiv_i16
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; SIGNEXT-NEXT: [[I32_EXTEND16_S_I32_:%[0-9]+]]:i32 = I32_EXTEND16_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: [[I32_EXTEND16_S_I32_1:%[0-9]+]]:i32 = I32_EXTEND16_S_I32 [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: [[DIV_S_I32_:%[0-9]+]]:i32 = DIV_S_I32 [[I32_EXTEND16_S_I32_]], [[I32_EXTEND16_S_I32_1]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: RETURN [[DIV_S_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_SDIV %0, %1
- %5:i32(s32) = G_ANYEXT %4(s16)
- RETURN %5(s32), implicit-def $arguments
-...
----
-name: sdiv_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sdiv_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[DIV_S_I32_:%[0-9]+]]:i32 = DIV_S_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[DIV_S_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_SDIV %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: sdiv_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sdiv_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[DIV_S_I64_:%[0-9]+]]:i64 = DIV_S_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[DIV_S_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_SDIV %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sext.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sext.mir
deleted file mode 100644
index 8c8e58b5e4a46..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sext.mir
+++ /dev/null
@@ -1,138 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=-sign-ext -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NO-SIGNEXT
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=+sign-ext -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,SIGNEXT
-
----
-name: sext_i8_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: sext_i8_i32
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 24, implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: sext_i8_i32
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[I32_EXTEND8_S_I32_:%[0-9]+]]:i32 = I32_EXTEND8_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: RETURN [[I32_EXTEND8_S_I32_]], implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %1(s32)
- %2:i32(s32) = G_SEXT %0(s8)
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: sext_i8_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: sext_i8_i64
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 56, implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHR_S_I64_:%[0-9]+]]:i64 = SHR_S_I64 [[SHL_I64_]], [[CONST_I64_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I64_]], implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: sext_i8_i64
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: [[I64_EXTEND8_S_I64_:%[0-9]+]]:i64 = I64_EXTEND8_S_I64 [[I64_EXTEND_U_I32_]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: RETURN [[I64_EXTEND8_S_I64_]], implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %1(s32)
- %2:i64(s64) = G_SEXT %0(s8)
- RETURN %2(s64), implicit-def $arguments
-...
----
-name: sext_i16_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: sext_i16_i32
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 16, implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: sext_i16_i32
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[I32_EXTEND16_S_I32_:%[0-9]+]]:i32 = I32_EXTEND16_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: RETURN [[I32_EXTEND16_S_I32_]], implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %1(s32)
- %2:i32(s32) = G_SEXT %0(s16)
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: sext_i16_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: sext_i16_i64
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 48, implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHR_S_I64_:%[0-9]+]]:i64 = SHR_S_I64 [[SHL_I64_]], [[CONST_I64_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I64_]], implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: sext_i16_i64
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: [[I64_EXTEND16_S_I64_:%[0-9]+]]:i64 = I64_EXTEND16_S_I64 [[I64_EXTEND_U_I32_]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: RETURN [[I64_EXTEND16_S_I64_]], implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %1(s32)
- %2:i64(s64) = G_SEXT %0(s16)
- RETURN %2(s64), implicit-def $arguments
-...
----
-name: sext_i32_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sext_i32_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[I64_EXTEND_S_I32_:%[0-9]+]]:i64 = I64_EXTEND_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[I64_EXTEND_S_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i64(s64) = G_SEXT %0(s32)
- RETURN %1(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sext_inreg.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sext_inreg.mir
deleted file mode 100644
index b9d904ae3f7a9..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sext_inreg.mir
+++ /dev/null
@@ -1,181 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=-sign-ext -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NO-SIGNEXT
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=+sign-ext -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,SIGNEXT
-
----
-name: sext_inreg_i1_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sext_inreg_i1_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 31, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 %1, [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_SEXT_INREG %1(s32), 1
- RETURN %1(s32), implicit-def $arguments
-...
----
-name: sext_inreg_i8_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: sext_inreg_i8_i32
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 24, implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 %1, [[CONST_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: sext_inreg_i8_i32
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[I32_EXTEND8_S_I32_:%[0-9]+]]:i32 = I32_EXTEND8_S_I32 [[I32_EXTEND8_S_I32_]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: RETURN [[I32_EXTEND8_S_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_SEXT_INREG %1(s32), 8
- RETURN %1(s32), implicit-def $arguments
-...
----
-name: sext_inreg_i16_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: sext_inreg_i16_i32
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 16, implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 %1, [[CONST_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: sext_inreg_i16_i32
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[I32_EXTEND16_S_I32_:%[0-9]+]]:i32 = I32_EXTEND16_S_I32 [[I32_EXTEND16_S_I32_]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: RETURN [[I32_EXTEND16_S_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_SEXT_INREG %1(s32), 16
- RETURN %1(s32), implicit-def $arguments
-...
-
----
-name: sext_inreg_i1_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sext_inreg_i1_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 63, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 %1, [[CONST_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHR_S_I64_:%[0-9]+]]:i64 = SHR_S_I64 [[SHL_I64_]], [[CONST_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHR_S_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_SEXT_INREG %1(s64), 1
- RETURN %1(s64), implicit-def $arguments
-...
----
-name: sext_inreg_i8_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: sext_inreg_i8_i64
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 56, implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 %1, [[CONST_I64_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHR_S_I64_:%[0-9]+]]:i64 = SHR_S_I64 [[SHL_I64_]], [[CONST_I64_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I64_]], implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: sext_inreg_i8_i64
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; SIGNEXT-NEXT: [[I64_EXTEND8_S_I64_:%[0-9]+]]:i64 = I64_EXTEND8_S_I64 [[I64_EXTEND8_S_I64_]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: RETURN [[I64_EXTEND8_S_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_SEXT_INREG %1(s64), 8
- RETURN %1(s64), implicit-def $arguments
-...
----
-name: sext_inreg_i16_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: sext_inreg_i16_i64
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 48, implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 %1, [[CONST_I64_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHR_S_I64_:%[0-9]+]]:i64 = SHR_S_I64 [[SHL_I64_]], [[CONST_I64_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I64_]], implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: sext_inreg_i16_i64
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; SIGNEXT-NEXT: [[I64_EXTEND16_S_I64_:%[0-9]+]]:i64 = I64_EXTEND16_S_I64 [[I64_EXTEND16_S_I64_]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: RETURN [[I64_EXTEND16_S_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_SEXT_INREG %1(s64), 16
- RETURN %1(s64), implicit-def $arguments
-...
-
----
-name: sext_inreg_i32_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: sext_inreg_i32_i64
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 32, implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 %1, [[CONST_I64_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHR_S_I64_:%[0-9]+]]:i64 = SHR_S_I64 [[SHL_I64_]], [[CONST_I64_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: RETURN [[SHR_S_I64_]], implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: sext_inreg_i32_i64
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; SIGNEXT-NEXT: [[I64_EXTEND32_S_I64_:%[0-9]+]]:i64 = I64_EXTEND32_S_I64 [[I64_EXTEND32_S_I64_]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: RETURN [[I64_EXTEND32_S_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_SEXT_INREG %1(s64), 32
- RETURN %1(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/shl.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/shl.mir
deleted file mode 100644
index c61312d799163..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/shl.mir
+++ /dev/null
@@ -1,278 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: shl_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shl_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 5, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHL_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %1:_(s8) = G_CONSTANT i8 5
- %3:_(s8) = G_SHL %0, %1
- %4:_(s32) = G_ANYEXT %3(s8)
- RETURN %4(s32), implicit-def $arguments
-
-...
----
-name: shlv_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shlv_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[AND_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHL_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_SHL %0, %1
- %5:_(s32) = G_ANYEXT %4(s8)
- RETURN %5(s32), implicit-def $arguments
-
-...
----
-name: shl_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shl_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 13, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHL_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %1:_(s16) = G_CONSTANT i16 13
- %3:_(s16) = G_SHL %0, %1
- %4:_(s32) = G_ANYEXT %3(s16)
- RETURN %4(s32), implicit-def $arguments
-
-...
----
-name: shlv_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shlv_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[AND_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHL_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_SHL %0, %1
- %5:_(s32) = G_ANYEXT %4(s16)
- RETURN %5(s32), implicit-def $arguments
-
-...
----
-name: shl_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shl_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHL_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s32) = G_CONSTANT i32 21
- %2:_(s32) = G_SHL %0, %1
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: shlv_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shlv_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHL_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_SHL %0, %1
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: shl_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shl_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHL_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s8) = G_CONSTANT i8 21
- %2:_(s32) = G_SHL %0, %1
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: shlv_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shlv_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[AND_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHL_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %2(s32)
- %3:_(s32) = G_SHL %0, %1
- RETURN %3(s32), implicit-def $arguments
-
-...
----
-name: shl_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shl_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[CONST_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHL_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_CONSTANT i64 37
- %2:_(s64) = G_SHL %0, %1
- RETURN %2(s64), implicit-def $arguments
-
-...
----
-name: shlv_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shlv_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHL_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_SHL %0, %1
- RETURN %2(s64), implicit-def $arguments
-
-...
----
-name: shl_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shl_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_]], [[CONST_I64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHL_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s8) = G_CONSTANT i8 37
- %2:_(s64) = G_SHL %0, %1
- RETURN %2(s64), implicit-def $arguments
-
-...
----
-name: shlv_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: shlv_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SHL_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %2(s32)
- %3:_(s64) = G_SHL %0, %1
- RETURN %3(s64), implicit-def $arguments
-
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/srem.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/srem.mir
deleted file mode 100644
index 4c9ef32cc6783..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/srem.mir
+++ /dev/null
@@ -1,122 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=-sign-ext -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NO-SIGNEXT
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -mattr=+sign-ext -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,SIGNEXT
-
----
-name: srem_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: srem_i8
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 24, implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 24, implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHL_I32_1:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHR_S_I32_1:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_1]], [[CONST_I32_1]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[REM_S_I32_:%[0-9]+]]:i32 = REM_S_I32 [[SHR_S_I32_]], [[SHR_S_I32_1]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: RETURN [[REM_S_I32_]], implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: srem_i8
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; SIGNEXT-NEXT: [[I32_EXTEND8_S_I32_:%[0-9]+]]:i32 = I32_EXTEND8_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: [[I32_EXTEND8_S_I32_1:%[0-9]+]]:i32 = I32_EXTEND8_S_I32 [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: [[REM_S_I32_:%[0-9]+]]:i32 = REM_S_I32 [[I32_EXTEND8_S_I32_]], [[I32_EXTEND8_S_I32_1]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: RETURN [[REM_S_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_SREM %0, %1
- %5:i32(s32) = G_ANYEXT %4(s8)
- RETURN %5(s32), implicit-def $arguments
-...
----
-name: srem_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; NO-SIGNEXT-LABEL: name: srem_i16
- ; NO-SIGNEXT: liveins: $arguments
- ; NO-SIGNEXT-NEXT: {{ $}}
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; NO-SIGNEXT-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 16, implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 16, implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHL_I32_1:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[SHR_S_I32_1:%[0-9]+]]:i32 = SHR_S_I32 [[SHL_I32_1]], [[CONST_I32_1]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: [[REM_S_I32_:%[0-9]+]]:i32 = REM_S_I32 [[SHR_S_I32_]], [[SHR_S_I32_1]], implicit-def dead $arguments
- ; NO-SIGNEXT-NEXT: RETURN [[REM_S_I32_]], implicit-def $arguments
- ;
- ; SIGNEXT-LABEL: name: srem_i16
- ; SIGNEXT: liveins: $arguments
- ; SIGNEXT-NEXT: {{ $}}
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; SIGNEXT-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; SIGNEXT-NEXT: [[I32_EXTEND16_S_I32_:%[0-9]+]]:i32 = I32_EXTEND16_S_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: [[I32_EXTEND16_S_I32_1:%[0-9]+]]:i32 = I32_EXTEND16_S_I32 [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: [[REM_S_I32_:%[0-9]+]]:i32 = REM_S_I32 [[I32_EXTEND16_S_I32_]], [[I32_EXTEND16_S_I32_1]], implicit-def dead $arguments
- ; SIGNEXT-NEXT: RETURN [[REM_S_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_SREM %0, %1
- %5:i32(s32) = G_ANYEXT %4(s16)
- RETURN %5(s32), implicit-def $arguments
-...
----
-name: srem_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: srem_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[REM_S_I32_:%[0-9]+]]:i32 = REM_S_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[REM_S_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_SREM %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: srem_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: srem_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[REM_S_I64_:%[0-9]+]]:i64 = REM_S_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[REM_S_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_SREM %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sub.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sub.mir
deleted file mode 100644
index d47a893852d70..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/sub.mir
+++ /dev/null
@@ -1,89 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: sub_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sub_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[SUB_I32_:%[0-9]+]]:i32 = SUB_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SUB_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_SUB %0, %1
- %5:i32(s32) = G_ANYEXT %4(s8)
- RETURN %5(s32), implicit-def $arguments
-...
----
-name: sub_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sub_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[SUB_I32_:%[0-9]+]]:i32 = SUB_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SUB_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_SUB %0, %1
- %5:i32(s32) = G_ANYEXT %4(s16)
- RETURN %5(s32), implicit-def $arguments
-...
----
-name: sub_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sub_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[SUB_I32_:%[0-9]+]]:i32 = SUB_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SUB_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_SUB %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: sub_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: sub_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[SUB_I64_:%[0-9]+]]:i64 = SUB_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SUB_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_SUB %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/trunc.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/trunc.mir
deleted file mode 100644
index f9b73d1d9d7d4..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/trunc.mir
+++ /dev/null
@@ -1,95 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: trunc_i32_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: trunc_i32_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: RETURN [[ARGUMENT_i32_]], implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %1(s32)
- %2:i32(s32) = G_ANYEXT %0(s8)
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: trunc_i32_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: trunc_i32_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: RETURN [[ARGUMENT_i32_]], implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %1(s32)
- %2:i32(s32) = G_ANYEXT %0(s16)
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: trunc_i64_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: trunc_i64_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
- %1:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %0:_(s8) = G_TRUNC %1(s64)
- %2:i32(s32) = G_ANYEXT %0(s8)
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: trunc_i64_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: trunc_i64_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
- %1:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %0:_(s16) = G_TRUNC %1(s64)
- %2:i32(s32) = G_ANYEXT %0(s16)
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: trunc_i64_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: trunc_i64_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
- %1:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %0:_(s32) = G_TRUNC %1(s64)
- RETURN %0(s32), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/udiv.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/udiv.mir
deleted file mode 100644
index 29de1db5e286b..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/udiv.mir
+++ /dev/null
@@ -1,97 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: udiv_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: udiv_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[DIV_U_I32_:%[0-9]+]]:i32 = DIV_U_I32 [[AND_I32_]], [[AND_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[DIV_U_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_UDIV %0, %1
- %5:i32(s32) = G_ANYEXT %4(s8)
- RETURN %5(s32), implicit-def $arguments
-...
----
-name: udiv_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: udiv_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[DIV_U_I32_:%[0-9]+]]:i32 = DIV_U_I32 [[AND_I32_]], [[AND_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[DIV_U_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_UDIV %0, %1
- %5:i32(s32) = G_ANYEXT %4(s16)
- RETURN %5(s32), implicit-def $arguments
-...
----
-name: udiv_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: udiv_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[DIV_U_I32_:%[0-9]+]]:i32 = DIV_U_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[DIV_U_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_UDIV %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: udiv_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: udiv_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[DIV_U_I64_:%[0-9]+]]:i64 = DIV_U_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[DIV_U_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_UDIV %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/urem.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/urem.mir
deleted file mode 100644
index 033a9dbfa0671..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/urem.mir
+++ /dev/null
@@ -1,97 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: urem_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: urem_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[REM_U_I32_:%[0-9]+]]:i32 = REM_U_I32 [[AND_I32_]], [[AND_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[REM_U_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_UREM %0, %1
- %5:i32(s32) = G_ANYEXT %4(s8)
- RETURN %5(s32), implicit-def $arguments
-...
----
-name: urem_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: urem_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: [[REM_U_I32_:%[0-9]+]]:i32 = REM_U_I32 [[AND_I32_]], [[AND_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[REM_U_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_UREM %0, %1
- %5:i32(s32) = G_ANYEXT %4(s16)
- RETURN %5(s32), implicit-def $arguments
-...
----
-name: urem_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: urem_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[REM_U_I32_:%[0-9]+]]:i32 = REM_U_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[REM_U_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_UREM %0, %1
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: urem_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: urem_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[REM_U_I64_:%[0-9]+]]:i64 = REM_U_I64 [[ARGUMENT_i64_]], [[ARGUMENT_i64_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[REM_U_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_UREM %0, %1
- RETURN %2(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/xor.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/xor.mir
deleted file mode 100644
index 921d7a30a8070..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/xor.mir
+++ /dev/null
@@ -1,116 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: xor_i1
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: xor_i1
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[XOR_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s1) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s1) = G_TRUNC %3(s32)
- %4:_(s1) = G_XOR %1, %0
- %5:_(s32) = G_ANYEXT %4(s1)
- RETURN %5(s32), implicit-def $arguments
-
-...
----
-name: xor_i8
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: xor_i8
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[XOR_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s8) = G_TRUNC %3(s32)
- %4:_(s8) = G_XOR %1, %0
- %5:_(s32) = G_ANYEXT %4(s8)
- RETURN %5(s32), implicit-def $arguments
-
-...
----
-name: xor_i16
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: xor_i16
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[XOR_I32_]], implicit-def $arguments
- %2:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %2(s32)
- %3:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %1:_(s16) = G_TRUNC %3(s32)
- %4:_(s16) = G_XOR %1, %0
- %5:_(s32) = G_ANYEXT %4(s16)
- RETURN %5(s32), implicit-def $arguments
-
-...
----
-name: xor_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: xor_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
- ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[XOR_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
- %2:_(s32) = G_XOR %1, %0
- RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: xor_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: xor_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
- ; CHECK-NEXT: [[XOR_I64_:%[0-9]+]]:i64 = XOR_I64 [[ARGUMENT_i64_1]], [[ARGUMENT_i64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[XOR_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
- %2:_(s64) = G_XOR %1, %0
- RETURN %2(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/zext.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/zext.mir
deleted file mode 100644
index 5e0079d181b71..0000000000000
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/zext.mir
+++ /dev/null
@@ -1,103 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
-
----
-name: zext_i8_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: zext_i8_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[AND_I32_]], implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %1(s32)
- %2:i32(s32) = G_ZEXT %0(s8)
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: zext_i8_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: zext_i8_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[AND_I64_]], implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %1(s32)
- %2:i64(s64) = G_ZEXT %0(s8)
- RETURN %2(s64), implicit-def $arguments
-...
----
-name: zext_i16_i32
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: zext_i16_i32
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[AND_I32_]], implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %1(s32)
- %2:i32(s32) = G_ZEXT %0(s16)
- RETURN %2(s32), implicit-def $arguments
-...
----
-name: zext_i16_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: zext_i16_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 65535, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[AND_I64_]], implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %1(s32)
- %2:i64(s64) = G_ZEXT %0(s16)
- RETURN %2(s64), implicit-def $arguments
-...
----
-name: zext_i32_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: zext_i32_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[I64_EXTEND_U_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:i64(s64) = G_ZEXT %0(s32)
- RETURN %1(s64), implicit-def $arguments
-...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/add.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/add.ll
new file mode 100644
index 0000000000000..e706d584cc14a
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/add.ll
@@ -0,0 +1,141 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O0 --global-isel -mattr=-sign-ext -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s -check-prefixes=CHECK,NO-SIGNEXT
+; RUN: llc < %s -O0 --global-isel -mattr=+sign-ext -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s -check-prefixes=CHECK,SIGNEXT
+
+target triple = "wasm32-unknown-unknown"
+
+define zeroext i8 @add_i8_zext(i8 zeroext %x, i8 zeroext %y) {
+; CHECK-LABEL: add_i8_zext:
+; CHECK: .functype add_i8_zext (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push4=, 0
+; CHECK-NEXT: local.get $push3=, 1
+; CHECK-NEXT: i32.add $push1=, $pop4, $pop3
+; CHECK-NEXT: i32.const $push2=, 255
+; CHECK-NEXT: i32.and $push0=, $pop1, $pop2
+; CHECK-NEXT: return $pop0
+ %a = add i8 %x, %y
+ ret i8 %a
+}
+
+define signext i8 @add_i8_sext(i8 signext %x, i8 signext %y) {
+; NO-SIGNEXT-LABEL: add_i8_sext:
+; NO-SIGNEXT: .functype add_i8_sext (i32, i32) -> (i32)
+; NO-SIGNEXT-NEXT: .local i32, i32
+; NO-SIGNEXT-NEXT: # %bb.0:
+; NO-SIGNEXT-NEXT: local.get $push4=, 0
+; NO-SIGNEXT-NEXT: local.get $push3=, 1
+; NO-SIGNEXT-NEXT: i32.add $push2=, $pop4, $pop3
+; NO-SIGNEXT-NEXT: local.set 2, $pop2
+; NO-SIGNEXT-NEXT: i32.const $push5=, 24
+; NO-SIGNEXT-NEXT: local.set 3, $pop5
+; NO-SIGNEXT-NEXT: local.get $push7=, 2
+; NO-SIGNEXT-NEXT: local.get $push6=, 3
+; NO-SIGNEXT-NEXT: i32.shl $push1=, $pop7, $pop6
+; NO-SIGNEXT-NEXT: local.get $push8=, 3
+; NO-SIGNEXT-NEXT: i32.shr_s $push0=, $pop1, $pop8
+; NO-SIGNEXT-NEXT: return $pop0
+;
+; SIGNEXT-LABEL: add_i8_sext:
+; SIGNEXT: .functype add_i8_sext (i32, i32) -> (i32)
+; SIGNEXT-NEXT: # %bb.0:
+; SIGNEXT-NEXT: local.get $push3=, 0
+; SIGNEXT-NEXT: local.get $push2=, 1
+; SIGNEXT-NEXT: i32.add $push1=, $pop3, $pop2
+; SIGNEXT-NEXT: i32.extend8_s $push0=, $pop1
+; SIGNEXT-NEXT: return $pop0
+ %a = add i8 %x, %y
+ ret i8 %a
+}
+
+define i8 @add_i8_aext(i8 %x, i8 %y) {
+; CHECK-LABEL: add_i8_aext:
+; CHECK: .functype add_i8_aext (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.add $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = add i8 %x, %y
+ ret i8 %a
+}
+
+define zeroext i16 @add_i16_zext(i16 zeroext %x, i16 zeroext %y) {
+; CHECK-LABEL: add_i16_zext:
+; CHECK: .functype add_i16_zext (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push4=, 0
+; CHECK-NEXT: local.get $push3=, 1
+; CHECK-NEXT: i32.add $push1=, $pop4, $pop3
+; CHECK-NEXT: i32.const $push2=, 65535
+; CHECK-NEXT: i32.and $push0=, $pop1, $pop2
+; CHECK-NEXT: return $pop0
+ %a = add i16 %x, %y
+ ret i16 %a
+}
+
+define signext i16 @add_i16_sext(i16 signext %x, i16 signext %y) {
+; NO-SIGNEXT-LABEL: add_i16_sext:
+; NO-SIGNEXT: .functype add_i16_sext (i32, i32) -> (i32)
+; NO-SIGNEXT-NEXT: .local i32, i32
+; NO-SIGNEXT-NEXT: # %bb.0:
+; NO-SIGNEXT-NEXT: local.get $push4=, 0
+; NO-SIGNEXT-NEXT: local.get $push3=, 1
+; NO-SIGNEXT-NEXT: i32.add $push2=, $pop4, $pop3
+; NO-SIGNEXT-NEXT: local.set 2, $pop2
+; NO-SIGNEXT-NEXT: i32.const $push5=, 16
+; NO-SIGNEXT-NEXT: local.set 3, $pop5
+; NO-SIGNEXT-NEXT: local.get $push7=, 2
+; NO-SIGNEXT-NEXT: local.get $push6=, 3
+; NO-SIGNEXT-NEXT: i32.shl $push1=, $pop7, $pop6
+; NO-SIGNEXT-NEXT: local.get $push8=, 3
+; NO-SIGNEXT-NEXT: i32.shr_s $push0=, $pop1, $pop8
+; NO-SIGNEXT-NEXT: return $pop0
+;
+; SIGNEXT-LABEL: add_i16_sext:
+; SIGNEXT: .functype add_i16_sext (i32, i32) -> (i32)
+; SIGNEXT-NEXT: # %bb.0:
+; SIGNEXT-NEXT: local.get $push3=, 0
+; SIGNEXT-NEXT: local.get $push2=, 1
+; SIGNEXT-NEXT: i32.add $push1=, $pop3, $pop2
+; SIGNEXT-NEXT: i32.extend16_s $push0=, $pop1
+; SIGNEXT-NEXT: return $pop0
+ %a = add i16 %x, %y
+ ret i16 %a
+}
+
+define i16 @add_i16_aext(i16 %x, i16 %y) {
+; CHECK-LABEL: add_i16_aext:
+; CHECK: .functype add_i16_aext (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.add $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = add i16 %x, %y
+ ret i16 %a
+}
+
+define i32 @add_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: add_i32:
+; CHECK: .functype add_i32 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.add $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = add i32 %x, %y
+ ret i32 %a
+}
+
+define i64 @add_i64(i64 %x, i64 %y) {
+; CHECK-LABEL: add_i64:
+; CHECK: .functype add_i64 (i64, i64) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i64.add $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = add i64 %x, %y
+ ret i64 %a
+}
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/and.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/and.ll
new file mode 100644
index 0000000000000..f85814a7d3261
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/and.ll
@@ -0,0 +1,64 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O0 --global-isel -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
+
+target triple = "wasm32-unknown-unknown"
+
+define i1 @and_i1(i1 %x, i1 %y) {
+; CHECK-LABEL: and_i1:
+; CHECK: .functype and_i1 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.and $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = and i1 %x, %y
+ ret i1 %a
+}
+
+define i8 @and_i8(i8 %x, i8 %y) {
+; CHECK-LABEL: and_i8:
+; CHECK: .functype and_i8 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.and $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = and i8 %x, %y
+ ret i8 %a
+}
+
+define i16 @and_i16(i16 %x, i16 %y) {
+; CHECK-LABEL: and_i16:
+; CHECK: .functype and_i16 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.and $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = and i16 %x, %y
+ ret i16 %a
+}
+
+define i32 @and_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: and_i32:
+; CHECK: .functype and_i32 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.and $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = and i32 %x, %y
+ ret i32 %a
+}
+
+define i64 @and_i64(i64 %x, i64 %y) {
+; CHECK-LABEL: and_i64:
+; CHECK: .functype and_i64 (i64, i64) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i64.and $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = and i64 %x, %y
+ ret i64 %a
+}
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/anyext.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/anyext.mir
similarity index 97%
rename from llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/anyext.mir
rename to llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/anyext.mir
index befdee3ca3181..112c949943f19 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/anyext.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/anyext.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select %s -o - | FileCheck %s
---
name: aext_i8_i32
@@ -38,6 +38,7 @@ body: |
%2:i64(s64) = G_ANYEXT %0(s8)
RETURN %2(s64), implicit-def $arguments
...
+
---
name: aext_i16_i32
alignment: 1
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.ll
new file mode 100644
index 0000000000000..5dc2d30966e03
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.ll
@@ -0,0 +1,183 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O0 --global-isel -mattr=-sign-ext -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s -check-prefixes=CHECK,NO-SIGNEXT
+; RUN: llc < %s -O0 --global-isel -mattr=+sign-ext -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s -check-prefixes=CHECK,SIGNEXT
+
+target triple = "wasm32-unknown-unknown"
+
+define i8 @ashr_i8(i8 %x) {
+; NO-SIGNEXT-LABEL: ashr_i8:
+; NO-SIGNEXT: .functype ashr_i8 (i32) -> (i32)
+; NO-SIGNEXT-NEXT: .local i32, i32
+; NO-SIGNEXT-NEXT: # %bb.0:
+; NO-SIGNEXT-NEXT: i32.const $push3=, 5
+; NO-SIGNEXT-NEXT: local.set 1, $pop3
+; NO-SIGNEXT-NEXT: i32.const $push4=, 24
+; NO-SIGNEXT-NEXT: local.set 2, $pop4
+; NO-SIGNEXT-NEXT: local.get $push6=, 0
+; NO-SIGNEXT-NEXT: local.get $push5=, 2
+; NO-SIGNEXT-NEXT: i32.shl $push2=, $pop6, $pop5
+; NO-SIGNEXT-NEXT: local.get $push7=, 2
+; NO-SIGNEXT-NEXT: i32.shr_s $push0=, $pop2, $pop7
+; NO-SIGNEXT-NEXT: local.get $push8=, 1
+; NO-SIGNEXT-NEXT: i32.shr_s $push1=, $pop0, $pop8
+; NO-SIGNEXT-NEXT: return $pop1
+;
+; SIGNEXT-LABEL: ashr_i8:
+; SIGNEXT: .functype ashr_i8 (i32) -> (i32)
+; SIGNEXT-NEXT: .local i32
+; SIGNEXT-NEXT: # %bb.0:
+; SIGNEXT-NEXT: i32.const $push2=, 5
+; SIGNEXT-NEXT: local.set 1, $pop2
+; SIGNEXT-NEXT: local.get $push3=, 0
+; SIGNEXT-NEXT: i32.extend8_s $push0=, $pop3
+; SIGNEXT-NEXT: local.get $push4=, 1
+; SIGNEXT-NEXT: i32.shr_s $push1=, $pop0, $pop4
+; SIGNEXT-NEXT: return $pop1
+ %a = ashr i8 %x, 5
+ ret i8 %a
+}
+
+define i8 @ashrv_i8(i8 %x, i8 %y) {
+; NO-SIGNEXT-LABEL: ashrv_i8:
+; NO-SIGNEXT: .functype ashrv_i8 (i32, i32) -> (i32)
+; NO-SIGNEXT-NEXT: .local i32
+; NO-SIGNEXT-NEXT: # %bb.0:
+; NO-SIGNEXT-NEXT: i32.const $push5=, 24
+; NO-SIGNEXT-NEXT: local.set 2, $pop5
+; NO-SIGNEXT-NEXT: local.get $push7=, 0
+; NO-SIGNEXT-NEXT: local.get $push6=, 2
+; NO-SIGNEXT-NEXT: i32.shl $push4=, $pop7, $pop6
+; NO-SIGNEXT-NEXT: local.get $push8=, 2
+; NO-SIGNEXT-NEXT: i32.shr_s $push0=, $pop4, $pop8
+; NO-SIGNEXT-NEXT: local.get $push9=, 1
+; NO-SIGNEXT-NEXT: i32.const $push3=, 255
+; NO-SIGNEXT-NEXT: i32.and $push2=, $pop9, $pop3
+; NO-SIGNEXT-NEXT: i32.shr_s $push1=, $pop0, $pop2
+; NO-SIGNEXT-NEXT: return $pop1
+;
+; SIGNEXT-LABEL: ashrv_i8:
+; SIGNEXT: .functype ashrv_i8 (i32, i32) -> (i32)
+; SIGNEXT-NEXT: # %bb.0:
+; SIGNEXT-NEXT: local.get $push4=, 0
+; SIGNEXT-NEXT: i32.extend8_s $push0=, $pop4
+; SIGNEXT-NEXT: local.get $push5=, 1
+; SIGNEXT-NEXT: i32.const $push3=, 255
+; SIGNEXT-NEXT: i32.and $push2=, $pop5, $pop3
+; SIGNEXT-NEXT: i32.shr_s $push1=, $pop0, $pop2
+; SIGNEXT-NEXT: return $pop1
+ %a = ashr i8 %x, %y
+ ret i8 %a
+}
+
+define i16 @ashr_i16(i16 %x) {
+; NO-SIGNEXT-LABEL: ashr_i16:
+; NO-SIGNEXT: .functype ashr_i16 (i32) -> (i32)
+; NO-SIGNEXT-NEXT: .local i32, i32
+; NO-SIGNEXT-NEXT: # %bb.0:
+; NO-SIGNEXT-NEXT: i32.const $push3=, 13
+; NO-SIGNEXT-NEXT: local.set 1, $pop3
+; NO-SIGNEXT-NEXT: i32.const $push4=, 16
+; NO-SIGNEXT-NEXT: local.set 2, $pop4
+; NO-SIGNEXT-NEXT: local.get $push6=, 0
+; NO-SIGNEXT-NEXT: local.get $push5=, 2
+; NO-SIGNEXT-NEXT: i32.shl $push2=, $pop6, $pop5
+; NO-SIGNEXT-NEXT: local.get $push7=, 2
+; NO-SIGNEXT-NEXT: i32.shr_s $push0=, $pop2, $pop7
+; NO-SIGNEXT-NEXT: local.get $push8=, 1
+; NO-SIGNEXT-NEXT: i32.shr_s $push1=, $pop0, $pop8
+; NO-SIGNEXT-NEXT: return $pop1
+;
+; SIGNEXT-LABEL: ashr_i16:
+; SIGNEXT: .functype ashr_i16 (i32) -> (i32)
+; SIGNEXT-NEXT: .local i32
+; SIGNEXT-NEXT: # %bb.0:
+; SIGNEXT-NEXT: i32.const $push2=, 13
+; SIGNEXT-NEXT: local.set 1, $pop2
+; SIGNEXT-NEXT: local.get $push3=, 0
+; SIGNEXT-NEXT: i32.extend16_s $push0=, $pop3
+; SIGNEXT-NEXT: local.get $push4=, 1
+; SIGNEXT-NEXT: i32.shr_s $push1=, $pop0, $pop4
+; SIGNEXT-NEXT: return $pop1
+ %a = ashr i16 %x, 13
+ ret i16 %a
+}
+
+define i16 @ashrv_i16(i16 %x, i16 %y) {
+; NO-SIGNEXT-LABEL: ashrv_i16:
+; NO-SIGNEXT: .functype ashrv_i16 (i32, i32) -> (i32)
+; NO-SIGNEXT-NEXT: .local i32
+; NO-SIGNEXT-NEXT: # %bb.0:
+; NO-SIGNEXT-NEXT: i32.const $push5=, 16
+; NO-SIGNEXT-NEXT: local.set 2, $pop5
+; NO-SIGNEXT-NEXT: local.get $push7=, 0
+; NO-SIGNEXT-NEXT: local.get $push6=, 2
+; NO-SIGNEXT-NEXT: i32.shl $push4=, $pop7, $pop6
+; NO-SIGNEXT-NEXT: local.get $push8=, 2
+; NO-SIGNEXT-NEXT: i32.shr_s $push0=, $pop4, $pop8
+; NO-SIGNEXT-NEXT: local.get $push9=, 1
+; NO-SIGNEXT-NEXT: i32.const $push3=, 65535
+; NO-SIGNEXT-NEXT: i32.and $push2=, $pop9, $pop3
+; NO-SIGNEXT-NEXT: i32.shr_s $push1=, $pop0, $pop2
+; NO-SIGNEXT-NEXT: return $pop1
+;
+; SIGNEXT-LABEL: ashrv_i16:
+; SIGNEXT: .functype ashrv_i16 (i32, i32) -> (i32)
+; SIGNEXT-NEXT: # %bb.0:
+; SIGNEXT-NEXT: local.get $push4=, 0
+; SIGNEXT-NEXT: i32.extend16_s $push0=, $pop4
+; SIGNEXT-NEXT: local.get $push5=, 1
+; SIGNEXT-NEXT: i32.const $push3=, 65535
+; SIGNEXT-NEXT: i32.and $push2=, $pop5, $pop3
+; SIGNEXT-NEXT: i32.shr_s $push1=, $pop0, $pop2
+; SIGNEXT-NEXT: return $pop1
+ %a = ashr i16 %x, %y
+ ret i16 %a
+}
+
+define i32 @ashr_i32(i32 %x) {
+; CHECK-LABEL: ashr_i32:
+; CHECK: .functype ashr_i32 (i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: i32.const $push0=, 21
+; CHECK-NEXT: i32.shr_s $push1=, $pop2, $pop0
+; CHECK-NEXT: return $pop1
+ %a = ashr i32 %x, 21
+ ret i32 %a
+}
+
+define i32 @ashrv_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: ashrv_i32:
+; CHECK: .functype ashrv_i32 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.shr_s $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = ashr i32 %x, %y
+ ret i32 %a
+}
+
+define i64 @ashr_i64(i64 %x) {
+; CHECK-LABEL: ashr_i64:
+; CHECK: .functype ashr_i64 (i64) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: i64.const $push0=, 37
+; CHECK-NEXT: i64.shr_s $push1=, $pop2, $pop0
+; CHECK-NEXT: return $pop1
+ %a = ashr i64 %x, 37
+ ret i64 %a
+}
+
+define i64 @ashrv_i64(i64 %x, i64 %y) {
+; CHECK-LABEL: ashrv_i64:
+; CHECK: .functype ashrv_i64 (i64, i64) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i64.shr_s $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = ashr i64 %x, %y
+ ret i64 %a
+}
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.mir
new file mode 100644
index 0000000000000..095017f6f5096
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ashr.mir
@@ -0,0 +1,93 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: ashr_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ashr_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s8) = G_CONSTANT i8 21
+ %2:_(s32) = G_ASHR %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: ashrv_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ashrv_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_S_I32_:%[0-9]+]]:i32 = SHR_S_I32 [[ARGUMENT_i32_]], [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_S_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %2(s32)
+ %3:_(s32) = G_ASHR %0, %1
+ RETURN %3(s32), implicit-def $arguments
+...
+
+---
+name: ashr_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ashr_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_]], [[CONST_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_S_I64_:%[0-9]+]]:i64 = SHR_S_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_S_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s8) = G_CONSTANT i8 37
+ %2:_(s64) = G_ASHR %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
+---
+name: ashrv_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ashrv_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_S_I64_:%[0-9]+]]:i64 = SHR_S_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_S_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %2(s32)
+ %3:_(s64) = G_ASHR %0, %1
+ RETURN %3(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/constant.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/constant.ll
new file mode 100644
index 0000000000000..8ceda5bb3740a
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/constant.ll
@@ -0,0 +1,85 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O0 --global-isel -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
+
+target triple = "wasm32-unknown-unknown"
+
+define i1 @const_i1() {
+; CHECK-LABEL: const_i1:
+; CHECK: .functype const_i1 () -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: i32.const $push0=, 1
+; CHECK-NEXT: return $pop0
+ ret i1 true
+}
+
+define zeroext i8 @const_i8_zext() {
+; CHECK-LABEL: const_i8_zext:
+; CHECK: .functype const_i8_zext () -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: i32.const $push0=, 255
+; CHECK-NEXT: return $pop0
+ ret i8 255
+}
+
+define signext i8 @const_i8_sext() {
+; CHECK-LABEL: const_i8_sext:
+; CHECK: .functype const_i8_sext () -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: i32.const $push0=, -1
+; CHECK-NEXT: return $pop0
+ ret i8 255
+}
+
+define i8 @const_i8_aext() {
+; CHECK-LABEL: const_i8_aext:
+; CHECK: .functype const_i8_aext () -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: i32.const $push0=, -1
+; CHECK-NEXT: return $pop0
+ ret i8 255
+}
+
+define zeroext i16 @const_i16_zext() {
+; CHECK-LABEL: const_i16_zext:
+; CHECK: .functype const_i16_zext () -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: i32.const $push0=, 65535
+; CHECK-NEXT: return $pop0
+ ret i16 65535
+}
+
+define signext i16 @const_i16_sext() {
+; CHECK-LABEL: const_i16_sext:
+; CHECK: .functype const_i16_sext () -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: i32.const $push0=, -1
+; CHECK-NEXT: return $pop0
+ ret i16 65535
+}
+
+define i16 @const_i16_aext() {
+; CHECK-LABEL: const_i16_aext:
+; CHECK: .functype const_i16_aext () -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: i32.const $push0=, -1
+; CHECK-NEXT: return $pop0
+ ret i16 65535
+}
+
+define i32 @const_i32() {
+; CHECK-LABEL: const_i32:
+; CHECK: .functype const_i32 () -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: i32.const $push0=, -1
+; CHECK-NEXT: return $pop0
+ ret i32 4294967295
+}
+
+define i64 @const_i64() {
+; CHECK-LABEL: const_i64:
+; CHECK: .functype const_i64 () -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: i64.const $push0=, -1
+; CHECK-NEXT: return $pop0
+ ret i64 18446744073709551615
+}
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctlz.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctlz.ll
new file mode 100644
index 0000000000000..dec69345a9905
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctlz.ll
@@ -0,0 +1,113 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O0 --global-isel -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
+
+target triple = "wasm32-unknown-unknown"
+
+declare i8 @llvm.ctlz.i8(i8, i1)
+declare i16 @llvm.ctlz.i16(i16, i1)
+declare i32 @llvm.ctlz.i32(i32, i1)
+declare i64 @llvm.ctlz.i64(i64, i1)
+
+define i8 @ctlz_i8(i8 %x) {
+; CHECK-LABEL: ctlz_i8:
+; CHECK: .functype ctlz_i8 (i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push5=, 0
+; CHECK-NEXT: i32.const $push4=, 255
+; CHECK-NEXT: i32.and $push0=, $pop5, $pop4
+; CHECK-NEXT: i32.clz $push1=, $pop0
+; CHECK-NEXT: i32.const $push2=, 24
+; CHECK-NEXT: i32.sub $push3=, $pop1, $pop2
+; CHECK-NEXT: return $pop3
+ %a = call i8 @llvm.ctlz.i8(i8 %x, i1 false)
+ ret i8 %a
+}
+
+define i8 @ctlz_zundef_i8(i8 %x) {
+; CHECK-LABEL: ctlz_zundef_i8:
+; CHECK: .functype ctlz_zundef_i8 (i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push5=, 0
+; CHECK-NEXT: i32.const $push4=, 255
+; CHECK-NEXT: i32.and $push0=, $pop5, $pop4
+; CHECK-NEXT: i32.clz $push1=, $pop0
+; CHECK-NEXT: i32.const $push2=, 24
+; CHECK-NEXT: i32.sub $push3=, $pop1, $pop2
+; CHECK-NEXT: return $pop3
+ %a = call i8 @llvm.ctlz.i8(i8 %x, i1 true)
+ ret i8 %a
+}
+
+define i16 @ctlz_i16(i16 %x) {
+; CHECK-LABEL: ctlz_i16:
+; CHECK: .functype ctlz_i16 (i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push5=, 0
+; CHECK-NEXT: i32.const $push4=, 65535
+; CHECK-NEXT: i32.and $push0=, $pop5, $pop4
+; CHECK-NEXT: i32.clz $push1=, $pop0
+; CHECK-NEXT: i32.const $push2=, 16
+; CHECK-NEXT: i32.sub $push3=, $pop1, $pop2
+; CHECK-NEXT: return $pop3
+ %a = call i16 @llvm.ctlz.i16(i16 %x, i1 false)
+ ret i16 %a
+}
+
+define i16 @ctlz_zundef_i16(i16 %x) {
+; CHECK-LABEL: ctlz_zundef_i16:
+; CHECK: .functype ctlz_zundef_i16 (i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push5=, 0
+; CHECK-NEXT: i32.const $push4=, 65535
+; CHECK-NEXT: i32.and $push0=, $pop5, $pop4
+; CHECK-NEXT: i32.clz $push1=, $pop0
+; CHECK-NEXT: i32.const $push2=, 16
+; CHECK-NEXT: i32.sub $push3=, $pop1, $pop2
+; CHECK-NEXT: return $pop3
+ %a = call i16 @llvm.ctlz.i16(i16 %x, i1 true)
+ ret i16 %a
+}
+
+define i32 @ctlz_i32(i32 %x) {
+; CHECK-LABEL: ctlz_i32:
+; CHECK: .functype ctlz_i32 (i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push1=, 0
+; CHECK-NEXT: i32.clz $push0=, $pop1
+; CHECK-NEXT: return $pop0
+ %a = call i32 @llvm.ctlz.i32(i32 %x, i1 false)
+ ret i32 %a
+}
+
+define i32 @ctlz_zundef_i32(i32 %x) {
+; CHECK-LABEL: ctlz_zundef_i32:
+; CHECK: .functype ctlz_zundef_i32 (i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push1=, 0
+; CHECK-NEXT: i32.clz $push0=, $pop1
+; CHECK-NEXT: return $pop0
+ %a = call i32 @llvm.ctlz.i32(i32 %x, i1 true)
+ ret i32 %a
+}
+
+define i64 @ctlz_i64(i64 %x) {
+; CHECK-LABEL: ctlz_i64:
+; CHECK: .functype ctlz_i64 (i64) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push1=, 0
+; CHECK-NEXT: i64.clz $push0=, $pop1
+; CHECK-NEXT: return $pop0
+ %a = call i64 @llvm.ctlz.i64(i64 %x, i1 false)
+ ret i64 %a
+}
+
+define i64 @ctlz_zundef_i64(i64 %x) {
+; CHECK-LABEL: ctlz_zundef_i64:
+; CHECK: .functype ctlz_zundef_i64 (i64) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push1=, 0
+; CHECK-NEXT: i64.clz $push0=, $pop1
+; CHECK-NEXT: return $pop0
+ %a = call i64 @llvm.ctlz.i64(i64 %x, i1 true)
+ ret i64 %a
+}
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ctlz.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctlz.mir
similarity index 60%
rename from llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ctlz.mir
rename to llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctlz.mir
index 4074d5308e403..938a411826e1a 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/ctlz.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctlz.mir
@@ -2,122 +2,93 @@
# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---
-name: ctlz_i8
+name: ctlz_i32_i8
alignment: 1
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $arguments
- ; CHECK-LABEL: name: ctlz_i8
+ ; CHECK-LABEL: name: ctlz_i32_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CLZ_I32_:%[0-9]+]]:i32 = CLZ_I32 [[AND_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 24, implicit-def dead $arguments
- ; CHECK-NEXT: [[SUB_I32_:%[0-9]+]]:i32 = nuw SUB_I32 [[CLZ_I32_]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SUB_I32_]], implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %1(s32)
- %2:_(s8) = G_CTLZ %0
- %3:_(s32) = G_ANYEXT %2(s8)
- RETURN %3(s32), implicit-def $arguments
-
+ ; CHECK-NEXT: [[CLZ_I32_:%[0-9]+]]:i32 = CLZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[CLZ_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s8) = G_CTLZ %0
+ %2:_(s32) = G_ANYEXT %1(s8)
+ RETURN %2(s32), implicit-def $arguments
...
---
-name: ctlz_i16
+name: ctlz_i64_i8
alignment: 1
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $arguments
- ; CHECK-LABEL: name: ctlz_i16
+ ; CHECK-LABEL: name: ctlz_i64_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 65535, implicit-def dead $arguments
- ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CLZ_I32_:%[0-9]+]]:i32 = CLZ_I32 [[AND_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 16, implicit-def dead $arguments
- ; CHECK-NEXT: [[SUB_I32_:%[0-9]+]]:i32 = nuw SUB_I32 [[CLZ_I32_]], [[CONST_I32_1]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[SUB_I32_]], implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %1(s32)
- %2:_(s16) = G_CTLZ %0
- %3:_(s32) = G_ANYEXT %2(s16)
- RETURN %3(s32), implicit-def $arguments
-
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CLZ_I64_:%[0-9]+]]:i64 = CLZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[CLZ_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s8) = G_CTLZ %0
+ %2:_(s32) = G_ANYEXT %1(s8)
+ RETURN %2(s32), implicit-def $arguments
...
---
-name: ctlz_i32
+name: ctlz_i64_i32
alignment: 1
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $arguments
- ; CHECK-LABEL: name: ctlz_i32
+ ; CHECK-LABEL: name: ctlz_i64_i32
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CLZ_I32_:%[0-9]+]]:i32 = CLZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CLZ_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CLZ_I64_:%[0-9]+]]:i64 = CLZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[CLZ_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
%1:_(s32) = G_CTLZ %0
RETURN %1(s32), implicit-def $arguments
-
...
+
+
---
-name: ctlz_i32_i8
+name: ctlz_zundef_i32_i8
alignment: 1
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $arguments
- ; CHECK-LABEL: name: ctlz_i32_i8
+ ; CHECK-LABEL: name: ctlz_zundef_i32_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
; CHECK-NEXT: [[CLZ_I32_:%[0-9]+]]:i32 = CLZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
; CHECK-NEXT: RETURN [[CLZ_I32_]], implicit-def $arguments
%0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s8) = G_CTLZ %0
+ %1:_(s8) = G_CTLZ_ZERO_UNDEF %0
%2:_(s32) = G_ANYEXT %1(s8)
RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: ctlz_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: ctlz_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CLZ_I64_:%[0-9]+]]:i64 = CLZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CLZ_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_CTLZ %0
- RETURN %1(s64), implicit-def $arguments
-
...
---
-name: ctlz_i64_i8
+name: ctlz_zundef_i64_i8
alignment: 1
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $arguments
- ; CHECK-LABEL: name: ctlz_i64_i8
+ ; CHECK-LABEL: name: ctlz_zundef_i64_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
@@ -125,20 +96,19 @@ body: |
; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[CLZ_I64_]], implicit-def dead $arguments
; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
%0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s8) = G_CTLZ %0
+ %1:_(s8) = G_CTLZ_ZERO_UNDEF %0
%2:_(s32) = G_ANYEXT %1(s8)
RETURN %2(s32), implicit-def $arguments
-
...
---
-name: ctlz_i64_i32
+name: ctlz_zundef_i64_i32
alignment: 1
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $arguments
- ; CHECK-LABEL: name: ctlz_i64_i32
+ ; CHECK-LABEL: name: ctlz_zundef_i64_i32
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
@@ -146,7 +116,6 @@ body: |
; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[CLZ_I64_]], implicit-def dead $arguments
; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
%0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s32) = G_CTLZ %0
+ %1:_(s32) = G_CTLZ_ZERO_UNDEF %0
RETURN %1(s32), implicit-def $arguments
-
...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctpop.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctpop.ll
new file mode 100644
index 0000000000000..ab4168f92dae8
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctpop.ll
@@ -0,0 +1,57 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O0 --global-isel -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
+
+target triple = "wasm32-unknown-unknown"
+
+declare i8 @llvm.ctpop.i8(i8)
+declare i16 @llvm.ctpop.i16(i16)
+declare i32 @llvm.ctpop.i32(i32)
+declare i64 @llvm.ctpop.i64(i64)
+
+define i8 @ctpop_i8(i8 %x) {
+; CHECK-LABEL: ctpop_i8:
+; CHECK: .functype ctpop_i8 (i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push3=, 0
+; CHECK-NEXT: i32.const $push2=, 255
+; CHECK-NEXT: i32.and $push0=, $pop3, $pop2
+; CHECK-NEXT: i32.popcnt $push1=, $pop0
+; CHECK-NEXT: return $pop1
+ %a = call i8 @llvm.ctpop.i8(i8 %x)
+ ret i8 %a
+}
+
+define i16 @ctpop_i16(i16 %x) {
+; CHECK-LABEL: ctpop_i16:
+; CHECK: .functype ctpop_i16 (i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push3=, 0
+; CHECK-NEXT: i32.const $push2=, 65535
+; CHECK-NEXT: i32.and $push0=, $pop3, $pop2
+; CHECK-NEXT: i32.popcnt $push1=, $pop0
+; CHECK-NEXT: return $pop1
+ %a = call i16 @llvm.ctpop.i16(i16 %x)
+ ret i16 %a
+}
+
+define i32 @ctpop_i32(i32 %x) {
+; CHECK-LABEL: ctpop_i32:
+; CHECK: .functype ctpop_i32 (i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push1=, 0
+; CHECK-NEXT: i32.popcnt $push0=, $pop1
+; CHECK-NEXT: return $pop0
+ %a = call i32 @llvm.ctpop.i32(i32 %x)
+ ret i32 %a
+}
+
+define i64 @ctpop_i64(i64 %x) {
+; CHECK-LABEL: ctpop_i64:
+; CHECK: .functype ctpop_i64 (i64) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push1=, 0
+; CHECK-NEXT: i64.popcnt $push0=, $pop1
+; CHECK-NEXT: return $pop0
+ %a = call i64 @llvm.ctpop.i64(i64 %x)
+ ret i64 %a
+}
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctpop.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctpop.mir
new file mode 100644
index 0000000000000..4883f9a363736
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/ctpop.mir
@@ -0,0 +1,62 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: ctpop_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctpop_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[POPCNT_I32_:%[0-9]+]]:i32 = POPCNT_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[POPCNT_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s8) = G_CTPOP %0
+ %2:_(s32) = G_ANYEXT %1(s8)
+ RETURN %2(s32), implicit-def $arguments
+...
+
+---
+name: ctpop_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctpop_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[POPCNT_I64_:%[0-9]+]]:i64 = POPCNT_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[POPCNT_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s8) = G_CTPOP %0
+ %2:_(s32) = G_ANYEXT %1(s8)
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: ctpop_i64_i32
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: ctpop_i64_i32
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[POPCNT_I64_:%[0-9]+]]:i64 = POPCNT_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[POPCNT_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s32) = G_CTPOP %0
+ RETURN %1(s32), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/cttz.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/cttz.ll
new file mode 100644
index 0000000000000..4f12a8c080c1a
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/cttz.ll
@@ -0,0 +1,105 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O0 --global-isel -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
+
+target triple = "wasm32-unknown-unknown"
+
+declare i8 @llvm.cttz.i8(i8, i1)
+declare i16 @llvm.cttz.i16(i16, i1)
+declare i32 @llvm.cttz.i32(i32, i1)
+declare i64 @llvm.cttz.i64(i64, i1)
+
+define i8 @cttz_i8(i8 %x) {
+; CHECK-LABEL: cttz_i8:
+; CHECK: .functype cttz_i8 (i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push3=, 0
+; CHECK-NEXT: i32.const $push0=, 256
+; CHECK-NEXT: i32.or $push1=, $pop3, $pop0
+; CHECK-NEXT: i32.ctz $push2=, $pop1
+; CHECK-NEXT: return $pop2
+ %a = call i8 @llvm.cttz.i8(i8 %x, i1 false)
+ ret i8 %a
+}
+
+define i8 @cttz_zundef_i8(i8 %x) {
+; CHECK-LABEL: cttz_zundef_i8:
+; CHECK: .functype cttz_zundef_i8 (i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push3=, 0
+; CHECK-NEXT: i32.const $push0=, 256
+; CHECK-NEXT: i32.or $push1=, $pop3, $pop0
+; CHECK-NEXT: i32.ctz $push2=, $pop1
+; CHECK-NEXT: return $pop2
+ %a = call i8 @llvm.cttz.i8(i8 %x, i1 true)
+ ret i8 %a
+}
+
+define i16 @cttz_i16(i16 %x) {
+; CHECK-LABEL: cttz_i16:
+; CHECK: .functype cttz_i16 (i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push3=, 0
+; CHECK-NEXT: i32.const $push0=, 65536
+; CHECK-NEXT: i32.or $push1=, $pop3, $pop0
+; CHECK-NEXT: i32.ctz $push2=, $pop1
+; CHECK-NEXT: return $pop2
+ %a = call i16 @llvm.cttz.i16(i16 %x, i1 false)
+ ret i16 %a
+}
+
+define i16 @cttz_zundef_i16(i16 %x) {
+; CHECK-LABEL: cttz_zundef_i16:
+; CHECK: .functype cttz_zundef_i16 (i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push3=, 0
+; CHECK-NEXT: i32.const $push0=, 65536
+; CHECK-NEXT: i32.or $push1=, $pop3, $pop0
+; CHECK-NEXT: i32.ctz $push2=, $pop1
+; CHECK-NEXT: return $pop2
+ %a = call i16 @llvm.cttz.i16(i16 %x, i1 true)
+ ret i16 %a
+}
+
+define i32 @cttz_i32(i32 %x) {
+; CHECK-LABEL: cttz_i32:
+; CHECK: .functype cttz_i32 (i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push1=, 0
+; CHECK-NEXT: i32.ctz $push0=, $pop1
+; CHECK-NEXT: return $pop0
+ %a = call i32 @llvm.cttz.i32(i32 %x, i1 false)
+ ret i32 %a
+}
+
+define i32 @cttz_zundef_i32(i32 %x) {
+; CHECK-LABEL: cttz_zundef_i32:
+; CHECK: .functype cttz_zundef_i32 (i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push1=, 0
+; CHECK-NEXT: i32.ctz $push0=, $pop1
+; CHECK-NEXT: return $pop0
+ %a = call i32 @llvm.cttz.i32(i32 %x, i1 true)
+ ret i32 %a
+}
+
+define i64 @cttz_i64(i64 %x) {
+; CHECK-LABEL: cttz_i64:
+; CHECK: .functype cttz_i64 (i64) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push1=, 0
+; CHECK-NEXT: i64.ctz $push0=, $pop1
+; CHECK-NEXT: return $pop0
+ %a = call i64 @llvm.cttz.i64(i64 %x, i1 false)
+ ret i64 %a
+}
+
+define i64 @cttz_zundef_i64(i64 %x) {
+; CHECK-LABEL: cttz_zundef_i64:
+; CHECK: .functype cttz_zundef_i64 (i64) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push1=, 0
+; CHECK-NEXT: i64.ctz $push0=, $pop1
+; CHECK-NEXT: return $pop0
+ %a = call i64 @llvm.cttz.i64(i64 %x, i1 true)
+ ret i64 %a
+}
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/cttz.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/cttz.mir
similarity index 65%
rename from llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/cttz.mir
rename to llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/cttz.mir
index 7dc298f9dc402..c6aea452083d2 100644
--- a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/cttz.mir
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/cttz.mir
@@ -2,118 +2,93 @@
# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---
-name: cttz_i8
+name: cttz_i32_i8
alignment: 1
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $arguments
- ; CHECK-LABEL: name: cttz_i8
+ ; CHECK-LABEL: name: cttz_i32_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 256, implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = OR_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CTZ_I32_:%[0-9]+]]:i32 = CTZ_I32 [[OR_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CTZ_I32_:%[0-9]+]]:i32 = CTZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
; CHECK-NEXT: RETURN [[CTZ_I32_]], implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s8) = G_TRUNC %1(s32)
- %2:_(s8) = G_CTTZ %0
- %3:_(s32) = G_ANYEXT %2(s8)
- RETURN %3(s32), implicit-def $arguments
-
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s8) = G_CTTZ %0
+ %2:_(s32) = G_ANYEXT %1(s8)
+ RETURN %2(s32), implicit-def $arguments
...
---
-name: cttz_i16
+name: cttz_i64_i8
alignment: 1
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $arguments
- ; CHECK-LABEL: name: cttz_i16
+ ; CHECK-LABEL: name: cttz_i64_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 65536, implicit-def dead $arguments
- ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = OR_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: [[CTZ_I32_:%[0-9]+]]:i32 = CTZ_I32 [[OR_I32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CTZ_I32_]], implicit-def $arguments
- %1:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %0:_(s16) = G_TRUNC %1(s32)
- %2:_(s16) = G_CTTZ %0
- %3:_(s32) = G_ANYEXT %2(s16)
- RETURN %3(s32), implicit-def $arguments
-
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTZ_I64_:%[0-9]+]]:i64 = CTZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[CTZ_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s8) = G_CTTZ %0
+ %2:_(s32) = G_ANYEXT %1(s8)
+ RETURN %2(s32), implicit-def $arguments
...
---
-name: cttz_i32
+name: cttz_i64_i32
alignment: 1
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $arguments
- ; CHECK-LABEL: name: cttz_i32
+ ; CHECK-LABEL: name: cttz_i64_i32
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
- ; CHECK-NEXT: [[CTZ_I32_:%[0-9]+]]:i32 = CTZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CTZ_I32_]], implicit-def $arguments
- %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CTZ_I64_:%[0-9]+]]:i64 = CTZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[CTZ_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
%1:_(s32) = G_CTTZ %0
RETURN %1(s32), implicit-def $arguments
-
...
+
+
---
-name: cttz_i32_i8
+name: cttz_zundef_i32_i8
alignment: 1
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $arguments
- ; CHECK-LABEL: name: cttz_i32_i8
+ ; CHECK-LABEL: name: cttz_zundef_i32_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
; CHECK-NEXT: [[CTZ_I32_:%[0-9]+]]:i32 = CTZ_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
; CHECK-NEXT: RETURN [[CTZ_I32_]], implicit-def $arguments
%0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
- %1:_(s8) = G_CTTZ %0
+ %1:_(s8) = G_CTTZ_ZERO_UNDEF %0
%2:_(s32) = G_ANYEXT %1(s8)
RETURN %2(s32), implicit-def $arguments
-
-...
----
-name: cttz_i64
-alignment: 1
-tracksRegLiveness: true
-body: |
- bb.1.entry:
- liveins: $arguments
-
- ; CHECK-LABEL: name: cttz_i64
- ; CHECK: liveins: $arguments
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
- ; CHECK-NEXT: [[CTZ_I64_:%[0-9]+]]:i64 = CTZ_I64 [[ARGUMENT_i64_]], implicit-def dead $arguments
- ; CHECK-NEXT: RETURN [[CTZ_I64_]], implicit-def $arguments
- %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s64) = G_CTTZ %0
- RETURN %1(s64), implicit-def $arguments
-
...
---
-name: cttz_i64_i8
+name: cttz_zundef_i64_i8
alignment: 1
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $arguments
- ; CHECK-LABEL: name: cttz_i64_i8
+ ; CHECK-LABEL: name: cttz_zundef_i64_i8
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
@@ -121,20 +96,19 @@ body: |
; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[CTZ_I64_]], implicit-def dead $arguments
; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
%0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s8) = G_CTTZ %0
+ %1:_(s8) = G_CTTZ_ZERO_UNDEF %0
%2:_(s32) = G_ANYEXT %1(s8)
RETURN %2(s32), implicit-def $arguments
-
...
---
-name: cttz_i64_i32
+name: cttz_zundef_i64_i32
alignment: 1
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $arguments
- ; CHECK-LABEL: name: cttz_i64_i32
+ ; CHECK-LABEL: name: cttz_zundef_i64_i32
; CHECK: liveins: $arguments
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
@@ -142,7 +116,6 @@ body: |
; CHECK-NEXT: [[I32_WRAP_I64_:%[0-9]+]]:i32 = I32_WRAP_I64 [[CTZ_I64_]], implicit-def dead $arguments
; CHECK-NEXT: RETURN [[I32_WRAP_I64_]], implicit-def $arguments
%0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
- %1:_(s32) = G_CTTZ %0
+ %1:_(s32) = G_CTTZ_ZERO_UNDEF %0
RETURN %1(s32), implicit-def $arguments
-
...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshl.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshl.ll
new file mode 100644
index 0000000000000..1ca53d31fc96b
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshl.ll
@@ -0,0 +1,221 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O0 --global-isel -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
+
+target triple = "wasm32-unknown-unknown"
+
+declare i8 @llvm.fshl.i8(i8, i8, i8)
+declare i16 @llvm.fshl.i16(i16, i16, i16)
+declare i32 @llvm.fshl.i32(i32, i32, i32)
+declare i64 @llvm.fshl.i64(i64, i64, i64)
+
+define i8 @fshl_i8(i8 %x, i8 %y) {
+; CHECK-LABEL: fshl_i8:
+; CHECK: .functype fshl_i8 (i32, i32) -> (i32)
+; CHECK-NEXT: .local i32, i32
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: i32.const $push5=, 5
+; CHECK-NEXT: local.set 2, $pop5
+; CHECK-NEXT: i32.const $push6=, 3
+; CHECK-NEXT: local.set 3, $pop6
+; CHECK-NEXT: local.get $push8=, 0
+; CHECK-NEXT: local.get $push7=, 2
+; CHECK-NEXT: i32.shl $push3=, $pop8, $pop7
+; CHECK-NEXT: local.get $push9=, 1
+; CHECK-NEXT: i32.const $push4=, 255
+; CHECK-NEXT: i32.and $push1=, $pop9, $pop4
+; CHECK-NEXT: local.get $push10=, 3
+; CHECK-NEXT: i32.shr_u $push2=, $pop1, $pop10
+; CHECK-NEXT: i32.or $push0=, $pop3, $pop2
+; CHECK-NEXT: return $pop0
+ %a = call i8 @llvm.fshl.i8(i8 %x, i8 %y, i8 5)
+ ret i8 %a
+}
+
+define i8 @fshlv_i8(i8 %x, i8 %y, i8 %z) {
+; CHECK-LABEL: fshlv_i8:
+; CHECK: .functype fshlv_i8 (i32, i32, i32) -> (i32)
+; CHECK-NEXT: .local i32, i32, i32, i32
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: i32.const $push10=, 7
+; CHECK-NEXT: local.set 3, $pop10
+; CHECK-NEXT: local.get $push13=, 2
+; CHECK-NEXT: local.get $push12=, 3
+; CHECK-NEXT: i32.and $push11=, $pop13, $pop12
+; CHECK-NEXT: local.set 4, $pop11
+; CHECK-NEXT: local.get $push16=, 3
+; CHECK-NEXT: local.get $push14=, 2
+; CHECK-NEXT: i32.const $push7=, -1
+; CHECK-NEXT: i32.xor $push6=, $pop14, $pop7
+; CHECK-NEXT: i32.and $push15=, $pop16, $pop6
+; CHECK-NEXT: local.set 5, $pop15
+; CHECK-NEXT: i32.const $push17=, 1
+; CHECK-NEXT: local.set 6, $pop17
+; CHECK-NEXT: local.get $push19=, 0
+; CHECK-NEXT: local.get $push18=, 4
+; CHECK-NEXT: i32.shl $push5=, $pop19, $pop18
+; CHECK-NEXT: local.get $push20=, 1
+; CHECK-NEXT: i32.const $push8=, 255
+; CHECK-NEXT: i32.and $push3=, $pop20, $pop8
+; CHECK-NEXT: local.get $push21=, 6
+; CHECK-NEXT: i32.shr_u $push4=, $pop3, $pop21
+; CHECK-NEXT: i32.const $push9=, 255
+; CHECK-NEXT: i32.and $push1=, $pop4, $pop9
+; CHECK-NEXT: local.get $push22=, 5
+; CHECK-NEXT: i32.shr_u $push2=, $pop1, $pop22
+; CHECK-NEXT: i32.or $push0=, $pop5, $pop2
+; CHECK-NEXT: return $pop0
+ %a = call i8 @llvm.fshl.i8(i8 %x, i8 %y, i8 %z)
+ ret i8 %a
+}
+
+define i16 @fshl_i16(i16 %x, i16 %y) {
+; CHECK-LABEL: fshl_i16:
+; CHECK: .functype fshl_i16 (i32, i32) -> (i32)
+; CHECK-NEXT: .local i32, i32
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: i32.const $push5=, 13
+; CHECK-NEXT: local.set 2, $pop5
+; CHECK-NEXT: i32.const $push6=, 3
+; CHECK-NEXT: local.set 3, $pop6
+; CHECK-NEXT: local.get $push8=, 0
+; CHECK-NEXT: local.get $push7=, 2
+; CHECK-NEXT: i32.shl $push3=, $pop8, $pop7
+; CHECK-NEXT: local.get $push9=, 1
+; CHECK-NEXT: i32.const $push4=, 65535
+; CHECK-NEXT: i32.and $push1=, $pop9, $pop4
+; CHECK-NEXT: local.get $push10=, 3
+; CHECK-NEXT: i32.shr_u $push2=, $pop1, $pop10
+; CHECK-NEXT: i32.or $push0=, $pop3, $pop2
+; CHECK-NEXT: return $pop0
+ %a = call i16 @llvm.fshl.i16(i16 %x, i16 %y, i16 13)
+ ret i16 %a
+}
+
+define i16 @fshlv_i16(i16 %x, i16 %y, i16 %z) {
+; CHECK-LABEL: fshlv_i16:
+; CHECK: .functype fshlv_i16 (i32, i32, i32) -> (i32)
+; CHECK-NEXT: .local i32, i32, i32, i32
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: i32.const $push10=, 15
+; CHECK-NEXT: local.set 3, $pop10
+; CHECK-NEXT: local.get $push13=, 2
+; CHECK-NEXT: local.get $push12=, 3
+; CHECK-NEXT: i32.and $push11=, $pop13, $pop12
+; CHECK-NEXT: local.set 4, $pop11
+; CHECK-NEXT: local.get $push16=, 3
+; CHECK-NEXT: local.get $push14=, 2
+; CHECK-NEXT: i32.const $push7=, -1
+; CHECK-NEXT: i32.xor $push6=, $pop14, $pop7
+; CHECK-NEXT: i32.and $push15=, $pop16, $pop6
+; CHECK-NEXT: local.set 5, $pop15
+; CHECK-NEXT: i32.const $push17=, 1
+; CHECK-NEXT: local.set 6, $pop17
+; CHECK-NEXT: local.get $push19=, 0
+; CHECK-NEXT: local.get $push18=, 4
+; CHECK-NEXT: i32.shl $push5=, $pop19, $pop18
+; CHECK-NEXT: local.get $push20=, 1
+; CHECK-NEXT: i32.const $push8=, 65535
+; CHECK-NEXT: i32.and $push3=, $pop20, $pop8
+; CHECK-NEXT: local.get $push21=, 6
+; CHECK-NEXT: i32.shr_u $push4=, $pop3, $pop21
+; CHECK-NEXT: i32.const $push9=, 65535
+; CHECK-NEXT: i32.and $push1=, $pop4, $pop9
+; CHECK-NEXT: local.get $push22=, 5
+; CHECK-NEXT: i32.shr_u $push2=, $pop1, $pop22
+; CHECK-NEXT: i32.or $push0=, $pop5, $pop2
+; CHECK-NEXT: return $pop0
+ %a = call i16 @llvm.fshl.i16(i16 %x, i16 %y, i16 %z)
+ ret i16 %a
+}
+
+define i32 @fshl_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: fshl_i32:
+; CHECK: .functype fshl_i32 (i32, i32) -> (i32)
+; CHECK-NEXT: .local i32, i32
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: i32.const $push3=, 21
+; CHECK-NEXT: local.set 2, $pop3
+; CHECK-NEXT: i32.const $push4=, 11
+; CHECK-NEXT: local.set 3, $pop4
+; CHECK-NEXT: local.get $push6=, 0
+; CHECK-NEXT: local.get $push5=, 2
+; CHECK-NEXT: i32.shl $push1=, $pop6, $pop5
+; CHECK-NEXT: local.get $push8=, 1
+; CHECK-NEXT: local.get $push7=, 3
+; CHECK-NEXT: i32.shr_u $push2=, $pop8, $pop7
+; CHECK-NEXT: i32.or $push0=, $pop1, $pop2
+; CHECK-NEXT: return $pop0
+ %a = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 21)
+ ret i32 %a
+}
+
+define i32 @fshlv_i32(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: fshlv_i32:
+; CHECK: .functype fshlv_i32 (i32, i32, i32) -> (i32)
+; CHECK-NEXT: .local i32, i32
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push6=, 2
+; CHECK-NEXT: i32.const $push1=, -1
+; CHECK-NEXT: i32.xor $push5=, $pop6, $pop1
+; CHECK-NEXT: local.set 3, $pop5
+; CHECK-NEXT: i32.const $push7=, 1
+; CHECK-NEXT: local.set 4, $pop7
+; CHECK-NEXT: local.get $push9=, 0
+; CHECK-NEXT: local.get $push8=, 2
+; CHECK-NEXT: i32.shl $push2=, $pop9, $pop8
+; CHECK-NEXT: local.get $push11=, 1
+; CHECK-NEXT: local.get $push10=, 4
+; CHECK-NEXT: i32.shr_u $push3=, $pop11, $pop10
+; CHECK-NEXT: local.get $push12=, 3
+; CHECK-NEXT: i32.shr_u $push4=, $pop3, $pop12
+; CHECK-NEXT: i32.or $push0=, $pop2, $pop4
+; CHECK-NEXT: return $pop0
+ %a = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %z)
+ ret i32 %a
+}
+
+define i64 @fshl_i64(i64 %x, i64 %y) {
+; CHECK-LABEL: fshl_i64:
+; CHECK: .functype fshl_i64 (i64, i64) -> (i64)
+; CHECK-NEXT: .local i64, i64
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: i64.const $push3=, 37
+; CHECK-NEXT: local.set 2, $pop3
+; CHECK-NEXT: i64.const $push4=, 27
+; CHECK-NEXT: local.set 3, $pop4
+; CHECK-NEXT: local.get $push6=, 0
+; CHECK-NEXT: local.get $push5=, 2
+; CHECK-NEXT: i64.shl $push1=, $pop6, $pop5
+; CHECK-NEXT: local.get $push8=, 1
+; CHECK-NEXT: local.get $push7=, 3
+; CHECK-NEXT: i64.shr_u $push2=, $pop8, $pop7
+; CHECK-NEXT: i64.or $push0=, $pop1, $pop2
+; CHECK-NEXT: return $pop0
+ %a = call i64 @llvm.fshl.i64(i64 %x, i64 %y, i64 37)
+ ret i64 %a
+}
+
+define i64 @fshlv_i64(i64 %x, i64 %y, i64 %z) {
+; CHECK-LABEL: fshlv_i64:
+; CHECK: .functype fshlv_i64 (i64, i64, i64) -> (i64)
+; CHECK-NEXT: .local i64, i64
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push6=, 2
+; CHECK-NEXT: i64.const $push1=, -1
+; CHECK-NEXT: i64.xor $push5=, $pop6, $pop1
+; CHECK-NEXT: local.set 3, $pop5
+; CHECK-NEXT: i64.const $push7=, 1
+; CHECK-NEXT: local.set 4, $pop7
+; CHECK-NEXT: local.get $push9=, 0
+; CHECK-NEXT: local.get $push8=, 2
+; CHECK-NEXT: i64.shl $push2=, $pop9, $pop8
+; CHECK-NEXT: local.get $push11=, 1
+; CHECK-NEXT: local.get $push10=, 4
+; CHECK-NEXT: i64.shr_u $push3=, $pop11, $pop10
+; CHECK-NEXT: local.get $push12=, 3
+; CHECK-NEXT: i64.shr_u $push4=, $pop3, $pop12
+; CHECK-NEXT: i64.or $push0=, $pop2, $pop4
+; CHECK-NEXT: return $pop0
+ %a = call i64 @llvm.fshl.i64(i64 %x, i64 %y, i64 %z)
+ ret i64 %a
+}
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshl.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshl.mir
new file mode 100644
index 0000000000000..f332cad22986f
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshl.mir
@@ -0,0 +1,128 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: fshl_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshl_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 11, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s8) = G_CONSTANT i8 21
+ %3:_(s32) = G_FSHL %0, %1, %2(s8)
+ RETURN %3(s32), implicit-def $arguments
+...
+---
+name: fshlv_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshlv_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32 = ARGUMENT_i32 2, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_2]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[ARGUMENT_i32_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_1]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_1:%[0-9]+]]:i32 = SHR_U_I32 [[SHR_U_I32_]], [[XOR_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %3:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ %2:_(s8) = G_TRUNC %3(s32)
+ %4:_(s32) = G_FSHL %0, %1, %2(s8)
+ RETURN %4(s32), implicit-def $arguments
+...
+
+
+---
+name: fshl_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshl_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 21, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_]], [[CONST_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_2:%[0-9]+]]:i64 = CONST_I64 43, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_3:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_1:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_2]], [[CONST_I64_3]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[AND_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = disjoint OR_I64 [[SHL_I64_]], [[SHR_U_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s8) = G_CONSTANT i8 21
+ %3:_(s64) = G_FSHL %0, %1, %2(s8)
+ RETURN %3(s64), implicit-def $arguments
+...
+---
+name: fshlv_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshlv_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 2, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 63, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[XOR_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_2:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_1:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_1]], [[CONST_I64_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[AND_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[I64_EXTEND_U_I32_1:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[AND_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_3:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_2:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_1]], [[CONST_I64_3]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_1:%[0-9]+]]:i64 = SHR_U_I64 [[SHR_U_I64_]], [[AND_I64_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = disjoint OR_I64 [[SHL_I64_]], [[SHR_U_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %3:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ %2:_(s8) = G_TRUNC %3(s32)
+ %4:_(s64) = G_FSHL %0, %1, %2(s8)
+ RETURN %4(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshr.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshr.ll
new file mode 100644
index 0000000000000..5819d948b2174
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshr.ll
@@ -0,0 +1,201 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O0 --global-isel -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
+
+target triple = "wasm32-unknown-unknown"
+
+declare i8 @llvm.fshr.i8(i8, i8, i8)
+declare i16 @llvm.fshr.i16(i16, i16, i16)
+declare i32 @llvm.fshr.i32(i32, i32, i32)
+declare i64 @llvm.fshr.i64(i64, i64, i64)
+
+define i8 @fshr_i8(i8 %x, i8 %y) {
+; CHECK-LABEL: fshr_i8:
+; CHECK: .functype fshr_i8 (i32, i32) -> (i32)
+; CHECK-NEXT: .local i32
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: i32.const $push6=, 5
+; CHECK-NEXT: local.set 2, $pop6
+; CHECK-NEXT: local.get $push7=, 0
+; CHECK-NEXT: i32.const $push4=, 3
+; CHECK-NEXT: i32.shl $push3=, $pop7, $pop4
+; CHECK-NEXT: local.get $push8=, 1
+; CHECK-NEXT: i32.const $push5=, 255
+; CHECK-NEXT: i32.and $push1=, $pop8, $pop5
+; CHECK-NEXT: local.get $push9=, 2
+; CHECK-NEXT: i32.shr_u $push2=, $pop1, $pop9
+; CHECK-NEXT: i32.or $push0=, $pop3, $pop2
+; CHECK-NEXT: return $pop0
+ %a = call i8 @llvm.fshr.i8(i8 %x, i8 %y, i8 5)
+ ret i8 %a
+}
+
+define i8 @fshrv_i8(i8 %x, i8 %y, i8 %z) {
+; CHECK-LABEL: fshrv_i8:
+; CHECK: .functype fshrv_i8 (i32, i32, i32) -> (i32)
+; CHECK-NEXT: .local i32, i32, i32
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: i32.const $push9=, 7
+; CHECK-NEXT: local.set 3, $pop9
+; CHECK-NEXT: local.get $push12=, 2
+; CHECK-NEXT: local.get $push11=, 3
+; CHECK-NEXT: i32.and $push10=, $pop12, $pop11
+; CHECK-NEXT: local.set 4, $pop10
+; CHECK-NEXT: local.get $push15=, 3
+; CHECK-NEXT: local.get $push13=, 2
+; CHECK-NEXT: i32.const $push7=, -1
+; CHECK-NEXT: i32.xor $push6=, $pop13, $pop7
+; CHECK-NEXT: i32.and $push14=, $pop15, $pop6
+; CHECK-NEXT: local.set 5, $pop14
+; CHECK-NEXT: local.get $push16=, 0
+; CHECK-NEXT: i32.const $push5=, 1
+; CHECK-NEXT: i32.shl $push4=, $pop16, $pop5
+; CHECK-NEXT: local.get $push17=, 5
+; CHECK-NEXT: i32.shl $push3=, $pop4, $pop17
+; CHECK-NEXT: local.get $push18=, 1
+; CHECK-NEXT: i32.const $push8=, 255
+; CHECK-NEXT: i32.and $push1=, $pop18, $pop8
+; CHECK-NEXT: local.get $push19=, 4
+; CHECK-NEXT: i32.shr_u $push2=, $pop1, $pop19
+; CHECK-NEXT: i32.or $push0=, $pop3, $pop2
+; CHECK-NEXT: return $pop0
+ %a = call i8 @llvm.fshr.i8(i8 %x, i8 %y, i8 %z)
+ ret i8 %a
+}
+
+define i16 @fshr_i16(i16 %x, i16 %y) {
+; CHECK-LABEL: fshr_i16:
+; CHECK: .functype fshr_i16 (i32, i32) -> (i32)
+; CHECK-NEXT: .local i32
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: i32.const $push6=, 13
+; CHECK-NEXT: local.set 2, $pop6
+; CHECK-NEXT: local.get $push7=, 0
+; CHECK-NEXT: i32.const $push4=, 3
+; CHECK-NEXT: i32.shl $push3=, $pop7, $pop4
+; CHECK-NEXT: local.get $push8=, 1
+; CHECK-NEXT: i32.const $push5=, 65535
+; CHECK-NEXT: i32.and $push1=, $pop8, $pop5
+; CHECK-NEXT: local.get $push9=, 2
+; CHECK-NEXT: i32.shr_u $push2=, $pop1, $pop9
+; CHECK-NEXT: i32.or $push0=, $pop3, $pop2
+; CHECK-NEXT: return $pop0
+ %a = call i16 @llvm.fshr.i16(i16 %x, i16 %y, i16 13)
+ ret i16 %a
+}
+
+define i16 @fshrv_i16(i16 %x, i16 %y, i16 %z) {
+; CHECK-LABEL: fshrv_i16:
+; CHECK: .functype fshrv_i16 (i32, i32, i32) -> (i32)
+; CHECK-NEXT: .local i32, i32, i32
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: i32.const $push9=, 15
+; CHECK-NEXT: local.set 3, $pop9
+; CHECK-NEXT: local.get $push12=, 2
+; CHECK-NEXT: local.get $push11=, 3
+; CHECK-NEXT: i32.and $push10=, $pop12, $pop11
+; CHECK-NEXT: local.set 4, $pop10
+; CHECK-NEXT: local.get $push15=, 3
+; CHECK-NEXT: local.get $push13=, 2
+; CHECK-NEXT: i32.const $push7=, -1
+; CHECK-NEXT: i32.xor $push6=, $pop13, $pop7
+; CHECK-NEXT: i32.and $push14=, $pop15, $pop6
+; CHECK-NEXT: local.set 5, $pop14
+; CHECK-NEXT: local.get $push16=, 0
+; CHECK-NEXT: i32.const $push5=, 1
+; CHECK-NEXT: i32.shl $push4=, $pop16, $pop5
+; CHECK-NEXT: local.get $push17=, 5
+; CHECK-NEXT: i32.shl $push3=, $pop4, $pop17
+; CHECK-NEXT: local.get $push18=, 1
+; CHECK-NEXT: i32.const $push8=, 65535
+; CHECK-NEXT: i32.and $push1=, $pop18, $pop8
+; CHECK-NEXT: local.get $push19=, 4
+; CHECK-NEXT: i32.shr_u $push2=, $pop1, $pop19
+; CHECK-NEXT: i32.or $push0=, $pop3, $pop2
+; CHECK-NEXT: return $pop0
+ %a = call i16 @llvm.fshr.i16(i16 %x, i16 %y, i16 %z)
+ ret i16 %a
+}
+
+define i32 @fshr_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: fshr_i32:
+; CHECK: .functype fshr_i32 (i32, i32) -> (i32)
+; CHECK-NEXT: .local i32
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: i32.const $push4=, 21
+; CHECK-NEXT: local.set 2, $pop4
+; CHECK-NEXT: local.get $push5=, 0
+; CHECK-NEXT: i32.const $push1=, 11
+; CHECK-NEXT: i32.shl $push2=, $pop5, $pop1
+; CHECK-NEXT: local.get $push7=, 1
+; CHECK-NEXT: local.get $push6=, 2
+; CHECK-NEXT: i32.shr_u $push3=, $pop7, $pop6
+; CHECK-NEXT: i32.or $push0=, $pop2, $pop3
+; CHECK-NEXT: return $pop0
+ %a = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 21)
+ ret i32 %a
+}
+
+define i32 @fshrv_i32(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: fshrv_i32:
+; CHECK: .functype fshrv_i32 (i32, i32, i32) -> (i32)
+; CHECK-NEXT: .local i32
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push7=, 2
+; CHECK-NEXT: i32.const $push1=, -1
+; CHECK-NEXT: i32.xor $push6=, $pop7, $pop1
+; CHECK-NEXT: local.set 3, $pop6
+; CHECK-NEXT: local.get $push8=, 0
+; CHECK-NEXT: i32.const $push2=, 1
+; CHECK-NEXT: i32.shl $push3=, $pop8, $pop2
+; CHECK-NEXT: local.get $push9=, 3
+; CHECK-NEXT: i32.shl $push4=, $pop3, $pop9
+; CHECK-NEXT: local.get $push11=, 1
+; CHECK-NEXT: local.get $push10=, 2
+; CHECK-NEXT: i32.shr_u $push5=, $pop11, $pop10
+; CHECK-NEXT: i32.or $push0=, $pop4, $pop5
+; CHECK-NEXT: return $pop0
+ %a = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %z)
+ ret i32 %a
+}
+
+define i64 @fshr_i64(i64 %x, i64 %y) {
+; CHECK-LABEL: fshr_i64:
+; CHECK: .functype fshr_i64 (i64, i64) -> (i64)
+; CHECK-NEXT: .local i64
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: i64.const $push4=, 37
+; CHECK-NEXT: local.set 2, $pop4
+; CHECK-NEXT: local.get $push5=, 0
+; CHECK-NEXT: i64.const $push1=, 27
+; CHECK-NEXT: i64.shl $push2=, $pop5, $pop1
+; CHECK-NEXT: local.get $push7=, 1
+; CHECK-NEXT: local.get $push6=, 2
+; CHECK-NEXT: i64.shr_u $push3=, $pop7, $pop6
+; CHECK-NEXT: i64.or $push0=, $pop2, $pop3
+; CHECK-NEXT: return $pop0
+ %a = call i64 @llvm.fshr.i64(i64 %x, i64 %y, i64 37)
+ ret i64 %a
+}
+
+define i64 @fshrv_i64(i64 %x, i64 %y, i64 %z) {
+; CHECK-LABEL: fshrv_i64:
+; CHECK: .functype fshrv_i64 (i64, i64, i64) -> (i64)
+; CHECK-NEXT: .local i64
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push7=, 2
+; CHECK-NEXT: i64.const $push1=, -1
+; CHECK-NEXT: i64.xor $push6=, $pop7, $pop1
+; CHECK-NEXT: local.set 3, $pop6
+; CHECK-NEXT: local.get $push8=, 0
+; CHECK-NEXT: i64.const $push2=, 1
+; CHECK-NEXT: i64.shl $push3=, $pop8, $pop2
+; CHECK-NEXT: local.get $push9=, 3
+; CHECK-NEXT: i64.shl $push4=, $pop3, $pop9
+; CHECK-NEXT: local.get $push11=, 1
+; CHECK-NEXT: local.get $push10=, 2
+; CHECK-NEXT: i64.shr_u $push5=, $pop11, $pop10
+; CHECK-NEXT: i64.or $push0=, $pop4, $pop5
+; CHECK-NEXT: return $pop0
+ %a = call i64 @llvm.fshr.i64(i64 %x, i64 %y, i64 %z)
+ ret i64 %a
+}
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshr.mir
new file mode 100644
index 0000000000000..c7cce3218d6c7
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/fshr.mir
@@ -0,0 +1,128 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: fshr_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshr_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 11, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_1]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_]], [[SHR_U_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %2:_(s8) = G_CONSTANT i8 21
+ %3:_(s32) = G_FSHR %0, %1, %2(s8)
+ RETURN %3(s32), implicit-def $arguments
+...
+---
+name: fshrv_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshrv_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32 = ARGUMENT_i32 2, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_2]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_1:%[0-9]+]]:i32 = SHL_I32 [[SHL_I32_]], [[XOR_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_1]], [[ARGUMENT_i32_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I32_:%[0-9]+]]:i32 = disjoint OR_I32 [[SHL_I32_1]], [[SHR_U_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %3:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ %2:_(s8) = G_TRUNC %3(s32)
+ %4:_(s32) = G_FSHR %0, %1, %2(s8)
+ RETURN %4(s32), implicit-def $arguments
+...
+
+
+---
+name: fshr_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshr_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 43, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_]], [[CONST_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_2:%[0-9]+]]:i64 = CONST_I64 21, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_3:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_1:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_2]], [[CONST_I64_3]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[AND_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = disjoint OR_I64 [[SHL_I64_]], [[SHR_U_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %2:_(s8) = G_CONSTANT i8 21
+ %3:_(s64) = G_FSHR %0, %1, %2(s8)
+ RETURN %3(s64), implicit-def $arguments
+...
+---
+name: fshrv_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: fshrv_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64 = ARGUMENT_i64 1, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 2, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 63, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I32_1:%[0-9]+]]:i32 = CONST_I32 -1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[XOR_I32_:%[0-9]+]]:i32 = XOR_I32 [[ARGUMENT_i32_]], [[CONST_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_1:%[0-9]+]]:i32 = AND_I32 [[XOR_I32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 1, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_]], [[CONST_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[AND_I32_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_2:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_1:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_1:%[0-9]+]]:i64 = SHL_I64 [[SHL_I64_]], [[AND_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[I64_EXTEND_U_I32_1:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_3:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_2:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_1]], [[CONST_I64_3]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_1]], [[AND_I64_2]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[OR_I64_:%[0-9]+]]:i64 = disjoint OR_I64 [[SHL_I64_1]], [[SHR_U_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[OR_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:i64(s64) = ARGUMENT_i64 1, implicit $arguments
+ %3:i32(s32) = ARGUMENT_i32 2, implicit $arguments
+ %2:_(s8) = G_TRUNC %3(s32)
+ %4:_(s64) = G_FSHR %0, %1, %2(s8)
+ RETURN %4(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/implicit_def.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/implicit_def.mir
similarity index 100%
rename from llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/implicit_def.mir
rename to llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/implicit_def.mir
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.ll
new file mode 100644
index 0000000000000..4054c2386fd08
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.ll
@@ -0,0 +1,118 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O0 --global-isel -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
+
+target triple = "wasm32-unknown-unknown"
+
+define i8 @lshr_i8(i8 %x) {
+; CHECK-LABEL: lshr_i8:
+; CHECK: .functype lshr_i8 (i32) -> (i32)
+; CHECK-NEXT: .local i32
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: i32.const $push3=, 5
+; CHECK-NEXT: local.set 1, $pop3
+; CHECK-NEXT: local.get $push4=, 0
+; CHECK-NEXT: i32.const $push2=, 255
+; CHECK-NEXT: i32.and $push0=, $pop4, $pop2
+; CHECK-NEXT: local.get $push5=, 1
+; CHECK-NEXT: i32.shr_u $push1=, $pop0, $pop5
+; CHECK-NEXT: return $pop1
+ %a = lshr i8 %x, 5
+ ret i8 %a
+}
+
+define i8 @lshrv_i8(i8 %x, i8 %y) {
+; CHECK-LABEL: lshrv_i8:
+; CHECK: .functype lshrv_i8 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push5=, 0
+; CHECK-NEXT: i32.const $push4=, 255
+; CHECK-NEXT: i32.and $push0=, $pop5, $pop4
+; CHECK-NEXT: local.get $push6=, 1
+; CHECK-NEXT: i32.const $push3=, 255
+; CHECK-NEXT: i32.and $push2=, $pop6, $pop3
+; CHECK-NEXT: i32.shr_u $push1=, $pop0, $pop2
+; CHECK-NEXT: return $pop1
+ %a = lshr i8 %x, %y
+ ret i8 %a
+}
+
+define i16 @lshr_i16(i16 %x) {
+; CHECK-LABEL: lshr_i16:
+; CHECK: .functype lshr_i16 (i32) -> (i32)
+; CHECK-NEXT: .local i32
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: i32.const $push3=, 13
+; CHECK-NEXT: local.set 1, $pop3
+; CHECK-NEXT: local.get $push4=, 0
+; CHECK-NEXT: i32.const $push2=, 65535
+; CHECK-NEXT: i32.and $push0=, $pop4, $pop2
+; CHECK-NEXT: local.get $push5=, 1
+; CHECK-NEXT: i32.shr_u $push1=, $pop0, $pop5
+; CHECK-NEXT: return $pop1
+ %a = lshr i16 %x, 13
+ ret i16 %a
+}
+
+define i16 @lshrv_i16(i16 %x, i16 %y) {
+; CHECK-LABEL: lshrv_i16:
+; CHECK: .functype lshrv_i16 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push5=, 0
+; CHECK-NEXT: i32.const $push4=, 65535
+; CHECK-NEXT: i32.and $push0=, $pop5, $pop4
+; CHECK-NEXT: local.get $push6=, 1
+; CHECK-NEXT: i32.const $push3=, 65535
+; CHECK-NEXT: i32.and $push2=, $pop6, $pop3
+; CHECK-NEXT: i32.shr_u $push1=, $pop0, $pop2
+; CHECK-NEXT: return $pop1
+ %a = lshr i16 %x, %y
+ ret i16 %a
+}
+
+define i32 @lshr_i32(i32 %x) {
+; CHECK-LABEL: lshr_i32:
+; CHECK: .functype lshr_i32 (i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: i32.const $push0=, 21
+; CHECK-NEXT: i32.shr_u $push1=, $pop2, $pop0
+; CHECK-NEXT: return $pop1
+ %a = lshr i32 %x, 21
+ ret i32 %a
+}
+
+define i32 @lshrv_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: lshrv_i32:
+; CHECK: .functype lshrv_i32 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.shr_u $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = lshr i32 %x, %y
+ ret i32 %a
+}
+
+define i64 @lshr_i64(i64 %x) {
+; CHECK-LABEL: lshr_i64:
+; CHECK: .functype lshr_i64 (i64) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: i64.const $push0=, 37
+; CHECK-NEXT: i64.shr_u $push1=, $pop2, $pop0
+; CHECK-NEXT: return $pop1
+ %a = lshr i64 %x, 37
+ ret i64 %a
+}
+
+define i64 @lshrv_i64(i64 %x, i64 %y) {
+; CHECK-LABEL: lshrv_i64:
+; CHECK: .functype lshrv_i64 (i64, i64) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i64.shr_u $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = lshr i64 %x, %y
+ ret i64 %a
+}
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.mir
new file mode 100644
index 0000000000000..071f5748e8590
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/lshr.mir
@@ -0,0 +1,93 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: lshr_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshr_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_U_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s8) = G_CONSTANT i8 21
+ %2:_(s32) = G_LSHR %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: lshrv_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshrv_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I32_:%[0-9]+]]:i32 = SHR_U_I32 [[ARGUMENT_i32_]], [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_U_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %2(s32)
+ %3:_(s32) = G_LSHR %0, %1
+ RETURN %3(s32), implicit-def $arguments
+...
+
+---
+name: lshr_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshr_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_]], [[CONST_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_U_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s8) = G_CONSTANT i8 37
+ %2:_(s64) = G_LSHR %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
+---
+name: lshrv_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: lshrv_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHR_U_I64_:%[0-9]+]]:i64 = SHR_U_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHR_U_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %2(s32)
+ %3:_(s64) = G_LSHR %0, %1
+ RETURN %3(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/mul.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/mul.ll
new file mode 100644
index 0000000000000..606ea9e563017
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/mul.ll
@@ -0,0 +1,52 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O0 --global-isel -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
+
+target triple = "wasm32-unknown-unknown"
+
+define i8 @mul_i8(i8 %x, i8 %y) {
+; CHECK-LABEL: mul_i8:
+; CHECK: .functype mul_i8 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.mul $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = mul i8 %x, %y
+ ret i8 %a
+}
+
+define i16 @mul_i16(i16 %x, i16 %y) {
+; CHECK-LABEL: mul_i16:
+; CHECK: .functype mul_i16 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.mul $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = mul i16 %x, %y
+ ret i16 %a
+}
+
+define i32 @mul_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: mul_i32:
+; CHECK: .functype mul_i32 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.mul $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = mul i32 %x, %y
+ ret i32 %a
+}
+
+define i64 @mul_i64(i64 %x, i64 %y) {
+; CHECK-LABEL: mul_i64:
+; CHECK: .functype mul_i64 (i64, i64) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i64.mul $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = mul i64 %x, %y
+ ret i64 %a
+}
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/or.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/or.ll
new file mode 100644
index 0000000000000..31a1e32ba0898
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/or.ll
@@ -0,0 +1,64 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O0 --global-isel -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
+
+target triple = "wasm32-unknown-unknown"
+
+define i1 @or_i1(i1 %x, i1 %y) {
+; CHECK-LABEL: or_i1:
+; CHECK: .functype or_i1 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.or $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = or i1 %x, %y
+ ret i1 %a
+}
+
+define i8 @or_i8(i8 %x, i8 %y) {
+; CHECK-LABEL: or_i8:
+; CHECK: .functype or_i8 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.or $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = or i8 %x, %y
+ ret i8 %a
+}
+
+define i16 @or_i16(i16 %x, i16 %y) {
+; CHECK-LABEL: or_i16:
+; CHECK: .functype or_i16 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.or $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = or i16 %x, %y
+ ret i16 %a
+}
+
+define i32 @or_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: or_i32:
+; CHECK: .functype or_i32 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.or $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = or i32 %x, %y
+ ret i32 %a
+}
+
+define i64 @or_i64(i64 %x, i64 %y) {
+; CHECK-LABEL: or_i64:
+; CHECK: .functype or_i64 (i64, i64) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i64.or $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = or i64 %x, %y
+ ret i64 %a
+}
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/rotl.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotl.mir
similarity index 100%
rename from llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/rotl.mir
rename to llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotl.mir
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/rotr.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotr.mir
similarity index 100%
rename from llvm/test/CodeGen/WebAssembly/GlobalISel/gmir/rotr.mir
rename to llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/rotr.mir
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/sdiv.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/sdiv.ll
new file mode 100644
index 0000000000000..b70d8a2a5a445
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/sdiv.ll
@@ -0,0 +1,56 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O0 --global-isel -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
+
+target triple = "wasm32-unknown-unknown"
+
+define i8 @sdiv_i8(i8 %x, i8 %y) {
+; CHECK-LABEL: sdiv_i8:
+; CHECK: .functype sdiv_i8 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push3=, 0
+; CHECK-NEXT: i32.extend8_s $push0=, $pop3
+; CHECK-NEXT: local.get $push4=, 1
+; CHECK-NEXT: i32.extend8_s $push1=, $pop4
+; CHECK-NEXT: i32.div_s $push2=, $pop0, $pop1
+; CHECK-NEXT: return $pop2
+ %a = sdiv i8 %x, %y
+ ret i8 %a
+}
+
+define i16 @sdiv_i16(i16 %x, i16 %y) {
+; CHECK-LABEL: sdiv_i16:
+; CHECK: .functype sdiv_i16 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push3=, 0
+; CHECK-NEXT: i32.extend16_s $push0=, $pop3
+; CHECK-NEXT: local.get $push4=, 1
+; CHECK-NEXT: i32.extend16_s $push1=, $pop4
+; CHECK-NEXT: i32.div_s $push2=, $pop0, $pop1
+; CHECK-NEXT: return $pop2
+ %a = sdiv i16 %x, %y
+ ret i16 %a
+}
+
+define i32 @sdiv_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: sdiv_i32:
+; CHECK: .functype sdiv_i32 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.div_s $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = sdiv i32 %x, %y
+ ret i32 %a
+}
+
+define i64 @sdiv_i64(i64 %x, i64 %y) {
+; CHECK-LABEL: sdiv_i64:
+; CHECK: .functype sdiv_i64 (i64, i64) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i64.div_s $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = sdiv i64 %x, %y
+ ret i64 %a
+}
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/sext.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/sext.ll
new file mode 100644
index 0000000000000..00c51b765b5da
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/sext.ll
@@ -0,0 +1,154 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O0 --global-isel -mattr=-sign-ext -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s -check-prefixes=CHECK,NO-SIGNEXT
+; RUN: llc < %s -O0 --global-isel -mattr=+sign-ext -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s -check-prefixes=CHECK,SIGNEXT
+
+target triple = "wasm32-unknown-unknown"
+
+define i32 @sext_i1_i32(i1 %x) {
+; CHECK-LABEL: sext_i1_i32:
+; CHECK: .functype sext_i1_i32 (i32) -> (i32)
+; CHECK-NEXT: .local i32
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: i32.const $push2=, 31
+; CHECK-NEXT: local.set 1, $pop2
+; CHECK-NEXT: local.get $push4=, 0
+; CHECK-NEXT: local.get $push3=, 1
+; CHECK-NEXT: i32.shl $push1=, $pop4, $pop3
+; CHECK-NEXT: local.get $push5=, 1
+; CHECK-NEXT: i32.shr_s $push0=, $pop1, $pop5
+; CHECK-NEXT: return $pop0
+ %a = sext i1 %x to i32
+ ret i32 %a
+}
+define i64 @sext_i1_i64(i1 %x) {
+; CHECK-LABEL: sext_i1_i64:
+; CHECK: .functype sext_i1_i64 (i32) -> (i64)
+; CHECK-NEXT: .local i64, i64
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push3=, 0
+; CHECK-NEXT: i64.extend_i32_u $push2=, $pop3
+; CHECK-NEXT: local.set 1, $pop2
+; CHECK-NEXT: i64.const $push4=, 63
+; CHECK-NEXT: local.set 2, $pop4
+; CHECK-NEXT: local.get $push6=, 1
+; CHECK-NEXT: local.get $push5=, 2
+; CHECK-NEXT: i64.shl $push1=, $pop6, $pop5
+; CHECK-NEXT: local.get $push7=, 2
+; CHECK-NEXT: i64.shr_s $push0=, $pop1, $pop7
+; CHECK-NEXT: return $pop0
+ %a = sext i1 %x to i64
+ ret i64 %a
+}
+
+define i32 @sext_i8_i32(i8 %x) {
+; NO-SIGNEXT-LABEL: sext_i8_i32:
+; NO-SIGNEXT: .functype sext_i8_i32 (i32) -> (i32)
+; NO-SIGNEXT-NEXT: .local i32
+; NO-SIGNEXT-NEXT: # %bb.0:
+; NO-SIGNEXT-NEXT: i32.const $push2=, 24
+; NO-SIGNEXT-NEXT: local.set 1, $pop2
+; NO-SIGNEXT-NEXT: local.get $push4=, 0
+; NO-SIGNEXT-NEXT: local.get $push3=, 1
+; NO-SIGNEXT-NEXT: i32.shl $push1=, $pop4, $pop3
+; NO-SIGNEXT-NEXT: local.get $push5=, 1
+; NO-SIGNEXT-NEXT: i32.shr_s $push0=, $pop1, $pop5
+; NO-SIGNEXT-NEXT: return $pop0
+;
+; SIGNEXT-LABEL: sext_i8_i32:
+; SIGNEXT: .functype sext_i8_i32 (i32) -> (i32)
+; SIGNEXT-NEXT: # %bb.0:
+; SIGNEXT-NEXT: local.get $push1=, 0
+; SIGNEXT-NEXT: i32.extend8_s $push0=, $pop1
+; SIGNEXT-NEXT: return $pop0
+ %a = sext i8 %x to i32
+ ret i32 %a
+}
+define i64 @sext_i8_i64(i8 %x) {
+; NO-SIGNEXT-LABEL: sext_i8_i64:
+; NO-SIGNEXT: .functype sext_i8_i64 (i32) -> (i64)
+; NO-SIGNEXT-NEXT: .local i64, i64
+; NO-SIGNEXT-NEXT: # %bb.0:
+; NO-SIGNEXT-NEXT: local.get $push3=, 0
+; NO-SIGNEXT-NEXT: i64.extend_i32_u $push2=, $pop3
+; NO-SIGNEXT-NEXT: local.set 1, $pop2
+; NO-SIGNEXT-NEXT: i64.const $push4=, 56
+; NO-SIGNEXT-NEXT: local.set 2, $pop4
+; NO-SIGNEXT-NEXT: local.get $push6=, 1
+; NO-SIGNEXT-NEXT: local.get $push5=, 2
+; NO-SIGNEXT-NEXT: i64.shl $push1=, $pop6, $pop5
+; NO-SIGNEXT-NEXT: local.get $push7=, 2
+; NO-SIGNEXT-NEXT: i64.shr_s $push0=, $pop1, $pop7
+; NO-SIGNEXT-NEXT: return $pop0
+;
+; SIGNEXT-LABEL: sext_i8_i64:
+; SIGNEXT: .functype sext_i8_i64 (i32) -> (i64)
+; SIGNEXT-NEXT: # %bb.0:
+; SIGNEXT-NEXT: local.get $push2=, 0
+; SIGNEXT-NEXT: i64.extend_i32_u $push1=, $pop2
+; SIGNEXT-NEXT: i64.extend8_s $push0=, $pop1
+; SIGNEXT-NEXT: return $pop0
+ %a = sext i8 %x to i64
+ ret i64 %a
+}
+
+define i32 @sext_i16_i32(i16 %x) {
+; NO-SIGNEXT-LABEL: sext_i16_i32:
+; NO-SIGNEXT: .functype sext_i16_i32 (i32) -> (i32)
+; NO-SIGNEXT-NEXT: .local i32
+; NO-SIGNEXT-NEXT: # %bb.0:
+; NO-SIGNEXT-NEXT: i32.const $push2=, 16
+; NO-SIGNEXT-NEXT: local.set 1, $pop2
+; NO-SIGNEXT-NEXT: local.get $push4=, 0
+; NO-SIGNEXT-NEXT: local.get $push3=, 1
+; NO-SIGNEXT-NEXT: i32.shl $push1=, $pop4, $pop3
+; NO-SIGNEXT-NEXT: local.get $push5=, 1
+; NO-SIGNEXT-NEXT: i32.shr_s $push0=, $pop1, $pop5
+; NO-SIGNEXT-NEXT: return $pop0
+;
+; SIGNEXT-LABEL: sext_i16_i32:
+; SIGNEXT: .functype sext_i16_i32 (i32) -> (i32)
+; SIGNEXT-NEXT: # %bb.0:
+; SIGNEXT-NEXT: local.get $push1=, 0
+; SIGNEXT-NEXT: i32.extend16_s $push0=, $pop1
+; SIGNEXT-NEXT: return $pop0
+ %a = sext i16 %x to i32
+ ret i32 %a
+}
+define i64 @sext_i16_i64(i16 %x) {
+; NO-SIGNEXT-LABEL: sext_i16_i64:
+; NO-SIGNEXT: .functype sext_i16_i64 (i32) -> (i64)
+; NO-SIGNEXT-NEXT: .local i64, i64
+; NO-SIGNEXT-NEXT: # %bb.0:
+; NO-SIGNEXT-NEXT: local.get $push3=, 0
+; NO-SIGNEXT-NEXT: i64.extend_i32_u $push2=, $pop3
+; NO-SIGNEXT-NEXT: local.set 1, $pop2
+; NO-SIGNEXT-NEXT: i64.const $push4=, 48
+; NO-SIGNEXT-NEXT: local.set 2, $pop4
+; NO-SIGNEXT-NEXT: local.get $push6=, 1
+; NO-SIGNEXT-NEXT: local.get $push5=, 2
+; NO-SIGNEXT-NEXT: i64.shl $push1=, $pop6, $pop5
+; NO-SIGNEXT-NEXT: local.get $push7=, 2
+; NO-SIGNEXT-NEXT: i64.shr_s $push0=, $pop1, $pop7
+; NO-SIGNEXT-NEXT: return $pop0
+;
+; SIGNEXT-LABEL: sext_i16_i64:
+; SIGNEXT: .functype sext_i16_i64 (i32) -> (i64)
+; SIGNEXT-NEXT: # %bb.0:
+; SIGNEXT-NEXT: local.get $push2=, 0
+; SIGNEXT-NEXT: i64.extend_i32_u $push1=, $pop2
+; SIGNEXT-NEXT: i64.extend16_s $push0=, $pop1
+; SIGNEXT-NEXT: return $pop0
+ %a = sext i16 %x to i64
+ ret i64 %a
+}
+
+define i64 @sext_i32_i64(i32 %x) {
+; CHECK-LABEL: sext_i32_i64:
+; CHECK: .functype sext_i32_i64 (i32) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push1=, 0
+; CHECK-NEXT: i64.extend_i32_s $push0=, $pop1
+; CHECK-NEXT: return $pop0
+ %a = sext i32 %x to i64
+ ret i64 %a
+}
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.ll
new file mode 100644
index 0000000000000..5ceb1016e169f
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.ll
@@ -0,0 +1,104 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O0 --global-isel -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
+
+target triple = "wasm32-unknown-unknown"
+
+define i8 @shl_i8(i8 %x) {
+; CHECK-LABEL: shl_i8:
+; CHECK: .functype shl_i8 (i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: i32.const $push1=, 5
+; CHECK-NEXT: i32.shl $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = shl i8 %x, 5
+ ret i8 %a
+}
+
+define i8 @shlv_i8(i8 %x, i8 %y) {
+; CHECK-LABEL: shlv_i8:
+; CHECK: .functype shlv_i8 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push4=, 0
+; CHECK-NEXT: local.get $push3=, 1
+; CHECK-NEXT: i32.const $push2=, 255
+; CHECK-NEXT: i32.and $push1=, $pop3, $pop2
+; CHECK-NEXT: i32.shl $push0=, $pop4, $pop1
+; CHECK-NEXT: return $pop0
+ %a = shl i8 %x, %y
+ ret i8 %a
+}
+
+define i16 @shl_i16(i16 %x) {
+; CHECK-LABEL: shl_i16:
+; CHECK: .functype shl_i16 (i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: i32.const $push1=, 13
+; CHECK-NEXT: i32.shl $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = shl i16 %x, 13
+ ret i16 %a
+}
+
+define i16 @shlv_i16(i16 %x, i16 %y) {
+; CHECK-LABEL: shlv_i16:
+; CHECK: .functype shlv_i16 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push4=, 0
+; CHECK-NEXT: local.get $push3=, 1
+; CHECK-NEXT: i32.const $push2=, 65535
+; CHECK-NEXT: i32.and $push1=, $pop3, $pop2
+; CHECK-NEXT: i32.shl $push0=, $pop4, $pop1
+; CHECK-NEXT: return $pop0
+ %a = shl i16 %x, %y
+ ret i16 %a
+}
+
+define i32 @shl_i32(i32 %x) {
+; CHECK-LABEL: shl_i32:
+; CHECK: .functype shl_i32 (i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: i32.const $push0=, 21
+; CHECK-NEXT: i32.shl $push1=, $pop2, $pop0
+; CHECK-NEXT: return $pop1
+ %a = shl i32 %x, 21
+ ret i32 %a
+}
+
+define i32 @shlv_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: shlv_i32:
+; CHECK: .functype shlv_i32 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.shl $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = shl i32 %x, %y
+ ret i32 %a
+}
+
+define i64 @shl_i64(i64 %x) {
+; CHECK-LABEL: shl_i64:
+; CHECK: .functype shl_i64 (i64) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: i64.const $push0=, 37
+; CHECK-NEXT: i64.shl $push1=, $pop2, $pop0
+; CHECK-NEXT: return $pop1
+ %a = shl i64 %x, 37
+ ret i64 %a
+}
+
+define i64 @shlv_i64(i64 %x, i64 %y) {
+; CHECK-LABEL: shlv_i64:
+; CHECK: .functype shlv_i64 (i64, i64) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i64.shl $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = shl i64 %x, %y
+ ret i64 %a
+}
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.mir b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.mir
new file mode 100644
index 0000000000000..fa1829e3927cc
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/shl.mir
@@ -0,0 +1,93 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=wasm32-unknown-unknown -run-pass=legalizer,regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: shl_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shl_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 21, implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHL_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %1:_(s8) = G_CONSTANT i8 21
+ %2:_(s32) = G_SHL %0, %1
+ RETURN %2(s32), implicit-def $arguments
+...
+---
+name: shlv_i32_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shlv_i32_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I32_:%[0-9]+]]:i32 = CONST_I32 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I32_:%[0-9]+]]:i32 = AND_I32 [[ARGUMENT_i32_1]], [[CONST_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I32_:%[0-9]+]]:i32 = SHL_I32 [[ARGUMENT_i32_]], [[AND_I32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHL_I32_]], implicit-def $arguments
+ %0:i32(s32) = ARGUMENT_i32 0, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %2(s32)
+ %3:_(s32) = G_SHL %0, %1
+ RETURN %3(s32), implicit-def $arguments
+...
+
+---
+name: shl_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shl_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 37, implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_1:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[CONST_I64_]], [[CONST_I64_1]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHL_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %1:_(s8) = G_CONSTANT i8 37
+ %2:_(s64) = G_SHL %0, %1
+ RETURN %2(s64), implicit-def $arguments
+...
+---
+name: shlv_i64_i8
+alignment: 1
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $arguments
+
+ ; CHECK-LABEL: name: shlv_i64_i8
+ ; CHECK: liveins: $arguments
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64 = ARGUMENT_i64 0, implicit $arguments
+ ; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32 = ARGUMENT_i32 1, implicit $arguments
+ ; CHECK-NEXT: [[I64_EXTEND_U_I32_:%[0-9]+]]:i64 = I64_EXTEND_U_I32 [[ARGUMENT_i32_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[CONST_I64_:%[0-9]+]]:i64 = CONST_I64 255, implicit-def dead $arguments
+ ; CHECK-NEXT: [[AND_I64_:%[0-9]+]]:i64 = AND_I64 [[I64_EXTEND_U_I32_]], [[CONST_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: [[SHL_I64_:%[0-9]+]]:i64 = SHL_I64 [[ARGUMENT_i64_]], [[AND_I64_]], implicit-def dead $arguments
+ ; CHECK-NEXT: RETURN [[SHL_I64_]], implicit-def $arguments
+ %0:i64(s64) = ARGUMENT_i64 0, implicit $arguments
+ %2:i32(s32) = ARGUMENT_i32 1, implicit $arguments
+ %1:_(s8) = G_TRUNC %2(s32)
+ %3:_(s64) = G_SHL %0, %1
+ RETURN %3(s64), implicit-def $arguments
+...
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/srem.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/srem.ll
new file mode 100644
index 0000000000000..f688924e2b9c9
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/srem.ll
@@ -0,0 +1,56 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O0 --global-isel -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
+
+target triple = "wasm32-unknown-unknown"
+
+define i8 @srem_i8(i8 %x, i8 %y) {
+; CHECK-LABEL: srem_i8:
+; CHECK: .functype srem_i8 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push3=, 0
+; CHECK-NEXT: i32.extend8_s $push0=, $pop3
+; CHECK-NEXT: local.get $push4=, 1
+; CHECK-NEXT: i32.extend8_s $push1=, $pop4
+; CHECK-NEXT: i32.rem_s $push2=, $pop0, $pop1
+; CHECK-NEXT: return $pop2
+ %a = srem i8 %x, %y
+ ret i8 %a
+}
+
+define i16 @srem_i16(i16 %x, i16 %y) {
+; CHECK-LABEL: srem_i16:
+; CHECK: .functype srem_i16 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push3=, 0
+; CHECK-NEXT: i32.extend16_s $push0=, $pop3
+; CHECK-NEXT: local.get $push4=, 1
+; CHECK-NEXT: i32.extend16_s $push1=, $pop4
+; CHECK-NEXT: i32.rem_s $push2=, $pop0, $pop1
+; CHECK-NEXT: return $pop2
+ %a = srem i16 %x, %y
+ ret i16 %a
+}
+
+define i32 @srem_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: srem_i32:
+; CHECK: .functype srem_i32 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.rem_s $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = srem i32 %x, %y
+ ret i32 %a
+}
+
+define i64 @srem_i64(i64 %x, i64 %y) {
+; CHECK-LABEL: srem_i64:
+; CHECK: .functype srem_i64 (i64, i64) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i64.rem_s $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = srem i64 %x, %y
+ ret i64 %a
+}
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/sub.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/sub.ll
new file mode 100644
index 0000000000000..3887d06e0c191
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/sub.ll
@@ -0,0 +1,52 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O0 --global-isel -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
+
+target triple = "wasm32-unknown-unknown"
+
+define i8 @sub_i8(i8 %x, i8 %y) {
+; CHECK-LABEL: sub_i8:
+; CHECK: .functype sub_i8 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.sub $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = sub i8 %x, %y
+ ret i8 %a
+}
+
+define i16 @sub_i16(i16 %x, i16 %y) {
+; CHECK-LABEL: sub_i16:
+; CHECK: .functype sub_i16 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.sub $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = sub i16 %x, %y
+ ret i16 %a
+}
+
+define i32 @sub_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: sub_i32:
+; CHECK: .functype sub_i32 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.sub $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = sub i32 %x, %y
+ ret i32 %a
+}
+
+define i64 @sub_i64(i64 %x, i64 %y) {
+; CHECK-LABEL: sub_i64:
+; CHECK: .functype sub_i64 (i64, i64) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i64.sub $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = sub i64 %x, %y
+ ret i64 %a
+}
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/trunc.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/trunc.ll
new file mode 100644
index 0000000000000..2634b62827998
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/trunc.ll
@@ -0,0 +1,75 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O0 --global-isel -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
+
+target triple = "wasm32-unknown-unknown"
+
+define i1 @trunc_i32_i1(i32 %x) {
+; CHECK-LABEL: trunc_i32_i1:
+; CHECK: .functype trunc_i32_i1 (i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push0=, 0
+; CHECK-NEXT: return $pop0
+ %a = trunc i32 %x to i1
+ ret i1 %a
+}
+define i1 @trunc_i64_i1(i64 %x) {
+; CHECK-LABEL: trunc_i64_i1:
+; CHECK: .functype trunc_i64_i1 (i64) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push1=, 0
+; CHECK-NEXT: i32.wrap_i64 $push0=, $pop1
+; CHECK-NEXT: return $pop0
+ %a = trunc i64 %x to i1
+ ret i1 %a
+}
+
+define i8 @trunc_i32_i8(i32 %x) {
+; CHECK-LABEL: trunc_i32_i8:
+; CHECK: .functype trunc_i32_i8 (i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push0=, 0
+; CHECK-NEXT: return $pop0
+ %a = trunc i32 %x to i8
+ ret i8 %a
+}
+define i8 @trunc_i64_i8(i64 %x) {
+; CHECK-LABEL: trunc_i64_i8:
+; CHECK: .functype trunc_i64_i8 (i64) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push1=, 0
+; CHECK-NEXT: i32.wrap_i64 $push0=, $pop1
+; CHECK-NEXT: return $pop0
+ %a = trunc i64 %x to i8
+ ret i8 %a
+}
+
+define i16 @trunc_i32_i16(i32 %x) {
+; CHECK-LABEL: trunc_i32_i16:
+; CHECK: .functype trunc_i32_i16 (i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push0=, 0
+; CHECK-NEXT: return $pop0
+ %a = trunc i32 %x to i16
+ ret i16 %a
+}
+define i16 @trunc_i64_i16(i64 %x) {
+; CHECK-LABEL: trunc_i64_i16:
+; CHECK: .functype trunc_i64_i16 (i64) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push1=, 0
+; CHECK-NEXT: i32.wrap_i64 $push0=, $pop1
+; CHECK-NEXT: return $pop0
+ %a = trunc i64 %x to i16
+ ret i16 %a
+}
+
+define i32 @trunc_i64_i32(i64 %x) {
+; CHECK-LABEL: trunc_i64_i32:
+; CHECK: .functype trunc_i64_i32 (i64) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push1=, 0
+; CHECK-NEXT: i32.wrap_i64 $push0=, $pop1
+; CHECK-NEXT: return $pop0
+ %a = trunc i64 %x to i32
+ ret i32 %a
+}
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/udiv.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/udiv.ll
new file mode 100644
index 0000000000000..09d5ecd77ea20
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/udiv.ll
@@ -0,0 +1,60 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O0 --global-isel -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
+
+target triple = "wasm32-unknown-unknown"
+
+define i8 @udiv_i8(i8 %x, i8 %y) {
+; CHECK-LABEL: udiv_i8:
+; CHECK: .functype udiv_i8 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push5=, 0
+; CHECK-NEXT: i32.const $push4=, 255
+; CHECK-NEXT: i32.and $push0=, $pop5, $pop4
+; CHECK-NEXT: local.get $push6=, 1
+; CHECK-NEXT: i32.const $push3=, 255
+; CHECK-NEXT: i32.and $push1=, $pop6, $pop3
+; CHECK-NEXT: i32.div_u $push2=, $pop0, $pop1
+; CHECK-NEXT: return $pop2
+ %a = udiv i8 %x, %y
+ ret i8 %a
+}
+
+define i16 @udiv_i16(i16 %x, i16 %y) {
+; CHECK-LABEL: udiv_i16:
+; CHECK: .functype udiv_i16 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push5=, 0
+; CHECK-NEXT: i32.const $push4=, 65535
+; CHECK-NEXT: i32.and $push0=, $pop5, $pop4
+; CHECK-NEXT: local.get $push6=, 1
+; CHECK-NEXT: i32.const $push3=, 65535
+; CHECK-NEXT: i32.and $push1=, $pop6, $pop3
+; CHECK-NEXT: i32.div_u $push2=, $pop0, $pop1
+; CHECK-NEXT: return $pop2
+ %a = udiv i16 %x, %y
+ ret i16 %a
+}
+
+define i32 @udiv_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: udiv_i32:
+; CHECK: .functype udiv_i32 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.div_u $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = udiv i32 %x, %y
+ ret i32 %a
+}
+
+define i64 @udiv_i64(i64 %x, i64 %y) {
+; CHECK-LABEL: udiv_i64:
+; CHECK: .functype udiv_i64 (i64, i64) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i64.div_u $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = udiv i64 %x, %y
+ ret i64 %a
+}
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/urem.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/urem.ll
new file mode 100644
index 0000000000000..a8c6dd64231ef
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/urem.ll
@@ -0,0 +1,60 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O0 --global-isel -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
+
+target triple = "wasm32-unknown-unknown"
+
+define i8 @urem_i8(i8 %x, i8 %y) {
+; CHECK-LABEL: urem_i8:
+; CHECK: .functype urem_i8 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push5=, 0
+; CHECK-NEXT: i32.const $push4=, 255
+; CHECK-NEXT: i32.and $push0=, $pop5, $pop4
+; CHECK-NEXT: local.get $push6=, 1
+; CHECK-NEXT: i32.const $push3=, 255
+; CHECK-NEXT: i32.and $push1=, $pop6, $pop3
+; CHECK-NEXT: i32.rem_u $push2=, $pop0, $pop1
+; CHECK-NEXT: return $pop2
+ %a = urem i8 %x, %y
+ ret i8 %a
+}
+
+define i16 @urem_i16(i16 %x, i16 %y) {
+; CHECK-LABEL: urem_i16:
+; CHECK: .functype urem_i16 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push5=, 0
+; CHECK-NEXT: i32.const $push4=, 65535
+; CHECK-NEXT: i32.and $push0=, $pop5, $pop4
+; CHECK-NEXT: local.get $push6=, 1
+; CHECK-NEXT: i32.const $push3=, 65535
+; CHECK-NEXT: i32.and $push1=, $pop6, $pop3
+; CHECK-NEXT: i32.rem_u $push2=, $pop0, $pop1
+; CHECK-NEXT: return $pop2
+ %a = urem i16 %x, %y
+ ret i16 %a
+}
+
+define i32 @urem_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: urem_i32:
+; CHECK: .functype urem_i32 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.rem_u $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = urem i32 %x, %y
+ ret i32 %a
+}
+
+define i64 @urem_i64(i64 %x, i64 %y) {
+; CHECK-LABEL: urem_i64:
+; CHECK: .functype urem_i64 (i64, i64) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i64.rem_u $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = urem i64 %x, %y
+ ret i64 %a
+}
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/xor.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/xor.ll
new file mode 100644
index 0000000000000..966ba970535bb
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/xor.ll
@@ -0,0 +1,64 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O0 --global-isel -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
+
+target triple = "wasm32-unknown-unknown"
+
+define i1 @xor_i1(i1 %x, i1 %y) {
+; CHECK-LABEL: xor_i1:
+; CHECK: .functype xor_i1 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.xor $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = xor i1 %x, %y
+ ret i1 %a
+}
+
+define i8 @xor_i8(i8 %x, i8 %y) {
+; CHECK-LABEL: xor_i8:
+; CHECK: .functype xor_i8 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.xor $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = xor i8 %x, %y
+ ret i8 %a
+}
+
+define i16 @xor_i16(i16 %x, i16 %y) {
+; CHECK-LABEL: xor_i16:
+; CHECK: .functype xor_i16 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.xor $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = xor i16 %x, %y
+ ret i16 %a
+}
+
+define i32 @xor_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: xor_i32:
+; CHECK: .functype xor_i32 (i32, i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i32.xor $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = xor i32 %x, %y
+ ret i32 %a
+}
+
+define i64 @xor_i64(i64 %x, i64 %y) {
+; CHECK-LABEL: xor_i64:
+; CHECK: .functype xor_i64 (i64, i64) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: i64.xor $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = xor i64 %x, %y
+ ret i64 %a
+}
diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/zext.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/zext.ll
new file mode 100644
index 0000000000000..55a587e2f6312
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/instructions/zext.ll
@@ -0,0 +1,88 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -O0 --global-isel -mattr=-sign-ext -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s -check-prefixes=CHECK
+; RUN: llc < %s -O0 --global-isel -mattr=+sign-ext -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s -check-prefixes=CHECK
+
+target triple = "wasm32-unknown-unknown"
+
+define i32 @zext_i1_i32(i1 %x) {
+; CHECK-LABEL: zext_i1_i32:
+; CHECK: .functype zext_i1_i32 (i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: i32.const $push1=, 1
+; CHECK-NEXT: i32.and $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = zext i1 %x to i32
+ ret i32 %a
+}
+define i64 @zext_i1_i64(i1 %x) {
+; CHECK-LABEL: zext_i1_i64:
+; CHECK: .functype zext_i1_i64 (i32) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push3=, 0
+; CHECK-NEXT: i64.extend_i32_u $push1=, $pop3
+; CHECK-NEXT: i64.const $push2=, 1
+; CHECK-NEXT: i64.and $push0=, $pop1, $pop2
+; CHECK-NEXT: return $pop0
+ %a = zext i1 %x to i64
+ ret i64 %a
+}
+
+define i32 @zext_i8_i32(i8 %x) {
+; CHECK-LABEL: zext_i8_i32:
+; CHECK: .functype zext_i8_i32 (i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: i32.const $push1=, 255
+; CHECK-NEXT: i32.and $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = zext i8 %x to i32
+ ret i32 %a
+}
+define i64 @zext_i8_i64(i8 %x) {
+; CHECK-LABEL: zext_i8_i64:
+; CHECK: .functype zext_i8_i64 (i32) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push3=, 0
+; CHECK-NEXT: i64.extend_i32_u $push1=, $pop3
+; CHECK-NEXT: i64.const $push2=, 255
+; CHECK-NEXT: i64.and $push0=, $pop1, $pop2
+; CHECK-NEXT: return $pop0
+ %a = zext i8 %x to i64
+ ret i64 %a
+}
+
+define i32 @zext_i16_i32(i16 %x) {
+; CHECK-LABEL: zext_i16_i32:
+; CHECK: .functype zext_i16_i32 (i32) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: i32.const $push1=, 65535
+; CHECK-NEXT: i32.and $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
+ %a = zext i16 %x to i32
+ ret i32 %a
+}
+define i64 @zext_i16_i64(i16 %x) {
+; CHECK-LABEL: zext_i16_i64:
+; CHECK: .functype zext_i16_i64 (i32) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push3=, 0
+; CHECK-NEXT: i64.extend_i32_u $push1=, $pop3
+; CHECK-NEXT: i64.const $push2=, 65535
+; CHECK-NEXT: i64.and $push0=, $pop1, $pop2
+; CHECK-NEXT: return $pop0
+ %a = zext i16 %x to i64
+ ret i64 %a
+}
+
+define i64 @zext_i32_i64(i32 %x) {
+; CHECK-LABEL: zext_i32_i64:
+; CHECK: .functype zext_i32_i64 (i32) -> (i64)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: local.get $push1=, 0
+; CHECK-NEXT: i64.extend_i32_u $push0=, $pop1
+; CHECK-NEXT: return $pop0
+ %a = zext i32 %x to i64
+ ret i64 %a
+}
>From 47943083edc692fc48038813b27699258a150a3b Mon Sep 17 00:00:00 2001
From: Demetrius Kanios <demetrius at kanios.net>
Date: Wed, 8 Apr 2026 14:16:07 -0700
Subject: [PATCH 7/7] Formatting touch-ups
---
.../WebAssembly/GISel/WebAssemblyInstructionSelector.cpp | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp
index 19b4cffa334bc..5c27dd9b5b201 100644
--- a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp
+++ b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp
@@ -23,7 +23,6 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/IR/IntrinsicsWebAssembly.h"
-#include "llvm/Support/ErrorHandling.h"
#define DEBUG_TYPE "wasm-isel"
@@ -89,9 +88,8 @@ bool WebAssemblyInstructionSelector::select(MachineInstr &I) {
MachineFunction &MF = *MBB.getParent();
MachineRegisterInfo &MRI = MF.getRegInfo();
- if (!I.isPreISelOpcode()) {
+ if (!I.isPreISelOpcode())
return true;
- }
if (selectImpl(I, *CoverageInfo))
return true;
@@ -105,9 +103,8 @@ bool WebAssemblyInstructionSelector::select(MachineInstr &I) {
const TargetRegisterClass *DefRC =
TRI.getConstrainedRegClassForOperand(I.getOperand(0), MRI);
- if (!DefRC) {
+ if (!DefRC)
return false;
- }
I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF));
return RBI.constrainGenericRegister(DefReg, *DefRC, MRI) != nullptr;
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