[llvm] [LV] Add VPlan printing tests checking SCEV expansion (NFC). (PR #191053)

[Florian Hahn via llvm-commits]

https://github.com/fhahn created https://github.com/llvm/llvm-project/pull/191053

Add additional test cases checking VPlan output of SCEV expansions.

>From a9af3104582c9a749ec51454ae6637b3288751bd Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo at fhahn.com>
Date: Tue, 7 Apr 2026 09:40:44 +0100
Subject: [PATCH] [LV] Add VPlan printing tests checking SCEV expansion (NFC).

Add additional test cases checking VPlan output of SCEV expansions.
---
 .../LoopVectorize/VPlan/expand-scev.ll        | 121 ++++++++++++++++++
 1 file changed, 121 insertions(+)
 create mode 100644 llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll

diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll b/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
new file mode 100644
index 0000000000000..823ecbe18041f
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
@@ -0,0 +1,121 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --filter-out-after "Successor" --version 6
+; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 \
+; RUN:   -force-target-supports-scalable-vectors \
+; RUN:   -disable-output -vplan-print-after="printFinalVPlan$" %s 2>&1 | FileCheck %s
+
+define void @scev_add_expanded(ptr %dst, i64 %n) {
+; CHECK-LABEL: VPlan for loop in 'scev_add_expanded'
+; CHECK:  VPlan 'Final VPlan for VF={4},UF={1}' {
+; CHECK-NEXT:  Live-in ir<%0> = original trip-count
+; CHECK-EMPTY:
+; CHECK-NEXT:  ir-bb<loop.preheader>:
+; CHECK-NEXT:    IR   %0 = add i64 %n, 2
+; CHECK-NEXT:    EMIT vp<%min.iters.check> = icmp ult ir<%0>, ir<4>
+; CHECK-NEXT:    EMIT branch-on-cond vp<%min.iters.check>
+; CHECK-NEXT:  Successor(s): ir-bb<scalar.ph>, vector.ph
+;
+entry:
+  %cmp = icmp ne i64 %n, 0
+  br i1 %cmp, label %loop, label %exit
+
+loop:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+  %gep = getelementptr i8, ptr %dst, i64 %iv
+  store i8 0, ptr %gep
+  %iv.next = add nuw i64 %iv, 1
+  %cmp.loop = icmp ule i64 %iv, %n
+  br i1 %cmp.loop, label %loop, label %exit
+
+exit:
+  ret void
+}
+
+define void @scev_add_lshr_expanded(ptr %dst, i64 %n) {
+; CHECK-LABEL: VPlan for loop in 'scev_add_lshr_expanded'
+; CHECK:  VPlan 'Final VPlan for VF={4},UF={1}' {
+; CHECK-NEXT:  Live-in ir<%2> = original trip-count
+; CHECK-EMPTY:
+; CHECK-NEXT:  ir-bb<loop.preheader>:
+; CHECK-NEXT:    IR   %0 = add i64 %n, -1
+; CHECK-NEXT:    IR   %1 = lshr i64 %0, 1
+; CHECK-NEXT:    IR   %2 = add nuw i64 %1, 1
+; CHECK-NEXT:    EMIT vp<%min.iters.check> = icmp ult ir<%2>, ir<4>
+; CHECK-NEXT:    EMIT branch-on-cond vp<%min.iters.check>
+; CHECK-NEXT:  Successor(s): ir-bb<scalar.ph>, vector.ph
+;
+entry:
+  %cmp = icmp ugt i64 %n, 2
+  br i1 %cmp, label %loop, label %exit
+
+loop:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+  %gep = getelementptr i8, ptr %dst, i64 %iv
+  store i8 0, ptr %gep
+  %iv.next = add nuw i64 %iv, 2
+  %cmp.loop = icmp ult i64 %iv.next, %n
+  br i1 %cmp.loop, label %loop, label %exit
+
+exit:
+  ret void
+}
+
+define void @scev_add_udiv3_expanded(ptr %dst, i64 %n) {
+; CHECK-LABEL: VPlan for loop in 'scev_add_udiv3_expanded'
+; CHECK:  VPlan 'Final VPlan for VF={4},UF={1}' {
+; CHECK-NEXT:  Live-in ir<%2> = original trip-count
+; CHECK-EMPTY:
+; CHECK-NEXT:  ir-bb<loop.preheader>:
+; CHECK-NEXT:    IR   %0 = add i64 %n, -1
+; CHECK-NEXT:    IR   %1 = udiv i64 %0, 3
+; CHECK-NEXT:    IR   %2 = add nuw nsw i64 %1, 1
+; CHECK-NEXT:    EMIT vp<%min.iters.check> = icmp ult ir<%2>, ir<4>
+; CHECK-NEXT:    EMIT branch-on-cond vp<%min.iters.check>
+; CHECK-NEXT:  Successor(s): ir-bb<scalar.ph>, vector.ph
+;
+entry:
+  %cmp = icmp ugt i64 %n, 3
+  br i1 %cmp, label %loop, label %exit
+
+loop:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+  %gep = getelementptr i8, ptr %dst, i64 %iv
+  store i8 0, ptr %gep
+  %iv.next = add nuw i64 %iv, 3
+  %cmp.loop = icmp ult i64 %iv.next, %n
+  br i1 %cmp.loop, label %loop, label %exit
+
+exit:
+  ret void
+}
+
+define void @scev_expand_vscale_mul(ptr %dst, i64 %n) {
+; CHECK-LABEL: VPlan for loop in 'scev_expand_vscale_mul'
+; CHECK:  VPlan 'Final VPlan for VF={vscale x 4},UF={1}' {
+; CHECK-NEXT:  Live-in ir<%n> = original trip-count
+; CHECK-EMPTY:
+; CHECK-NEXT:  ir-bb<loop.preheader>:
+; CHECK-NEXT:    IR   %0 = call i64 @llvm.vscale.i64()
+; CHECK-NEXT:    IR   %1 = shl nuw i64 %0, 2
+; CHECK-NEXT:    EMIT vp<%min.iters.check> = icmp ult ir<%n>, ir<%1>
+; CHECK-NEXT:    EMIT branch-on-cond vp<%min.iters.check>
+; CHECK-NEXT:  Successor(s): ir-bb<scalar.ph>, vector.ph
+;
+entry:
+  %cmp = icmp ne i64 %n, 0
+  br i1 %cmp, label %loop, label %exit
+
+loop:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+  %gep = getelementptr i8, ptr %dst, i64 %iv
+  store i8 0, ptr %gep
+  %iv.next = add nuw i64 %iv, 1
+  %cmp.loop = icmp ult i64 %iv.next, %n
+  br i1 %cmp.loop, label %loop, label %exit, !llvm.loop !0
+
+exit:
+  ret void
+}
+
+!0 = distinct !{!0, !1, !2}
+!1 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
+!2 = !{!"llvm.loop.vectorize.width", i32 4}