[llvm] [DAG] computeKnownFPClass - add ISD::FNEG handling + test coverage (PR #190325)

[via llvm-commits]

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@@ -52,3 +52,28 @@ define <vscale x 2 x i1> @splat_constant_f64_isinf_false() {
   ret <vscale x 2 x i1> %res
 }
 
+define <4 x i1> @fneg_vec_not_negative(<4 x i32> %vecbits) nounwind {
+; CHECK-LABEL: fneg_vec_not_negative:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT:    vmclr.m v0
+; CHECK-NEXT:    ret
+  %masked = or <4 x i32> %vecbits, splat(i32 u0x80000000) ; set sign bits
+  %fvec = bitcast <4 x i32> %masked to <4 x float>
+  %neg = fneg <4 x float> %fvec
+  %res = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %neg, i32 60) ; any negative
+  ret <4 x i1> %res
+}
+
+define <4 x i1> @fneg_vec_not_positive(<4 x i32> %vecbits) nounwind {
+; CHECK-LABEL: fneg_vec_not_positive:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT:    vmclr.m v0
+; CHECK-NEXT:    ret
+  %masked = and <4 x i32> %vecbits, splat(i32 u0x7fffffff) ; clear sign bit
+  %fvec = bitcast <4 x i32> %masked to <4 x float>
+  %neg = fneg <4 x float> %fvec
+  %res = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %neg, i32 960) ; any positive
+  ret <4 x i1> %res
+}
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s-mv wrote:

Added a negative case (fneg_vec_unknown_sign) where no folding occurs

https://github.com/llvm/llvm-project/pull/190325