[llvm] [PowerPC] Simplify implementation of atomis loads (PR #191044)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 8 12:54:36 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-powerpc
Author: Kai Nacke (redstar)
<details>
<summary>Changes</summary>
The code for atomic loads is verbose. There are 10 different operations and 4 memory sizes to support, which means 40 pseudo instructions are used, with all the details repeated. This PR changes the following:
- Use a loop over the operations and the sizes to create the pseudo instruction
- Adds the memory size as last operand to the pseudo instruction
- Updates the C++ code to take advantage of the memory size in the pseudo instruction
---
Patch is 26.46 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/191044.diff
4 Files Affected:
- (modified) llvm/lib/Target/PowerPC/PPCISelLowering.cpp (+71-79)
- (modified) llvm/lib/Target/PowerPC/PPCISelLowering.h (-2)
- (modified) llvm/lib/Target/PowerPC/PPCInstr64Bit.td (+21-35)
- (modified) llvm/lib/Target/PowerPC/PPCInstrInfo.td (+36-113)
``````````diff
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index d21ccb59f9962..394b464b0f435 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -13048,14 +13048,16 @@ Instruction *PPCTargetLowering::emitTrailingFence(IRBuilderBase &Builder,
return nullptr;
}
-MachineBasicBlock *
-PPCTargetLowering::EmitAtomicBinary(MachineInstr &MI, MachineBasicBlock *BB,
- unsigned AtomicSize,
- unsigned BinOpcode,
- unsigned CmpOpcode,
- unsigned CmpPred) const {
- // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
+MachineBasicBlock *PPCTargetLowering::EmitAtomicBinary(MachineInstr &MI,
+ MachineBasicBlock *BB,
+ unsigned BinOpcode,
+ unsigned CmpOpcode,
+ unsigned CmpPred) const {
+ // BinOpcode != 0: Handles atomic load with binary operator, e.g. NAND.
+ // CmpOpcode != 0: Handles atomic load with MIN/MAX etc.
+ // BinOpcode == 0 && CmpOpcode == 0: Handles ATOMIC_SWAP.
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
+ unsigned AtomicSize = MI.getOperand(MI.getNumExplicitOperands()-1).getImm();
auto LoadMnemonic = PPC::LDARX;
auto StoreMnemonic = PPC::STDCX;
@@ -13227,10 +13229,11 @@ static bool isSignExtended(MachineInstr &MI, const PPCInstrInfo *TII) {
}
MachineBasicBlock *PPCTargetLowering::EmitPartwordAtomicBinary(
- MachineInstr &MI, MachineBasicBlock *BB,
- bool is8bit, // operation
- unsigned BinOpcode, unsigned CmpOpcode, unsigned CmpPred) const {
- // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
+ MachineInstr &MI, MachineBasicBlock *BB, unsigned BinOpcode,
+ unsigned CmpOpcode, unsigned CmpPred) const {
+ // BinOpcode != 0: Handles atomic load with binary operator, e.g. NAND.
+ // CmpOpcode != 0: Handles atomic load with MIN/MAX etc.
+ // BinOpcode == 0 && CmpOpcode == 0: Handles ATOMIC_SWAP.
const PPCInstrInfo *TII = Subtarget.getInstrInfo();
// If this is a signed comparison and the value being compared is not known
@@ -13242,6 +13245,7 @@ MachineBasicBlock *PPCTargetLowering::EmitPartwordAtomicBinary(
bool IsSignExtended =
incr.isVirtual() && isSignExtended(*RegInfo.getVRegDef(incr), TII);
+ const bool is8bit = MI.getOperand(MI.getNumExplicitOperands()-1).getImm() == 1;
if (CmpOpcode == PPC::CMPW && !IsSignExtended) {
Register ValueReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
BuildMI(*BB, MI, dl, TII->get(is8bit ? PPC::EXTSB : PPC::EXTSH), ValueReg)
@@ -13251,8 +13255,7 @@ MachineBasicBlock *PPCTargetLowering::EmitPartwordAtomicBinary(
}
// If we support part-word atomic mnemonics, just use them
if (Subtarget.hasPartwordAtomics())
- return EmitAtomicBinary(MI, BB, is8bit ? 1 : 2, BinOpcode, CmpOpcode,
- CmpPred);
+ return EmitAtomicBinary(MI, BB, BinOpcode, CmpOpcode, CmpPred);
// In 64 bit mode we have to use 64 bits for addresses, even though the
// lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
@@ -14080,104 +14083,93 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
BB->addSuccessor(readMBB);
BB->addSuccessor(sinkMBB);
- } else if (MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
- BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
- else if (MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
- BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
+ } else if (MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I8 ||
+ MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
+ BB = EmitPartwordAtomicBinary(MI, BB, PPC::ADD4);
else if (MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
- BB = EmitAtomicBinary(MI, BB, 4, PPC::ADD4);
+ BB = EmitAtomicBinary(MI, BB, PPC::ADD4);
else if (MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
- BB = EmitAtomicBinary(MI, BB, 8, PPC::ADD8);
+ BB = EmitAtomicBinary(MI, BB, PPC::ADD8);
- else if (MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
- BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
- else if (MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
- BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
+ else if (MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I8 ||
+ MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
+ BB = EmitPartwordAtomicBinary(MI, BB, PPC::AND);
else if (MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
- BB = EmitAtomicBinary(MI, BB, 4, PPC::AND);
+ BB = EmitAtomicBinary(MI, BB, PPC::AND);
else if (MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
- BB = EmitAtomicBinary(MI, BB, 8, PPC::AND8);
+ BB = EmitAtomicBinary(MI, BB, PPC::AND8);
- else if (MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
- BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
- else if (MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
- BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
+ else if (MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I8 ||
+ MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
+ BB = EmitPartwordAtomicBinary(MI, BB, PPC::OR);
else if (MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
- BB = EmitAtomicBinary(MI, BB, 4, PPC::OR);
+ BB = EmitAtomicBinary(MI, BB, PPC::OR);
else if (MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
- BB = EmitAtomicBinary(MI, BB, 8, PPC::OR8);
+ BB = EmitAtomicBinary(MI, BB, PPC::OR8);
- else if (MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
- BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
- else if (MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
- BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
+ else if (MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I8 ||
+ MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
+ BB = EmitPartwordAtomicBinary(MI, BB, PPC::XOR);
else if (MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
- BB = EmitAtomicBinary(MI, BB, 4, PPC::XOR);
+ BB = EmitAtomicBinary(MI, BB, PPC::XOR);
else if (MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
- BB = EmitAtomicBinary(MI, BB, 8, PPC::XOR8);
+ BB = EmitAtomicBinary(MI, BB, PPC::XOR8);
- else if (MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
- BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
- else if (MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
- BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
+ else if (MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I8 ||
+ MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
+ BB = EmitPartwordAtomicBinary(MI, BB, PPC::NAND);
else if (MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
- BB = EmitAtomicBinary(MI, BB, 4, PPC::NAND);
+ BB = EmitAtomicBinary(MI, BB, PPC::NAND);
else if (MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
- BB = EmitAtomicBinary(MI, BB, 8, PPC::NAND8);
+ BB = EmitAtomicBinary(MI, BB, PPC::NAND8);
- else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
- BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
- else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
- BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
+ else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I8 ||
+ MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
+ BB = EmitPartwordAtomicBinary(MI, BB, PPC::SUBF);
else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
- BB = EmitAtomicBinary(MI, BB, 4, PPC::SUBF);
+ BB = EmitAtomicBinary(MI, BB, PPC::SUBF);
else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
- BB = EmitAtomicBinary(MI, BB, 8, PPC::SUBF8);
+ BB = EmitAtomicBinary(MI, BB, PPC::SUBF8);
- else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I8)
- BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPW, PPC::PRED_LT);
- else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I16)
- BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPW, PPC::PRED_LT);
+ else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I8 ||
+ MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I16)
+ BB = EmitPartwordAtomicBinary(MI, BB, 0, PPC::CMPW, PPC::PRED_LT);
else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I32)
- BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPW, PPC::PRED_LT);
+ BB = EmitAtomicBinary(MI, BB, 0, PPC::CMPW, PPC::PRED_LT);
else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I64)
- BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPD, PPC::PRED_LT);
+ BB = EmitAtomicBinary(MI, BB, 0, PPC::CMPD, PPC::PRED_LT);
- else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I8)
- BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPW, PPC::PRED_GT);
- else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I16)
- BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPW, PPC::PRED_GT);
+ else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I8 ||
+ MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I16)
+ BB = EmitPartwordAtomicBinary(MI, BB, 0, PPC::CMPW, PPC::PRED_GT);
else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I32)
- BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPW, PPC::PRED_GT);
+ BB = EmitAtomicBinary(MI, BB, 0, PPC::CMPW, PPC::PRED_GT);
else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I64)
- BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPD, PPC::PRED_GT);
+ BB = EmitAtomicBinary(MI, BB, 0, PPC::CMPD, PPC::PRED_GT);
- else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I8)
- BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPLW, PPC::PRED_LT);
- else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I16)
- BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPLW, PPC::PRED_LT);
+ else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I8 ||
+ MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I16)
+ BB = EmitPartwordAtomicBinary(MI, BB, 0, PPC::CMPLW, PPC::PRED_LT);
else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I32)
- BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPLW, PPC::PRED_LT);
+ BB = EmitAtomicBinary(MI, BB, 0, PPC::CMPLW, PPC::PRED_LT);
else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I64)
- BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPLD, PPC::PRED_LT);
+ BB = EmitAtomicBinary(MI, BB, 0, PPC::CMPLD, PPC::PRED_LT);
- else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I8)
- BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPLW, PPC::PRED_GT);
- else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I16)
- BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPLW, PPC::PRED_GT);
+ else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I8 ||
+ MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I16)
+ BB = EmitPartwordAtomicBinary(MI, BB, 0, PPC::CMPLW, PPC::PRED_GT);
else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I32)
- BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPLW, PPC::PRED_GT);
+ BB = EmitAtomicBinary(MI, BB, 0, PPC::CMPLW, PPC::PRED_GT);
else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I64)
- BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPLD, PPC::PRED_GT);
+ BB = EmitAtomicBinary(MI, BB, 0, PPC::CMPLD, PPC::PRED_GT);
- else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I8)
- BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
- else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I16)
- BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
+ else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I8 ||
+ MI.getOpcode() == PPC::ATOMIC_SWAP_I16)
+ BB = EmitPartwordAtomicBinary(MI, BB, 0);
else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I32)
- BB = EmitAtomicBinary(MI, BB, 4, 0);
+ BB = EmitAtomicBinary(MI, BB, 0);
else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I64)
- BB = EmitAtomicBinary(MI, BB, 8, 0);
+ BB = EmitAtomicBinary(MI, BB, 0);
else if (MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I64 ||
(Subtarget.hasPartwordAtomics() &&
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
index 7077d7fa486e1..d82339c597dac 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -373,13 +373,11 @@ namespace llvm {
MachineBasicBlock *MBB) const override;
MachineBasicBlock *EmitAtomicBinary(MachineInstr &MI,
MachineBasicBlock *MBB,
- unsigned AtomicSize,
unsigned BinOpcode,
unsigned CmpOpcode = 0,
unsigned CmpPred = 0) const;
MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr &MI,
MachineBasicBlock *MBB,
- bool is8bit,
unsigned Opcode,
unsigned CmpOpcode = 0,
unsigned CmpPred = 0) const;
diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
index a973654c22c38..29e2a3afb5060 100644
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -265,47 +265,33 @@ def : Pat<(PPCcall_nop_rm (i64 mcsym:$dst)),
// clean this up in PPCMIPeephole with calls to
// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them
// in the first place.
-let Defs = [CR0] in {
- def ATOMIC_LOAD_ADD_I64 : PPCCustomInserterPseudo<
- (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64",
- [(set i64:$dst, (atomic_load_add_i64 ForceXForm:$ptr, i64:$incr))]>;
- def ATOMIC_LOAD_SUB_I64 : PPCCustomInserterPseudo<
- (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64",
- [(set i64:$dst, (atomic_load_sub_i64 ForceXForm:$ptr, i64:$incr))]>;
- def ATOMIC_LOAD_OR_I64 : PPCCustomInserterPseudo<
- (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64",
- [(set i64:$dst, (atomic_load_or_i64 ForceXForm:$ptr, i64:$incr))]>;
- def ATOMIC_LOAD_XOR_I64 : PPCCustomInserterPseudo<
- (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64",
- [(set i64:$dst, (atomic_load_xor_i64 ForceXForm:$ptr, i64:$incr))]>;
- def ATOMIC_LOAD_AND_I64 : PPCCustomInserterPseudo<
- (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64",
- [(set i64:$dst, (atomic_load_and_i64 ForceXForm:$ptr, i64:$incr))]>;
- def ATOMIC_LOAD_NAND_I64 : PPCCustomInserterPseudo<
- (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64",
- [(set i64:$dst, (atomic_load_nand_i64 ForceXForm:$ptr, i64:$incr))]>;
- def ATOMIC_LOAD_MIN_I64 : PPCCustomInserterPseudo<
- (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64",
- [(set i64:$dst, (atomic_load_min_i64 ForceXForm:$ptr, i64:$incr))]>;
- def ATOMIC_LOAD_MAX_I64 : PPCCustomInserterPseudo<
- (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64",
- [(set i64:$dst, (atomic_load_max_i64 ForceXForm:$ptr, i64:$incr))]>;
- def ATOMIC_LOAD_UMIN_I64 : PPCCustomInserterPseudo<
- (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64",
- [(set i64:$dst, (atomic_load_umin_i64 ForceXForm:$ptr, i64:$incr))]>;
- def ATOMIC_LOAD_UMAX_I64 : PPCCustomInserterPseudo<
- (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64",
- [(set i64:$dst, (atomic_load_umax_i64 ForceXForm:$ptr, i64:$incr))]>;
+foreach op = ["add", "sub", "and", "or", "xor", "nand", "min", "max", "umax",
+ "umin"] in {
+ defvar pat = !cast<PatFrag>("atomic_load_"#op#"_i64");
+ defvar pseudo = "ATOMIC_LOAD_"#!toupper(op)#"_I64";
+ let Defs = [CR0] in
+ def pseudo : PPCCustomInserterPseudo<
+ (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr, i32imm:$sz),
+ "#" # NAME, []>;
+ def : Pat<(i64 (pat ForceXForm:$ptr, g8rc:$incr)),
+ (!cast<Instruction>(pseudo) memrr:$ptr, g8rc:$incr, 8)>;
+}
+let Defs = [CR0] in {
def ATOMIC_CMP_SWAP_I64 : PPCCustomInserterPseudo<
- (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64",
- [(set i64:$dst, (atomic_cmp_swap_i64 ForceXForm:$ptr, i64:$old, i64:$new))]>;
+ (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new, i32imm:$sz),
+ "#" # NAME, []>;
def ATOMIC_SWAP_I64 : PPCCustomInserterPseudo<
- (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64",
- [(set i64:$dst, (atomic_swap_i64 ForceXForm:$ptr, i64:$new))]>;
+ (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new, i32imm:$sz),
+ "#" # NAME, []>;
}
+def : Pat<(i64 (atomic_cmp_swap_i64 ForceXForm:$ptr, g8rc:$old, g8rc:$new)),
+ (ATOMIC_CMP_SWAP_I64 memrr:$ptr, i64:$old, i64:$new, 8)>;
+def : Pat<(i64 (atomic_swap_i64 ForceXForm:$ptr, g8rc:$new)),
+ (ATOMIC_SWAP_I64 memrr:$ptr, i64:$new, 8)>;
+
// Instructions to support atomic operations
let mayLoad = 1, mayStore = 1, hasSideEffects = 1 in {
def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index e3240a72a113f..ba66d9e6bb274 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2011,123 +2011,46 @@ def : Pat<(int_ppc_dcbtst_with_hint xoaddr:$dst, i32:$TH),
// clean this up in PPCMIPeephole with calls to
// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them
// in the first place.
-let Defs = [CR0] in {
- def ATOMIC_LOAD_ADD_I8 : PPCCustomInserterPseudo<
- (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
- [(set i32:$dst, (atomic_load_add_i8 ForceXForm:$ptr, i32:$incr))]>;
- def ATOMIC_LOAD_SUB_I8 : PPCCustomInserterPseudo<
- (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
- [(set i32:$dst, (atomic_load_sub_i8 ForceXForm:$ptr, i32:$incr))]>;
- def ATOMIC_LOAD_AND_I8 : PPCCustomInserterPseudo<
- (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
- [(set i32:$dst, (atomic_load_and_i8 ForceXForm:$ptr, i32:$incr))]>;
- def ATOMIC_LOAD_OR_I8 : PPCCustomInserterPseudo<
- (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
- [(set i32:$dst, (atomic_load_or_i8 ForceXForm:$ptr, i32:$incr))]>;
- def ATOMIC_LOAD_XOR_I8 : PPCCustomInserterPseudo<
- (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
- [(set i32:$dst, (atomic_load_xor_i8 ForceXForm:$ptr, i32:$incr))]>;
- def ATOMIC_LOAD_NAND_I8 : PPCCustomInserterPseudo<
- (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
- [(set i32:$dst, (atomic_load_nand_i8 ForceXForm:$ptr, i32:$incr))]>;
- def ATOMIC_LOAD_MIN_I8 : PPCCustomInserterPseudo<
- (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I8",
- [(set i32:$dst, (atomic_load_min_i8 ForceXForm:$ptr, i32:$incr))]>;
- def ATOMIC_LOAD_MAX_I8 : PPCCustomInserterPseudo<
- (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I8",
- [(set i32:$dst, (atomic_load_max_i8 ForceXForm:$ptr, i32:$incr))]>;
- def ATOMIC_LOAD_UMIN_I8 : PPCCustomInserterPseudo<
- (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I8",
- [(set i32:$dst, (atomic_load_umin_i8 ForceXForm:$ptr, i32:$incr))]>;
- def ATOMIC_LOAD_UMAX_I8 : PPCCustomInserterPseudo<
- (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I8",
- [(set i32:$dst, (atomic_load_umax_i8 ForceXForm:$ptr, i32:$incr))]>;
- def ATOMIC_LOAD_ADD_I16 : PPCCustomInserterPseudo<
- (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
- [(set i32:$dst, (atomic_load_add_i16 ForceXForm:$ptr, i32:$incr))]>;
- def ATOMIC_LOAD_SUB_I16 : PPCCustomInserterPseudo<
- (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
- [(set i32:$dst, (atomic_load_sub_i16 ForceXForm:$ptr, i32:$incr))]>;
- def ATOMIC_LOAD_AND_I16 : PPCCustomInserterPseudo<
- (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
- [(set i32:$dst, (atomic_load_and_i16 ForceXForm:$ptr, i32:$incr))]>;
- def ATOMIC_LOAD_OR_I16 : PPCCustomInserterPseudo<
- (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
- [(set i...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/191044
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