[llvm] [AMDGPU][GISel] RegBankLegalize rules for SWMMAC instructions (PR #190997)
Chinmay Deshpande via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 8 09:01:07 PDT 2026
https://github.com/chinmaydd updated https://github.com/llvm/llvm-project/pull/190997
>From 20771b7b16485fee5fdc5d32fb2e6704a385b685 Mon Sep 17 00:00:00 2001
From: Chinmay Deshpande <chdeshpa at amd.com>
Date: Wed, 8 Apr 2026 11:54:00 -0400
Subject: [PATCH 1/2] [AMDGPU][GISel] RegBankLegalize rules for SWMMAC
instructions
---
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 26 +++++++++++++++----
.../wmma-gfx12-w32-swmmac-index_key.ll | 4 +--
.../wmma-gfx12-w64-swmmac-index_key.ll | 4 +--
3 files changed, 25 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 969c703a4fd38..93ddad3b41028 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1814,18 +1814,18 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(S32, {{UniInVgprS32}, {IntrId, Imm, Vgpr32, Imm, Vgpr32, Vgpr32}})
.Div(S32, {{Vgpr32}, {IntrId, Imm, Vgpr32, Imm, Vgpr32, Vgpr32}});
- // WMMA intrinsics: all register operands map to VGPR.
+ // WMMA/SWMMAC intrinsics: all register operands map to VGPR.
addRulesForIOpcs(
- {// GFX11+
+ {// WMMA GFX11+
amdgcn_wmma_f32_16x16x16_f16, amdgcn_wmma_f32_16x16x16_bf16,
amdgcn_wmma_f16_16x16x16_f16, amdgcn_wmma_bf16_16x16x16_bf16,
amdgcn_wmma_f16_16x16x16_f16_tied, amdgcn_wmma_bf16_16x16x16_bf16_tied,
amdgcn_wmma_i32_16x16x16_iu8, amdgcn_wmma_i32_16x16x16_iu4,
- // GFX12
+ // WMMA GFX12
amdgcn_wmma_f32_16x16x16_fp8_fp8, amdgcn_wmma_f32_16x16x16_fp8_bf8,
amdgcn_wmma_f32_16x16x16_bf8_fp8, amdgcn_wmma_f32_16x16x16_bf8_bf8,
amdgcn_wmma_i32_16x16x32_iu4,
- // GFX1250
+ // WMMA GFX1250
amdgcn_wmma_f32_16x16x4_f32, amdgcn_wmma_f32_16x16x32_bf16,
amdgcn_wmma_f32_16x16x32_f16, amdgcn_wmma_f16_16x16x32_f16,
amdgcn_wmma_bf16_16x16x32_bf16, amdgcn_wmma_bf16f32_16x16x32_bf16,
@@ -1841,7 +1841,23 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
amdgcn_wmma_scale_f32_16x16x128_f8f6f4,
amdgcn_wmma_scale16_f32_16x16x128_f8f6f4, amdgcn_wmma_f32_32x16x128_f4,
amdgcn_wmma_scale_f32_32x16x128_f4,
- amdgcn_wmma_scale16_f32_32x16x128_f4})
+ amdgcn_wmma_scale16_f32_32x16x128_f4,
+ // SWMMAC GFX12
+ amdgcn_swmmac_f32_16x16x32_f16, amdgcn_swmmac_f32_16x16x32_bf16,
+ amdgcn_swmmac_f16_16x16x32_f16, amdgcn_swmmac_bf16_16x16x32_bf16,
+ amdgcn_swmmac_i32_16x16x32_iu8, amdgcn_swmmac_i32_16x16x32_iu4,
+ amdgcn_swmmac_i32_16x16x64_iu4,
+ amdgcn_swmmac_f32_16x16x32_fp8_fp8, amdgcn_swmmac_f32_16x16x32_fp8_bf8,
+ amdgcn_swmmac_f32_16x16x32_bf8_fp8, amdgcn_swmmac_f32_16x16x32_bf8_bf8,
+ // SWMMAC GFX1250
+ amdgcn_swmmac_f32_16x16x64_f16, amdgcn_swmmac_f32_16x16x64_bf16,
+ amdgcn_swmmac_f16_16x16x64_f16, amdgcn_swmmac_bf16_16x16x64_bf16,
+ amdgcn_swmmac_bf16f32_16x16x64_bf16,
+ amdgcn_swmmac_f32_16x16x128_fp8_fp8, amdgcn_swmmac_f32_16x16x128_fp8_bf8,
+ amdgcn_swmmac_f32_16x16x128_bf8_fp8, amdgcn_swmmac_f32_16x16x128_bf8_bf8,
+ amdgcn_swmmac_f16_16x16x128_fp8_fp8, amdgcn_swmmac_f16_16x16x128_fp8_bf8,
+ amdgcn_swmmac_f16_16x16x128_bf8_fp8, amdgcn_swmmac_f16_16x16x128_bf8_bf8,
+ amdgcn_swmmac_i32_16x16x128_iu8})
.Any({{}, {{}, {}, ApplyAllVgpr}});
} // end initialize rules
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-swmmac-index_key.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-swmmac-index_key.ll
index a3d0da7dfc143..31b64c249b335 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-swmmac-index_key.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-swmmac-index_key.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1170 < %s | FileCheck %s --check-prefixes=GCN,GFX1170
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s --check-prefixes=GCN,GFX12
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1170 < %s | FileCheck %s --check-prefixes=GCN,GFX1170
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s --check-prefixes=GCN,GFX12
define amdgpu_ps void @test_swmmac_f32_16x16x32_f16_index_key(<8 x half> %A, <16 x half> %B, <8 x float> %C, ptr addrspace(1) %IndexVecPtr, ptr addrspace(1) %out0, ptr addrspace(1) %out1) {
; GFX1170-LABEL: test_swmmac_f32_16x16x32_f16_index_key:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-swmmac-index_key.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-swmmac-index_key.ll
index 7d31e262b4862..8a614ab61aced 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-swmmac-index_key.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-swmmac-index_key.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1170 -mattr=+wavefrontsize64 < %s | FileCheck %s --check-prefixes=GCN,GFX1170
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 < %s | FileCheck %s --check-prefixes=GCN,GFX12
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1170 -mattr=+wavefrontsize64 < %s | FileCheck %s --check-prefixes=GCN,GFX1170
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 < %s | FileCheck %s --check-prefixes=GCN,GFX12
define amdgpu_ps void @test_swmmac_f32_16x16x32_f16_index_key(<4 x half> %A, <8 x half> %B, <4 x float> %C, ptr addrspace(1) %IndexVecPtr, ptr addrspace(1) %out0, ptr addrspace(1) %out1, ptr addrspace(1) %out2, ptr addrspace(1) %out3) {
; GFX1170-LABEL: test_swmmac_f32_16x16x32_f16_index_key:
>From 75225d7a8fcef7dabf222610f4a187b84b0e12d1 Mon Sep 17 00:00:00 2001
From: Chinmay Deshpande <chdeshpa at amd.com>
Date: Wed, 8 Apr 2026 12:00:53 -0400
Subject: [PATCH 2/2] [AMDGPU] Fix formatting
---
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 20 +++++++++----------
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 93ddad3b41028..137b055952ba0 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1840,24 +1840,22 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
amdgcn_wmma_i32_16x16x64_iu8, amdgcn_wmma_f32_16x16x128_f8f6f4,
amdgcn_wmma_scale_f32_16x16x128_f8f6f4,
amdgcn_wmma_scale16_f32_16x16x128_f8f6f4, amdgcn_wmma_f32_32x16x128_f4,
- amdgcn_wmma_scale_f32_32x16x128_f4,
- amdgcn_wmma_scale16_f32_32x16x128_f4,
+ amdgcn_wmma_scale_f32_32x16x128_f4, amdgcn_wmma_scale16_f32_32x16x128_f4,
// SWMMAC GFX12
amdgcn_swmmac_f32_16x16x32_f16, amdgcn_swmmac_f32_16x16x32_bf16,
amdgcn_swmmac_f16_16x16x32_f16, amdgcn_swmmac_bf16_16x16x32_bf16,
amdgcn_swmmac_i32_16x16x32_iu8, amdgcn_swmmac_i32_16x16x32_iu4,
- amdgcn_swmmac_i32_16x16x64_iu4,
- amdgcn_swmmac_f32_16x16x32_fp8_fp8, amdgcn_swmmac_f32_16x16x32_fp8_bf8,
- amdgcn_swmmac_f32_16x16x32_bf8_fp8, amdgcn_swmmac_f32_16x16x32_bf8_bf8,
+ amdgcn_swmmac_i32_16x16x64_iu4, amdgcn_swmmac_f32_16x16x32_fp8_fp8,
+ amdgcn_swmmac_f32_16x16x32_fp8_bf8, amdgcn_swmmac_f32_16x16x32_bf8_fp8,
+ amdgcn_swmmac_f32_16x16x32_bf8_bf8,
// SWMMAC GFX1250
amdgcn_swmmac_f32_16x16x64_f16, amdgcn_swmmac_f32_16x16x64_bf16,
amdgcn_swmmac_f16_16x16x64_f16, amdgcn_swmmac_bf16_16x16x64_bf16,
- amdgcn_swmmac_bf16f32_16x16x64_bf16,
- amdgcn_swmmac_f32_16x16x128_fp8_fp8, amdgcn_swmmac_f32_16x16x128_fp8_bf8,
- amdgcn_swmmac_f32_16x16x128_bf8_fp8, amdgcn_swmmac_f32_16x16x128_bf8_bf8,
- amdgcn_swmmac_f16_16x16x128_fp8_fp8, amdgcn_swmmac_f16_16x16x128_fp8_bf8,
- amdgcn_swmmac_f16_16x16x128_bf8_fp8, amdgcn_swmmac_f16_16x16x128_bf8_bf8,
- amdgcn_swmmac_i32_16x16x128_iu8})
+ amdgcn_swmmac_bf16f32_16x16x64_bf16, amdgcn_swmmac_f32_16x16x128_fp8_fp8,
+ amdgcn_swmmac_f32_16x16x128_fp8_bf8, amdgcn_swmmac_f32_16x16x128_bf8_fp8,
+ amdgcn_swmmac_f32_16x16x128_bf8_bf8, amdgcn_swmmac_f16_16x16x128_fp8_fp8,
+ amdgcn_swmmac_f16_16x16x128_fp8_bf8, amdgcn_swmmac_f16_16x16x128_bf8_fp8,
+ amdgcn_swmmac_f16_16x16x128_bf8_bf8, amdgcn_swmmac_i32_16x16x128_iu8})
.Any({{}, {{}, {}, ApplyAllVgpr}});
} // end initialize rules
More information about the llvm-commits
mailing list