[llvm] daf7a8f - AMDGPU coverity fixes (#182013)

[via llvm-commits]

Author: Rafał Rudnicki
Date: 2026-04-08T11:49:15Z
New Revision: daf7a8f835c6c385934d73e67bafbf81daaebf5e

URL: https://github.com/llvm/llvm-project/commit/daf7a8f835c6c385934d73e67bafbf81daaebf5e
DIFF: https://github.com/llvm/llvm-project/commit/daf7a8f835c6c385934d73e67bafbf81daaebf5e.diff

LOG: AMDGPU coverity fixes (#182013)

Coverity fixes

Added: 
    llvm/test/CodeGen/AMDGPU/inline-asm-vgpr-range-unsupported-width.ll

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
    llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
    llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
index 9fb7bba4b22cc..56592bde3b1c7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
@@ -247,6 +247,7 @@ void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
     LLVMContext &C = MI->getMF()->getFunction().getContext();
     C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
                 "a target-specific version: " + Twine(MI->getOpcode()));
+    return;
   }
 
   OutMI.setOpcode(MCOpcode);

diff  --git a/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp b/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
index 7a5db42c7a89a..931a2854c54f9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
@@ -205,7 +205,8 @@ bool AMDGPURewriteAGPRCopyMFMAImpl::recomputeRegClassExceptRewritable(
       if (!NewRC || NewRC == OldRC) {
         LLVM_DEBUG(dbgs() << "User of " << printReg(Reg, &TRI)
                           << " cannot be reassigned to "
-                          << TRI.getRegClassName(NewRC) << ": " << *MI);
+                          << (NewRC ? TRI.getRegClassName(NewRC) : "NULL")
+                          << ": " << *MI);
         return false;
       }
     }

diff  --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 2eda82ca296cc..562225d808992 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -18597,7 +18597,7 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI_,
       // Check for lossy scalar/vector conversions.
       if (VT.isVector() && VT.getSizeInBits() != 32)
         return std::pair(0U, nullptr);
-      if (Idx < RC->getNumRegs())
+      if (RC && Idx < RC->getNumRegs())
         return std::pair(RC->getRegister(Idx), RC);
       return std::pair(0U, nullptr);
     }

diff  --git a/llvm/test/CodeGen/AMDGPU/inline-asm-vgpr-range-unsupported-width.ll b/llvm/test/CodeGen/AMDGPU/inline-asm-vgpr-range-unsupported-width.ll
new file mode 100644
index 0000000000000..4596c18643f5e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/inline-asm-vgpr-range-unsupported-width.ll
@@ -0,0 +1,12 @@
+; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=null %s 2>&1 | FileCheck %s
+
+; This is a negative test: the VGPR physical register range below requires
+; a 13-register (416-bit) VGPR, which doesn't exist.
+
+; CHECK: error: couldn't allocate output register for constraint '{v[0:12]}'
+
+define amdgpu_kernel void @k() {
+entry:
+  %x = call i416 asm sideeffect "", "={v[0:12]}"()
+  ret void
+}