[llvm] [AMDGPU][CodeGen] Implement SimplifyDemandedBitsForTargetNode for readlane, wwm and set.inactive intrinsics. (PR #190830)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 8 01:55:54 PDT 2026
================
@@ -0,0 +1,266 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
+
+define void @readfirstlane_demanded_i8_zext_store(i8 %src, ptr addrspace(1) %ptr) {
+; GCN-LABEL: readfirstlane_demanded_i8_zext_store:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_readfirstlane_b32 s4, v0
+; GCN-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NEXT: global_store_byte v[1:2], v0, off
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %zext = zext i8 %src to i32
+ %readfirstlane = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %zext)
+ %trunc = trunc i32 %readfirstlane to i8
+ store i8 %trunc, ptr addrspace(1) %ptr
+ ret void
+}
+
+define void @readfirstlane_demanded_i8_sext_store(i8 %src, ptr addrspace(1) %ptr) {
+; GCN-LABEL: readfirstlane_demanded_i8_sext_store:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_readfirstlane_b32 s4, v0
+; GCN-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NEXT: global_store_byte v[1:2], v0, off
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %sext = sext i8 %src to i32
+ %readfirstlane = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %sext)
+ %trunc = trunc i32 %readfirstlane to i8
+ store i8 %trunc, ptr addrspace(1) %ptr
+ ret void
+}
+
+define i16 @readfirstlane_demanded_i16_zext(i16 %src) {
+; GCN-LABEL: readfirstlane_demanded_i16_zext:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_readfirstlane_b32 s4, v0
+; GCN-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %zext = zext i16 %src to i32
+ %readfirstlane = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %zext)
+ %trunc = trunc i32 %readfirstlane to i16
+ ret i16 %trunc
+}
+
+define i16 @readfirstlane_demanded_i16_sext(i16 %src) {
+; GCN-LABEL: readfirstlane_demanded_i16_sext:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_readfirstlane_b32 s4, v0
+; GCN-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %sext = sext i16 %src to i32
+ %readfirstlane = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %sext)
+ %trunc = trunc i32 %readfirstlane to i16
+ ret i16 %trunc
+}
+
+define void @readlane_demanded_i8_zext_store(i8 %src, ptr addrspace(1) %ptr) {
+; GCN-LABEL: readlane_demanded_i8_zext_store:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_readlane_b32 s4, v0, 0
+; GCN-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NEXT: global_store_byte v[1:2], v0, off
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %zext = zext i8 %src to i32
+ %readlane = call i32 @llvm.amdgcn.readlane.i32(i32 %zext, i32 0)
+ %trunc = trunc i32 %readlane to i8
+ store i8 %trunc, ptr addrspace(1) %ptr
+ ret void
+}
+
+define void @readlane_demanded_i8_sext_store(i8 %src, ptr addrspace(1) %ptr) {
+; GCN-LABEL: readlane_demanded_i8_sext_store:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_readlane_b32 s4, v0, 0
+; GCN-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NEXT: global_store_byte v[1:2], v0, off
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %sext = sext i8 %src to i32
+ %readlane = call i32 @llvm.amdgcn.readlane.i32(i32 %sext, i32 0)
+ %trunc = trunc i32 %readlane to i8
+ store i8 %trunc, ptr addrspace(1) %ptr
+ ret void
+}
+
+define i16 @readlane_demanded_i16_zext(i16 %src) {
+; GCN-LABEL: readlane_demanded_i16_zext:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_readlane_b32 s4, v0, 0
+; GCN-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %zext = zext i16 %src to i32
+ %readlane = call i32 @llvm.amdgcn.readlane.i32(i32 %zext, i32 0)
+ %trunc = trunc i32 %readlane to i16
+ ret i16 %trunc
+}
+
+define i16 @readlane_demanded_i16_sext(i16 %src) {
+; GCN-LABEL: readlane_demanded_i16_sext:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_readlane_b32 s4, v0, 0
+; GCN-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %sext = sext i16 %src to i32
+ %readlane = call i32 @llvm.amdgcn.readlane.i32(i32 %sext, i32 0)
+ %trunc = trunc i32 %readlane to i16
+ ret i16 %trunc
+}
+
+define void @wwm_demanded_i8_zext_store(i8 %src, ptr addrspace(1) %ptr) {
+; GCN-LABEL: wwm_demanded_i8_zext_store:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: s_xor_saveexec_b64 s[4:5], -1
+; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-NEXT: s_mov_b64 exec, s[4:5]
+; GCN-NEXT: s_or_saveexec_b64 s[4:5], -1
+; GCN-NEXT: v_mov_b32_e32 v3, v0
+; GCN-NEXT: s_mov_b64 exec, s[4:5]
+; GCN-NEXT: v_mov_b32_e32 v0, v3
+; GCN-NEXT: global_store_byte v[1:2], v0, off
+; GCN-NEXT: s_xor_saveexec_b64 s[4:5], -1
+; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-NEXT: s_mov_b64 exec, s[4:5]
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %zext = zext i8 %src to i32
+ %wwm = call i32 @llvm.amdgcn.wwm(i32 %zext)
+ %trunc = trunc i32 %wwm to i8
+ store i8 %trunc, ptr addrspace(1) %ptr
+ ret void
+}
+
+define void @wwm_demanded_i8_sext_store(i8 %src, ptr addrspace(1) %ptr) {
+; GCN-LABEL: wwm_demanded_i8_sext_store:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: s_xor_saveexec_b64 s[4:5], -1
+; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-NEXT: s_mov_b64 exec, s[4:5]
+; GCN-NEXT: s_or_saveexec_b64 s[4:5], -1
+; GCN-NEXT: v_mov_b32_e32 v3, v0
+; GCN-NEXT: s_mov_b64 exec, s[4:5]
+; GCN-NEXT: v_mov_b32_e32 v0, v3
+; GCN-NEXT: global_store_byte v[1:2], v0, off
+; GCN-NEXT: s_xor_saveexec_b64 s[4:5], -1
+; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-NEXT: s_mov_b64 exec, s[4:5]
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %sext = sext i8 %src to i32
+ %wwm = call i32 @llvm.amdgcn.wwm(i32 %sext)
+ %trunc = trunc i32 %wwm to i8
+ store i8 %trunc, ptr addrspace(1) %ptr
+ ret void
+}
+
+define i16 @wwm_demanded_i16_zext(i16 %src) {
+; GCN-LABEL: wwm_demanded_i16_zext:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: s_xor_saveexec_b64 s[4:5], -1
+; GCN-NEXT: buffer_store_dword v1, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-NEXT: s_mov_b64 exec, s[4:5]
+; GCN-NEXT: s_or_saveexec_b64 s[4:5], -1
+; GCN-NEXT: v_mov_b32_e32 v1, v0
+; GCN-NEXT: s_mov_b64 exec, s[4:5]
+; GCN-NEXT: v_mov_b32_e32 v0, v1
+; GCN-NEXT: s_xor_saveexec_b64 s[4:5], -1
+; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-NEXT: s_mov_b64 exec, s[4:5]
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %zext = zext i16 %src to i32
+ %wwm = call i32 @llvm.amdgcn.wwm(i32 %zext)
+ %trunc = trunc i32 %wwm to i16
+ ret i16 %trunc
+}
+
+define i16 @wwm_demanded_i16_sext(i16 %src) {
+; GCN-LABEL: wwm_demanded_i16_sext:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: s_xor_saveexec_b64 s[4:5], -1
+; GCN-NEXT: buffer_store_dword v1, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-NEXT: s_mov_b64 exec, s[4:5]
+; GCN-NEXT: s_or_saveexec_b64 s[4:5], -1
+; GCN-NEXT: v_mov_b32_e32 v1, v0
+; GCN-NEXT: s_mov_b64 exec, s[4:5]
+; GCN-NEXT: v_mov_b32_e32 v0, v1
+; GCN-NEXT: s_xor_saveexec_b64 s[4:5], -1
+; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-NEXT: s_mov_b64 exec, s[4:5]
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %sext = sext i16 %src to i32
+ %wwm = call i32 @llvm.amdgcn.wwm(i32 %sext)
+ %trunc = trunc i32 %wwm to i16
+ ret i16 %trunc
+}
+
+define void @set.inactive_demanded_i8_zext_store(i8 %src, ptr addrspace(1) %ptr) {
+; GCN-LABEL: set.inactive_demanded_i8_zext_store:
+; GCN: ; %bb.0:
+; GCN-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $exec
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: global_store_byte v[1:2], v0, off
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %zext = zext i8 %src to i32
+ %set.inactive = call i32 @llvm.amdgcn.set.inactive(i32 %zext, i32 0)
----------------
arsenm wrote:
Missing type mangling suffix
https://github.com/llvm/llvm-project/pull/190830
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