[llvm] [DAG] computeKnownFPClass - add ISD::FNEG handling + test coverage (PR #190325)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 7 14:08:26 PDT 2026
https://github.com/s-mv updated https://github.com/llvm/llvm-project/pull/190325
>From 5ae6819b7fe18e21534b510e6da76f878ca7c1a9 Mon Sep 17 00:00:00 2001
From: smv <shreerangvaidya28 at gmail.com>
Date: Fri, 3 Apr 2026 14:50:33 +0530
Subject: [PATCH 1/4] [DAG] add ISD::FNEG handling to computeKnownFPClass +
tests
---
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 6 +++
llvm/test/CodeGen/RISCV/known-fpclass-fneg.ll | 40 +++++++++++++++++++
2 files changed, 46 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/known-fpclass-fneg.ll
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 137922aa62557..151ae19af3bfa 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -6057,6 +6057,12 @@ KnownFPClass SelectionDAG::computeKnownFPClass(SDValue Op,
Known.SignBit = false;
break;
}
+ case ISD::FNEG: {
+ Known = computeKnownFPClass(Op.getOperand(0), DemandedElts,
+ InterestedClasses, Depth + 1);
+ Known.fneg();
+ break;
+ }
case ISD::BUILD_VECTOR: {
assert(!VT.isScalableVector());
bool First = true;
diff --git a/llvm/test/CodeGen/RISCV/known-fpclass-fneg.ll b/llvm/test/CodeGen/RISCV/known-fpclass-fneg.ll
new file mode 100644
index 0000000000000..3c1c02c8d8a75
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/known-fpclass-fneg.ll
@@ -0,0 +1,40 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+f,+d | FileCheck %s
+
+declare i1 @llvm.is.fpclass.f32(float, i32)
+
+define i1 @fneg_const_not_inf() nounwind {
+; CHECK-LABEL: fneg_const_not_inf:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a0, 0
+; CHECK-NEXT: ret
+ %n = fneg float 1.0
+ %r = call i1 @llvm.is.fpclass.f32(float %n, i32 512) ; +inf
+ ret i1 %r
+}
+
+define i1 @fneg_mask_not_nan(i32 %a) nounwind {
+; CHECK-LABEL: fneg_mask_not_nan:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a0, 0
+; CHECK-NEXT: ret
+ %m = and i32 %a, u0x007fffff
+ %x = bitcast i32 %m to float
+ %n = fneg float %x
+ %r = call i1 @llvm.is.fpclass.f32(float %n, i32 3) ; nan
+ ret i1 %r
+}
+
+define i1 @fneg_shift_not_inf(i32 %x) nounwind {
+; CHECK-LABEL: fneg_shift_not_inf:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a0, 0
+; CHECK-NEXT: ret
+ %shl = shl i32 %x, 2
+ %shr = lshr i32 %shl, 2
+ %y = bitcast i32 %shr to float
+
+ %n = fneg float %y
+ %r = call i1 @llvm.is.fpclass.f32(float %n, i32 512) ; +inf
+ ret i1 %r
+}
>From 27a8b8b02bc99d80c2aac3a667406bb5043c331a Mon Sep 17 00:00:00 2001
From: smv <shreerangvaidya28 at gmail.com>
Date: Fri, 3 Apr 2026 17:36:24 +0530
Subject: [PATCH 2/4] [DAG] vector test case for ISD::FNEG handling
---
llvm/test/CodeGen/RISCV/known-fpclass-fneg.ll | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/known-fpclass-fneg.ll b/llvm/test/CodeGen/RISCV/known-fpclass-fneg.ll
index 3c1c02c8d8a75..896a37639aca2 100644
--- a/llvm/test/CodeGen/RISCV/known-fpclass-fneg.ll
+++ b/llvm/test/CodeGen/RISCV/known-fpclass-fneg.ll
@@ -2,6 +2,7 @@
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+f,+d | FileCheck %s
declare i1 @llvm.is.fpclass.f32(float, i32)
+declare <4 x i1> @llvm.is.fpclass.vf32(<4 x float>, i32)
define i1 @fneg_const_not_inf() nounwind {
; CHECK-LABEL: fneg_const_not_inf:
@@ -38,3 +39,22 @@ define i1 @fneg_shift_not_inf(i32 %x) nounwind {
%r = call i1 @llvm.is.fpclass.f32(float %n, i32 512) ; +inf
ret i1 %r
}
+
+define <4 x i1> @fneg_vec_not_inf(<4 x i32> %vecbits) nounwind {
+; CHECK-LABEL: fneg_vec_not_inf:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 262144
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vfneg.v v8, v8
+; CHECK-NEXT: vfclass.v v8, v8
+; CHECK-NEXT: vand.vi v8, v8, 14
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: ret
+ %masked = and <4 x i32> %vecbits, <i32 u0x3fffffff, i32 u0x3fffffff, i32 u0x3fffffff, i32 u0x3fffffff>
+ %fvec = bitcast <4 x i32> %masked to <4 x float>
+ %neg = fneg <4 x float> %fvec
+ %res = call <4 x i1> @llvm.is.fpclass.vf32(<4 x float> %neg, i32 312) ; +inf
+ ret <4 x i1> %res
+}
>From fcaf4bbd83105e7b9747ad4636b26c33692ea205 Mon Sep 17 00:00:00 2001
From: smv <shreerangvaidya28 at gmail.com>
Date: Fri, 3 Apr 2026 19:54:48 +0530
Subject: [PATCH 3/4] [DAG] computeKnownFPClass - update tests
- Replace test fneg_vec_not_inf with fneg_vec_not_negative
- Remove fneg_const_not_inf
---
llvm/test/CodeGen/RISCV/combine-is_fpclass.ll | 38 ++++++++++++
llvm/test/CodeGen/RISCV/known-fpclass-fneg.ll | 60 -------------------
2 files changed, 38 insertions(+), 60 deletions(-)
delete mode 100644 llvm/test/CodeGen/RISCV/known-fpclass-fneg.ll
diff --git a/llvm/test/CodeGen/RISCV/combine-is_fpclass.ll b/llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
index 5049775710628..e9bf8b6c38b11 100644
--- a/llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
+++ b/llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
@@ -52,3 +52,41 @@ define <vscale x 2 x i1> @splat_constant_f64_isinf_false() {
ret <vscale x 2 x i1> %res
}
+define i1 @fneg_mask_not_nan(i32 %a) nounwind {
+; CHECK-LABEL: fneg_mask_not_nan:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a0, 0
+; CHECK-NEXT: ret
+ %m = and i32 %a, u0x007fffff
+ %x = bitcast i32 %m to float
+ %n = fneg float %x
+ %r = call i1 @llvm.is.fpclass.f32(float %n, i32 3) ; nan
+ ret i1 %r
+}
+
+define i1 @fneg_shift_not_inf(i32 %x) nounwind {
+; CHECK-LABEL: fneg_shift_not_inf:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a0, 0
+; CHECK-NEXT: ret
+ %shl = shl i32 %x, 2
+ %shr = lshr i32 %shl, 2
+ %y = bitcast i32 %shr to float
+
+ %n = fneg float %y
+ %r = call i1 @llvm.is.fpclass.f32(float %n, i32 512) ; +inf
+ ret i1 %r
+}
+
+define <4 x i1> @fneg_vec_not_negative(<4 x i32> %vecbits) nounwind {
+; CHECK-LABEL: fneg_vec_not_negative:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vmclr.m v0
+; CHECK-NEXT: ret
+ %masked = or <4 x i32> %vecbits, splat(i32 u0x80000000) ; set sign bits
+ %fvec = bitcast <4 x i32> %masked to <4 x float>
+ %neg = fneg <4 x float> %fvec
+ %res = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %neg, i32 60) ; any negative
+ ret <4 x i1> %res
+}
diff --git a/llvm/test/CodeGen/RISCV/known-fpclass-fneg.ll b/llvm/test/CodeGen/RISCV/known-fpclass-fneg.ll
deleted file mode 100644
index 896a37639aca2..0000000000000
--- a/llvm/test/CodeGen/RISCV/known-fpclass-fneg.ll
+++ /dev/null
@@ -1,60 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+f,+d | FileCheck %s
-
-declare i1 @llvm.is.fpclass.f32(float, i32)
-declare <4 x i1> @llvm.is.fpclass.vf32(<4 x float>, i32)
-
-define i1 @fneg_const_not_inf() nounwind {
-; CHECK-LABEL: fneg_const_not_inf:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, 0
-; CHECK-NEXT: ret
- %n = fneg float 1.0
- %r = call i1 @llvm.is.fpclass.f32(float %n, i32 512) ; +inf
- ret i1 %r
-}
-
-define i1 @fneg_mask_not_nan(i32 %a) nounwind {
-; CHECK-LABEL: fneg_mask_not_nan:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, 0
-; CHECK-NEXT: ret
- %m = and i32 %a, u0x007fffff
- %x = bitcast i32 %m to float
- %n = fneg float %x
- %r = call i1 @llvm.is.fpclass.f32(float %n, i32 3) ; nan
- ret i1 %r
-}
-
-define i1 @fneg_shift_not_inf(i32 %x) nounwind {
-; CHECK-LABEL: fneg_shift_not_inf:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, 0
-; CHECK-NEXT: ret
- %shl = shl i32 %x, 2
- %shr = lshr i32 %shl, 2
- %y = bitcast i32 %shr to float
-
- %n = fneg float %y
- %r = call i1 @llvm.is.fpclass.f32(float %n, i32 512) ; +inf
- ret i1 %r
-}
-
-define <4 x i1> @fneg_vec_not_inf(<4 x i32> %vecbits) nounwind {
-; CHECK-LABEL: fneg_vec_not_inf:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lui a0, 262144
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vand.vx v8, v8, a0
-; CHECK-NEXT: vfneg.v v8, v8
-; CHECK-NEXT: vfclass.v v8, v8
-; CHECK-NEXT: vand.vi v8, v8, 14
-; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: ret
- %masked = and <4 x i32> %vecbits, <i32 u0x3fffffff, i32 u0x3fffffff, i32 u0x3fffffff, i32 u0x3fffffff>
- %fvec = bitcast <4 x i32> %masked to <4 x float>
- %neg = fneg <4 x float> %fvec
- %res = call <4 x i1> @llvm.is.fpclass.vf32(<4 x float> %neg, i32 312) ; +inf
- ret <4 x i1> %res
-}
>From 2ab158b57196f3f8382aff68adc8c959c360ff53 Mon Sep 17 00:00:00 2001
From: smv <shreerangvaidya28 at gmail.com>
Date: Wed, 8 Apr 2026 02:28:20 +0530
Subject: [PATCH 4/4] [DAG] computeKnownFPClass: rewrite ISD::FNEG tests
- Add vector test fneg_vec_not_positive
- Remove fneg_mask_not_nan, fneg_shift_not_inf
---
llvm/test/CodeGen/RISCV/combine-is_fpclass.ll | 39 +++++++------------
1 file changed, 13 insertions(+), 26 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/combine-is_fpclass.ll b/llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
index e9bf8b6c38b11..b5f920c5046b2 100644
--- a/llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
+++ b/llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
@@ -52,32 +52,6 @@ define <vscale x 2 x i1> @splat_constant_f64_isinf_false() {
ret <vscale x 2 x i1> %res
}
-define i1 @fneg_mask_not_nan(i32 %a) nounwind {
-; CHECK-LABEL: fneg_mask_not_nan:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, 0
-; CHECK-NEXT: ret
- %m = and i32 %a, u0x007fffff
- %x = bitcast i32 %m to float
- %n = fneg float %x
- %r = call i1 @llvm.is.fpclass.f32(float %n, i32 3) ; nan
- ret i1 %r
-}
-
-define i1 @fneg_shift_not_inf(i32 %x) nounwind {
-; CHECK-LABEL: fneg_shift_not_inf:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, 0
-; CHECK-NEXT: ret
- %shl = shl i32 %x, 2
- %shr = lshr i32 %shl, 2
- %y = bitcast i32 %shr to float
-
- %n = fneg float %y
- %r = call i1 @llvm.is.fpclass.f32(float %n, i32 512) ; +inf
- ret i1 %r
-}
-
define <4 x i1> @fneg_vec_not_negative(<4 x i32> %vecbits) nounwind {
; CHECK-LABEL: fneg_vec_not_negative:
; CHECK: # %bb.0:
@@ -90,3 +64,16 @@ define <4 x i1> @fneg_vec_not_negative(<4 x i32> %vecbits) nounwind {
%res = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %neg, i32 60) ; any negative
ret <4 x i1> %res
}
+
+define <4 x i1> @fneg_vec_not_positive(<4 x i32> %vecbits) nounwind {
+; CHECK-LABEL: fneg_vec_not_positive:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT: vmclr.m v0
+; CHECK-NEXT: ret
+ %masked = and <4 x i32> %vecbits, splat(i32 u0x7fffffff) ; clear sign bit
+ %fvec = bitcast <4 x i32> %masked to <4 x float>
+ %neg = fneg <4 x float> %fvec
+ %res = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %neg, i32 960) ; any positive
+ ret <4 x i1> %res
+}
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