[llvm] [DAG] Add Srl combine for extracting last element of BUILD_VECTOR (PR #181412)

[Frederick Vu via llvm-commits]

FrederickVu wrote:

> The fold seems reasonable, but I don't know how generally useful it is. It doesn't seem to have any effect on targets like RISCV and X86. Would it make more sense to change `SITargetLowering::lowerEXTRACT_VECTOR_ELT` to do this directly, instead of creating the `srl`?

I believe when I originally observed this, SimplifyDemandedBits ran after extract_vector_elt was lowered to a srl. Additionally, in `llvm/test/CodeGen/AMDGPU/move-to-valu-lshl_add.ll` it seems the `srl`s are not created by extract_vector_elt, and the `BUILD_VECTOR`s which trigger this PR's fold are created during legalization. 

https://github.com/llvm/llvm-project/pull/181412