[llvm] [AArch64] Codegen for AArch64 Return Address Signing Hardening (PR #176187)

[Anatoly Trosinenko via llvm-commits]

================
@@ -276,5 +327,78 @@ bool AArch64PointerAuth::runOnMachineFunction(MachineFunction &MF) {
     Modified = true;
   }
 
+  Modified |= emitSignReturnAddressHardening(MF);
+
+  return Modified;
+}
+
+bool AArch64PointerAuth::emitSignReturnAddressHardening(MachineFunction &MF) {
+  const auto *FI = MF.getInfo<AArch64FunctionInfo>();
+  assert(FI && "FI can't be null");
+  if (!FI->shouldSignReturnAddress(MF) || !FI->shouldHardenSignReturnAddress())
+    return false;
+  assert(Subtarget && "Subtarget must be initialized");
+
+  bool Modified = false;
+  for (MachineBasicBlock &MBB : MF) {
+    if (!MBB.isReturnBlock())
+      continue;
+
+    MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
+
+    if (MBBI == MBB.end() || MBBI->getOpcode() != AArch64::RET)
+      continue;
+
+    DebugLoc DL = MBBI->getDebugLoc();
+
+    Register XReg = RSHelper.findRegister(MBBI);
+
+    // Register copies are done using ORRXrs directly instead of using the
+    // pseudo-instruction COPY because this function can be called after
+    // pseudo-instruction expansion takes place, for example via the machine
+    // outliner pass.
+    BuildMI(MBB, MBBI, DL, TII->get(AArch64::ORRXrs), XReg)
+        .addUse(AArch64::XZR)
+        .addUse(AArch64::LR)
+        .addImm(0)
+        .setMIFlag(MachineInstr::FrameDestroy);
+
+    // The XPACI instruction is only available with FEAT_PAUTH. So if the
+    // subtarget does not have it, the alternative XPACLRI instruction must be
+    // used instead. The latter is in hint space, therefore can be present even
+    // if FEAT_PAUTH is absent.
----------------
atrosinenko wrote:

By the way, in addition to the two links mentioned in the description, this one seems to be important to understand the implications of FPAC: https://developer.arm.com/documentation/110389/latest/ Without this information, I would assume something like
```
MOV X0, LR
XPACI X0
LDR W0, [X0]
AUTIASP
RET
```
to be required with `FEAT_FPAC`, as otherwise I would expect failed AUTIASP to stop speculation without speculating later XPACI and LDR instructions.

https://github.com/llvm/llvm-project/pull/176187