[llvm] [LV] Fix cmp-select reduction phi backedge when fold tail. (PR #190752)

[Florian Hahn via llvm-commits]

https://github.com/fhahn commented:

> Checked and there's no diffs on `-target aarch64-linux-gnu -march=armv9-a -O3`, or on RISC-V currently. LGTM

I'm not sure, but I don't think this enables tail-folding by default? Not sure which CPUs enable tail-folding by default, but I'd expect a number of changes (at least on the IR level) when tail-folding is enabled. I am surprised that we don't have coverage in the existing tests.

But I'd expect this to change codegen for any loop with tail-folding, below is a reduced version for AArch64 with `opt -p loop-vectorize -prefer-predicate-over-epilogue=predicate-dont-vectorize -mcpu=neoverse-v2`.

I'd expect moving the select inside the loop and feeding the reduction will have some negative performance impact.  I think in terms of the state of the VPlan where we transform the VPlan, the current code should be fine and it is only the EVL lowering that makes it problematic? If so, is there any way to handle this together with the EVL lowering? Otherwise other transforms may get this wrong in similar fashion.

```
target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
target triple = "arm64-apple-macosx15.0.0"

define i32 @zot(i32 %arg) {
bb:
  %icmp = icmp sgt i32 %arg, 0
  br i1 %icmp, label %bb1, label %bb5

bb1:                                              ; preds = %bb1, %bb
  %phi = phi i64 [ %add, %bb1 ], [ 0, %bb ]
  %phi2 = phi i32 [ %select, %bb1 ], [ 0, %bb ]
  %icmp3 = icmp eq i32 0, 0
  %trunc = trunc i64 %phi to i32
  %select = select i1 %icmp3, i32 %trunc, i32 %phi2
  %add = add i64 %phi, 1
  %zext = zext i32 %arg to i64
  %icmp4 = icmp eq i64 %phi, %zext
  br i1 %icmp4, label %bb5, label %bb1

bb5:                                              ; preds = %bb1, %bb
  %phi6 = phi i32 [ %select, %bb1 ], [ 0, %bb ]
  ret i32 %phi6
}
```

https://github.com/llvm/llvm-project/pull/190752