[llvm] [LV][NFC] Remove more unused function attributes from tests (PR #190786)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 7 05:56:41 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-transforms
@llvm/pr-subscribers-backend-amdgpu
Author: David Sherwood (david-arm)
<details>
<summary>Changes</summary>
Following on from PR #<!-- -->188185 I've removed some more function attributes from tests that weren't adding any value. As part of this patch I've also removed some unnecessary `Function Attrs:` comments that live above functions.
I suspect that there are other attributes that can be removed, for example see ARM/arm-ieee-vectorize.ll. However, I haven't had chance to look into these yet as they are more FP and/or target specific and perhaps require more thought.
---
Patch is 85.48 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/190786.diff
66 Files Affected:
- (modified) llvm/test/Transforms/LoopVectorize/2012-10-20-infloop.ll (+2-2)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/aarch64-unroll.ll (-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/arm64-unroll.ll (-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll (-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/pr33053.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/pr36032.ll (+1-2)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses-cost.ll (-1)
- (modified) llvm/test/Transforms/LoopVectorize/AMDGPU/divergent-runtime-check.ll (+1-2)
- (modified) llvm/test/Transforms/LoopVectorize/AMDGPU/unroll-in-loop-vectorizer.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/ARM/active-lane-mask.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/ARM/arm-ieee-vectorize.ll (+2-2)
- (modified) llvm/test/Transforms/LoopVectorize/Hexagon/maximum-vf-crash.ll (-1)
- (modified) llvm/test/Transforms/LoopVectorize/Hexagon/minimum-vf.ll (+4-6)
- (modified) llvm/test/Transforms/LoopVectorize/LoongArch/loongarch-interleaved.ll (-1)
- (modified) llvm/test/Transforms/LoopVectorize/PowerPC/interleave_IC.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/PowerPC/massv-altivec.ll (+4-6)
- (modified) llvm/test/Transforms/LoopVectorize/PowerPC/massv-calls.ll (+62-64)
- (modified) llvm/test/Transforms/LoopVectorize/PowerPC/massv-unsupported.ll (-2)
- (modified) llvm/test/Transforms/LoopVectorize/PowerPC/reg-usage.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/PowerPC/stride-vectorization.ll (+1-2)
- (modified) llvm/test/Transforms/LoopVectorize/PowerPC/vectorize-bswap.ll (-1)
- (modified) llvm/test/Transforms/LoopVectorize/PowerPC/vectorize-only-for-real.ll (+7-12)
- (modified) llvm/test/Transforms/LoopVectorize/PowerPC/vsx-tsvc-s173.ll (+1-3)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/riscv-interleaved.ll (+1-4)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/riscv-unroll.ll (-1)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/short-trip-count.ll (+2-2)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/unroll-in-loop-vectorizer.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-half.ll (-2)
- (modified) llvm/test/Transforms/LoopVectorize/X86/already-vectorized.ll (-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/consecutive-ptr-cg-bug.ll (-2)
- (modified) llvm/test/Transforms/LoopVectorize/X86/fp_to_sint8-cost-model.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/int128_no_gather.ll (+2-7)
- (modified) llvm/test/Transforms/LoopVectorize/X86/interleaved-accesses-use-after-free.ll (-3)
- (modified) llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll (+8-9)
- (modified) llvm/test/Transforms/LoopVectorize/X86/no-vector.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/no_fpmath.ll (+1-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/no_fpmath_with_hotness.ll (+2-6)
- (modified) llvm/test/Transforms/LoopVectorize/X86/pr35432.ll (-2)
- (modified) llvm/test/Transforms/LoopVectorize/X86/pr48340.ll (+2-2)
- (modified) llvm/test/Transforms/LoopVectorize/X86/register-assumption.ll (+1-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/scatter_crash.ll (+1-2)
- (modified) llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll (-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/uint64_to_fp64-cost-model.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/vector_ptr_load_store.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll (+4-9)
- (modified) llvm/test/Transforms/LoopVectorize/assume.ll (+1-3)
- (modified) llvm/test/Transforms/LoopVectorize/conditional-assignment.ll (+1-4)
- (modified) llvm/test/Transforms/LoopVectorize/control-flow.ll (+1-4)
- (modified) llvm/test/Transforms/LoopVectorize/dbg.value.ll (+2-7)
- (modified) llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-variable-size.ll (-1)
- (modified) llvm/test/Transforms/LoopVectorize/diag-missing-instr-debug-loc.ll (+1-2)
- (modified) llvm/test/Transforms/LoopVectorize/diag-with-hotness-info-2.ll (+1-4)
- (modified) llvm/test/Transforms/LoopVectorize/diag-with-hotness-info.ll (+1-4)
- (modified) llvm/test/Transforms/LoopVectorize/ee-crash.ll (+1-3)
- (modified) llvm/test/Transforms/LoopVectorize/global_alias.ll (+7-7)
- (modified) llvm/test/Transforms/LoopVectorize/if-reduction.ll (+42-42)
- (modified) llvm/test/Transforms/LoopVectorize/incorrect-dom-info.ll (+1-2)
- (modified) llvm/test/Transforms/LoopVectorize/induction.ll (+2-2)
- (modified) llvm/test/Transforms/LoopVectorize/int_sideeffect.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/no_array_bounds.ll (+1-4)
- (modified) llvm/test/Transforms/LoopVectorize/no_switch.ll (+1-4)
- (modified) llvm/test/Transforms/LoopVectorize/no_switch_disable_vectorization.ll (+1-4)
- (modified) llvm/test/Transforms/LoopVectorize/pointer-induction.ll (-1)
- (modified) llvm/test/Transforms/LoopVectorize/reuse-lcssa-phi-scev-expansion.ll (-1)
- (modified) llvm/test/Transforms/LoopVectorize/scalable-assume.ll (+1-3)
``````````diff
diff --git a/llvm/test/Transforms/LoopVectorize/2012-10-20-infloop.ll b/llvm/test/Transforms/LoopVectorize/2012-10-20-infloop.ll
index 36a1ce2b5f08f..57c2d62f7661b 100644
--- a/llvm/test/Transforms/LoopVectorize/2012-10-20-infloop.ll
+++ b/llvm/test/Transforms/LoopVectorize/2012-10-20-infloop.ll
@@ -1,7 +1,7 @@
; RUN: opt < %s -passes=loop-vectorize,dce -force-vector-interleave=1 -force-vector-width=4
; Check that we don't fall into an infinite loop.
-define void @test() nounwind {
+define void @test() {
entry:
br label %for.body
@@ -12,7 +12,7 @@ for.body:
-define void @test2() nounwind {
+define void @test2() {
entry:
br label %for.body
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/aarch64-unroll.ll b/llvm/test/Transforms/LoopVectorize/AArch64/aarch64-unroll.ll
index 4df0ad9e0eb19..0a6bf1e504699 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/aarch64-unroll.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/aarch64-unroll.ll
@@ -1,7 +1,6 @@
; RUN: opt < %s -passes=loop-vectorize -mtriple=aarch64-none-linux-gnu -mattr=+neon -S | FileCheck %s
target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
-; Function Attrs: nounwind
define ptr @array_add(ptr noalias nocapture readonly %a, ptr noalias nocapture readonly %b, ptr %c, i32 %size) {
;CHECK-LABEL: array_add
;CHECK: load <4 x i32>
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/arm64-unroll.ll b/llvm/test/Transforms/LoopVectorize/AArch64/arm64-unroll.ll
index 8e963fc5997b8..b6a56df837bb8 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/arm64-unroll.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/arm64-unroll.ll
@@ -1,7 +1,6 @@
; RUN: opt < %s -passes=loop-vectorize -mtriple=arm64-none-linux-gnu -mattr=+neon -S | FileCheck %s
target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
-; Function Attrs: nounwind
define ptr @array_add(ptr noalias nocapture readonly %a, ptr noalias nocapture readonly %b, ptr %c, i32 %size) {
;CHECK-LABEL: array_add
;CHECK: load <4 x i32>
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll
index 98d3ee86cf276..76b43215a593c 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll
@@ -7,7 +7,6 @@
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-none-unknown-elf"
-; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: read) vscale_range(1,16)
define i32 @chained_partial_reduce_add_sub(ptr %a, ptr %b, ptr %c, i32 %N) #0 {
; CHECK-NEON-LABEL: define i32 @chained_partial_reduce_add_sub(
; CHECK-NEON-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/pr33053.ll b/llvm/test/Transforms/LoopVectorize/AArch64/pr33053.ll
index 11f7a7e5f02d0..cd1d3c9eecc24 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/pr33053.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/pr33053.ll
@@ -37,7 +37,7 @@ for.end: ; preds = %for.body
ret i32 %conv27
}
-attributes #0 = { norecurse nounwind readonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+neon" "use-soft-float"="false" }
+attributes #0 = { readonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+neon" "use-soft-float"="false" }
!llvm.ident = !{!0}
!0 = !{!"clang"}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/pr36032.ll b/llvm/test/Transforms/LoopVectorize/AArch64/pr36032.ll
index 1c04cc0a00307..baa7064d4c8ca 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/pr36032.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/pr36032.ll
@@ -10,8 +10,7 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
@c = global [6 x i8] zeroinitializer, align 1
@b = internal global %struct.anon zeroinitializer, align 1
-; Function Attrs: noreturn nounwind
-define void @_Z1dv() #0 {
+define void @_Z1dv() {
; CHECK-LABEL: @_Z1dv(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CALL:%.*]] = tail call ptr @"_ZN3$_01aEv"(ptr nonnull @b)
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses-cost.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses-cost.ll
index 564fba65e6238..f9462a795a010 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses-cost.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses-cost.ll
@@ -5,7 +5,6 @@ target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:
; Test cases for modeling interleave access costs.
-; Function Attrs: vscale_range(2,2)
define void @test_masked_interleave(ptr noalias %A, ptr noalias %B, ptr noalias %C) #0 {
; CHECK-LABEL: define void @test_masked_interleave(
; CHECK-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]]) #[[ATTR0:[0-9]+]] {
diff --git a/llvm/test/Transforms/LoopVectorize/AMDGPU/divergent-runtime-check.ll b/llvm/test/Transforms/LoopVectorize/AMDGPU/divergent-runtime-check.ll
index b1f2ccd556e21..497a422826d89 100644
--- a/llvm/test/Transforms/LoopVectorize/AMDGPU/divergent-runtime-check.ll
+++ b/llvm/test/Transforms/LoopVectorize/AMDGPU/divergent-runtime-check.ll
@@ -6,7 +6,7 @@
; GCN-NOT: store <2 x half>
; REMARK: remark: <unknown>:0:0: loop not vectorized: runtime pointer checks needed. Not enabled for divergent target
-define amdgpu_kernel void @runtime_check_divergent_target(ptr addrspace(1) nocapture %a, ptr addrspace(1) nocapture %b) #0 {
+define amdgpu_kernel void @runtime_check_divergent_target(ptr addrspace(1) nocapture %a, ptr addrspace(1) nocapture %b) {
entry:
br label %for.body
@@ -26,4 +26,3 @@ for.end: ; preds = %for.body, %entry
ret void
}
-attributes #0 = { nounwind }
diff --git a/llvm/test/Transforms/LoopVectorize/AMDGPU/unroll-in-loop-vectorizer.ll b/llvm/test/Transforms/LoopVectorize/AMDGPU/unroll-in-loop-vectorizer.ll
index ac67257fb2a40..78959a864630e 100644
--- a/llvm/test/Transforms/LoopVectorize/AMDGPU/unroll-in-loop-vectorizer.ll
+++ b/llvm/test/Transforms/LoopVectorize/AMDGPU/unroll-in-loop-vectorizer.ll
@@ -7,7 +7,7 @@
; CHECK: store i32
; CHECK-NOT: store i32
; CHECK: ret
-define amdgpu_kernel void @small_loop(ptr nocapture %inArray, i32 %size) nounwind {
+define amdgpu_kernel void @small_loop(ptr nocapture %inArray, i32 %size) {
entry:
%0 = icmp sgt i32 %size, 0
br i1 %0, label %loop, label %exit
diff --git a/llvm/test/Transforms/LoopVectorize/ARM/active-lane-mask.ll b/llvm/test/Transforms/LoopVectorize/ARM/active-lane-mask.ll
index 583e1562327a7..3ffafa404269b 100644
--- a/llvm/test/Transforms/LoopVectorize/ARM/active-lane-mask.ll
+++ b/llvm/test/Transforms/LoopVectorize/ARM/active-lane-mask.ll
@@ -60,7 +60,7 @@ for.end:
ret void
}
-attributes #0 = { nofree norecurse nounwind "target-features"="+armv8.1-m.main,+mve.fp" }
+attributes #0 = { nofree "target-features"="+armv8.1-m.main,+mve.fp" }
!1 = distinct !{!1, !2, !3}
!2 = !{!"llvm.loop.vectorize.width", i32 16}
diff --git a/llvm/test/Transforms/LoopVectorize/ARM/arm-ieee-vectorize.ll b/llvm/test/Transforms/LoopVectorize/ARM/arm-ieee-vectorize.ll
index 25799183b1a02..41124de4ec122 100644
--- a/llvm/test/Transforms/LoopVectorize/ARM/arm-ieee-vectorize.ll
+++ b/llvm/test/Transforms/LoopVectorize/ARM/arm-ieee-vectorize.ll
@@ -327,5 +327,5 @@ for.end: ; preds = %for.body, %entry
declare float @fabsf(float)
-attributes #1 = { nounwind readnone "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a8" "target-features"="+dsp,+neon,+vfp3" "use-soft-float"="false" }
-attributes #2 = { nounwind readnone "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a8" "target-features"="+dsp,+neon,+vfp3" "use-soft-float"="false" }
+attributes #1 = { readnone "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a8" "target-features"="+dsp,+neon,+vfp3" "use-soft-float"="false" }
+attributes #2 = { readnone "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a8" "target-features"="+dsp,+neon,+vfp3" "use-soft-float"="false" }
diff --git a/llvm/test/Transforms/LoopVectorize/Hexagon/maximum-vf-crash.ll b/llvm/test/Transforms/LoopVectorize/Hexagon/maximum-vf-crash.ll
index 6b201fdf21d21..199f636539b21 100644
--- a/llvm/test/Transforms/LoopVectorize/Hexagon/maximum-vf-crash.ll
+++ b/llvm/test/Transforms/LoopVectorize/Hexagon/maximum-vf-crash.ll
@@ -7,7 +7,6 @@
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
-; Function Attrs: optsize
define i32 @f(ptr %src) #0 {
entry:
br label %loop
diff --git a/llvm/test/Transforms/LoopVectorize/Hexagon/minimum-vf.ll b/llvm/test/Transforms/LoopVectorize/Hexagon/minimum-vf.ll
index 480a69c465d25..4e6f8c23ee805 100644
--- a/llvm/test/Transforms/LoopVectorize/Hexagon/minimum-vf.ll
+++ b/llvm/test/Transforms/LoopVectorize/Hexagon/minimum-vf.ll
@@ -14,8 +14,7 @@ target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i
declare void @llvm.lifetime.start.p0(ptr nocapture) #0
declare void @llvm.lifetime.end.p0(ptr nocapture) #0
-; Function Attrs: nounwind
-define hidden fastcc void @f0(ptr nocapture %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i8 zeroext %a5) unnamed_addr #1 {
+define hidden fastcc void @f0(ptr nocapture %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i8 zeroext %a5) #1 {
b0:
%v0 = alloca [4 x [9 x i16]], align 8
call void @llvm.lifetime.start.p0(ptr nonnull %v0) #2
@@ -147,13 +146,12 @@ b1: ; preds = %b1, %b0
br i1 %v120, label %b2, label %b1
b2: ; preds = %b1, %b0
- call void @llvm.lifetime.end.p0(ptr nonnull %v0) #2
+ call void @llvm.lifetime.end.p0(ptr nonnull %v0)
ret void
}
-attributes #0 = { argmemonly nounwind }
-attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }
-attributes #2 = { nounwind }
+attributes #0 = { argmemonly }
+attributes #1 = { "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }
!llvm.module.flags = !{!0}
diff --git a/llvm/test/Transforms/LoopVectorize/LoongArch/loongarch-interleaved.ll b/llvm/test/Transforms/LoopVectorize/LoongArch/loongarch-interleaved.ll
index 1de6e128d22f6..f697c7f4617d6 100644
--- a/llvm/test/Transforms/LoopVectorize/LoongArch/loongarch-interleaved.ll
+++ b/llvm/test/Transforms/LoopVectorize/LoongArch/loongarch-interleaved.ll
@@ -5,7 +5,6 @@
; CHECK-LABEL: foo
; CHECK: %{{.*}} = add {{.*}}, 8
-; Function Attrs: nofree norecurse nosync nounwind writeonly
define void @foo(i32 signext %n, ptr nocapture %A) #0 {
entry:
%cmp5 = icmp sgt i32 %n, 0
diff --git a/llvm/test/Transforms/LoopVectorize/PowerPC/interleave_IC.ll b/llvm/test/Transforms/LoopVectorize/PowerPC/interleave_IC.ll
index c1acb98b425d8..f03edf4f14807 100644
--- a/llvm/test/Transforms/LoopVectorize/PowerPC/interleave_IC.ll
+++ b/llvm/test/Transforms/LoopVectorize/PowerPC/interleave_IC.ll
@@ -20,7 +20,7 @@
target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"
-define void @test(ptr %arg, ptr %arg1) align 2 {
+define void @test(ptr %arg, ptr %arg1) {
bb:
%tpm15 = load ptr, ptr %arg, align 8
%tpm19 = load ptr, ptr %arg1, align 8
diff --git a/llvm/test/Transforms/LoopVectorize/PowerPC/massv-altivec.ll b/llvm/test/Transforms/LoopVectorize/PowerPC/massv-altivec.ll
index 3f533f15fb83e..eebf7dfbe23ec 100644
--- a/llvm/test/Transforms/LoopVectorize/PowerPC/massv-altivec.ll
+++ b/llvm/test/Transforms/LoopVectorize/PowerPC/massv-altivec.ll
@@ -3,11 +3,11 @@
target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"
-declare double @cbrt(double) #0
-declare float @cbrtf(float) #0
+declare double @cbrt(double)
+declare float @cbrtf(float)
-declare double @atanh(double) #0
-declare float @atanhf(float) #0
+declare double @atanh(double)
+declare float @atanhf(float)
; MASSV is unsupported for AltiVec.
; Check that massv entries are not generated.
@@ -102,5 +102,3 @@ for.body:
for.end:
ret void
}
-
-attributes #0 = { nounwind }
diff --git a/llvm/test/Transforms/LoopVectorize/PowerPC/massv-calls.ll b/llvm/test/Transforms/LoopVectorize/PowerPC/massv-calls.ll
index a5df23296440d..c90db2bbb4dbe 100644
--- a/llvm/test/Transforms/LoopVectorize/PowerPC/massv-calls.ll
+++ b/llvm/test/Transforms/LoopVectorize/PowerPC/massv-calls.ll
@@ -1,90 +1,90 @@
; RUN: opt -vector-library=MASSV -mtriple=powerpc64le-unknown-linux-gnu -passes=inject-tli-mappings,loop-vectorize -force-vector-interleave=1 -S < %s | FileCheck %s
; RUN: opt -vector-library=MASSV -vec-extabi -mattr=+altivec -mcpu=ppc64 -mtriple=powerpc64-ibm-aix-xcoff -passes=inject-tli-mappings,loop-vectorize -force-vector-interleave=1 -S < %s | FileCheck %s
-declare double @cbrt(double) #0
-declare float @cbrtf(float) #0
+declare double @cbrt(double)
+declare float @cbrtf(float)
-declare double @pow(double, double) #0
-declare double @llvm.pow.f64(double, double) #0
-declare float @powf(float, float) #0
-declare float @llvm.pow.f32(float, float) #0
+declare double @pow(double, double)
+declare double @llvm.pow.f64(double, double)
+declare float @powf(float, float)
+declare float @llvm.pow.f32(float, float)
-declare double @sqrt(double) #0
-declare float @sqrtf(float) #0
+declare double @sqrt(double)
+declare float @sqrtf(float)
-declare double @exp(double) #0
-declare double @llvm.exp.f64(double) #0
-declare float @expf(float) #0
-declare float @llvm.exp.f32(float) #0
+declare double @exp(double)
+declare double @llvm.exp.f64(double)
+declare float @expf(float)
+declare float @llvm.exp.f32(float)
-declare double @exp2(double) #0
-declare double @llvm.exp2.f64(double) #0
-declare float @exp2f(float) #0
-declare float @llvm.exp2.f32(float) #0
+declare double @exp2(double)
+declare double @llvm.exp2.f64(double)
+declare float @exp2f(float)
+declare float @llvm.exp2.f32(float)
-declare double @expm1(double) #0
-declare float @expm1f(float) #0
+declare double @expm1(double)
+declare float @expm1f(float)
-declare double @log(double) #0
-declare double @llvm.log.f64(double) #0
-declare float @logf(float) #0
-declare float @llvm.log.f32(float) #0
+declare double @log(double)
+declare double @llvm.log.f64(double)
+declare float @logf(float)
+declare float @llvm.log.f32(float)
-declare double @log1p(double) #0
-declare float @log1pf(float) #0
+declare double @log1p(double)
+declare float @log1pf(float)
-declare double @log10(double) #0
-declare double @llvm.log10.f64(double) #0
-declare float @log10f(float) #0
-declare float @llvm.log10.f32(float) #0
+declare double @log10(double)
+declare double @llvm.log10.f64(double)
+declare float @log10f(float)
+declare float @llvm.log10.f32(float)
-declare double @log2(double) #0
-declare double @llvm.log2.f64(double) #0
-declare float @log2f(float) #0
-declare float @llvm.log2.f32(float) #0
+declare double @log2(double)
+declare double @llvm.log2.f64(double)
+declare float @log2f(float)
+declare float @llvm.log2.f32(float)
-declare double @sin(double) #0
-declare double @llvm.sin.f64(double) #0
-declare float @sinf(float) #0
-declare float @llvm.sin.f32(float) #0
+declare double @sin(double)
+declare double @llvm.sin.f64(double)
+declare float @sinf(float)
+declare float @llvm.sin.f32(float)
-declare double @cos(double) #0
-declare double @llvm.cos.f64(double) #0
-declare float @cosf(float) #0
-declare float @llvm.cos.f32(float) #0
+declare double @cos(double)
+declare double @llvm.cos.f64(double)
+declare float @cosf(float)
+declare float @llvm.cos.f32(float)
-declare double @tan(double) #0
-declare float @tanf(float) #0
+declare double @tan(double)
+declare float @tanf(float)
-declare double @asin(double) #0
-declare float @asinf(float) #0
+declare double @asin(double)
+declare float @asinf(float)
-declare double @acos(double) #0
-declare float @acosf(float) #0
+declare double @acos(double)
+declare float @acosf(float)
-declare double @atan(double) #0
-declare float @atanf(float) #0
+declare double @atan(double)
+declare float @atanf(float)
-declare double @atan2(double, double) #0
-declare float @atan2f(float, float) #0
+declare double @atan2(double, double)
+declare float @atan2f(float, float)
-declare double @sinh(double) #0
-declare float @sinhf(float) #0
+declare double @sinh(double)
+declare float @sinhf(float)
-declare double @cosh(double) #0
-declare float @coshf(float) #0
+declare double @cosh(double)
+declare float @coshf(float)
-declare double @tanh(double) #0
-declare float @tanhf(float) #0
+declare double @tanh(double)
+declare float @tanhf(float)
-declare double @asinh(double) #0
-declare float @asinhf(float) #0
+declare double @asinh(double)
+declare float @asinhf(float)
-declare double @acosh(double) #0
-declare float @acoshf(float) #0
+declare double @acosh(double)
+declare float @acoshf(float)
-declare double @atanh(double) #0
-declare float @atanhf(float) #0
+declare double @atanh(double)
+declare float @atanhf(float)
define void @cbrt_f64(ptr nocapture %varray) {
; CHECK-LABEL: @cbrt_f64(
@@ -1565,5 +1565,3 @@ for.body:
for.end:
ret void
}
-
-attributes #0 = { nounwind }
diff --git a/llvm/test/Transforms/LoopVectorize/PowerPC/massv-unsupported.ll b/llvm/test/Transforms/LoopVectorize/PowerPC/massv-unsupported.ll
index dde36970f9b95..7e85841c420aa 100644
--- a/llvm/test/Transforms/LoopVectorize/PowerPC/massv-unsupported.ll
+++ b/llvm/test/Transforms/LoopVectorize/PowerPC/massv-unsupported.ll
@@ -108,5 +108,3 @@ for.body:
for.end:
ret void
}
-
-attributes #0 = { nounwind }
diff --git a/llvm/test/Transforms/LoopVectorize/PowerPC/reg-usage.ll b/llvm/test/Transforms/LoopVectorize/PowerPC/reg-usage.ll
index a92c7894de93c..d69d900b49732 100644
--- a/llvm/test/Transforms/LoopVectorize/PowerPC/reg-usage.ll
+++ b/llvm/test/Transforms/LoopVectorize/PowerPC/reg-usage.ll
@@ -220,7 +220,7 @@ define void @double_(ptr nocapture %A, i32 %n) {
ret void
}
-define ppc_fp128 @fp128_(ptr nocapture %n, ppc_fp128 %d) nounwind readonly {
+define ppc_fp128 @fp128_(ptr nocapture %n, ppc_fp128 %d) readonly {
;CHECK-LABEL: fp128_
;CHECK: LV(REG): VF = 1
;CHECK: LV(REG): Found max usage: 2 item
diff --git a/llvm/test/Transforms/LoopVectorize/PowerPC/stride-vectorization.ll b/llvm/test/Transforms/LoopVectorize/PowerPC/stride-vectorization.ll
index e10acf43ff8a9..40bd5a91fbbcd 100644
--- a/llvm/test/Transforms/LoopVectorize/PowerPC/stride-vectorization.ll
+++ b/llvm/test/Transforms/LoopVectorize/PowerPC/stride-vectorization.ll
@@ -2,7 +2,6 @@
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
-; Function Attrs: nounwind
define void @foo(ptr noalias nocapture %a, ptr noalias nocapture readonly %b) #0 {
entry:
br label %for.body
@@ -32,5 +31,5 @@ for.body: ; preds = %for.body, %entry
br i1 %exitcond, label %for.cond.cleanup, label %for.body
}
-attributes #0 = { nounwind "target-cpu"="pwr8" }
+attribute...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/190786
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