[llvm] [SPARC][IAS] Make 64-bit instructions available in 32-bit mode on V9 (PR #187534)

[Sergei Barannikov via llvm-commits]

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@@ -42,12 +42,15 @@ def : Pat<(i64 (sext i32:$val)), (SRAri $val, 0)>;
 def : Pat<(i64 (and i64:$val, 0xffffffff)), (SRLri $val, 0)>;
 def : Pat<(i64 (sext_inreg i64:$val, i32)), (SRAri $val, 0)>;
 
+} // Predicates = [Is64Bit]
+
+let Predicates = [HasV9] in {
+
 defm SLLX : F3_S<"sllx", 0b100101, 1, shl, i64, shift_imm6, I64Regs>;
 defm SRLX : F3_S<"srlx", 0b100110, 1, srl, i64, shift_imm6, I64Regs>;
 defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, shift_imm6, I64Regs>;
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s-barannikov wrote:

These multiclasses generate patterns with the same predicate (HasV9).
This means they will be available for instruction selection in 32-bit mode with -mcpu=v9, which, if I understand correctly, isn't right. They should only be available to code generator in 64-bit or v8plus mode only. I guess it is ok for now since we don't really support v8plus mode in codegen...
Please correct me if I'm wrong.


https://github.com/llvm/llvm-project/pull/187534