[llvm] [AArch64][SelectionDAG] use fmov for constant forming of {1.0,0.0} (PR #189921)

[Eli Friedman via llvm-commits]

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@@ -329,3 +329,93 @@ define <4 x bfloat> @negzero_v4bf16(<4 x bfloat> %a) {
 ; CHECK-NEXT:    ret
   ret <4 x bfloat> <bfloat -0.0, bfloat -0.0, bfloat -0.0, bfloat -0.0>
 }
+
+; Test that BUILD_VECTOR with an FP constant in lane 0 and +0.0 in upper lanes
+; lowers to a scalar FMOV. On AArch64, writing a scalar FP register zeroes the
+; upper bits of the enclosing vector register.
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efriedma-quic wrote:

Are there some negative tests we should add here?  Like, maybe a test with a high bit set, or a test with an immediate that isn't a getFP32Imm()?

https://github.com/llvm/llvm-project/pull/189921