[llvm] [NewPM] Port for AArch64A57FPLoadBalancing (PR #190652)
Leonardo Román Carrillo via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 6 12:38:50 PDT 2026
https://github.com/leonardo-roman-carrillo updated https://github.com/llvm/llvm-project/pull/190652
>From 2e0ee6d1718c8bf9021fbb9e103ec4572895a225 Mon Sep 17 00:00:00 2001
From: Leonardo Roman <leonardoroman at google.com>
Date: Mon, 6 Apr 2026 18:17:19 +0000
Subject: [PATCH] [NewPM] Port for AArch64A57FPLoadBalancing
---
llvm/lib/Target/AArch64/AArch64.h | 10 ++-
.../AArch64/AArch64A57FPLoadBalancing.cpp | 85 +++++++++++--------
.../Target/AArch64/AArch64PassRegistry.def | 1 +
.../Target/AArch64/AArch64TargetMachine.cpp | 4 +-
4 files changed, 62 insertions(+), 38 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64.h b/llvm/lib/Target/AArch64/AArch64.h
index a4910df6957c9..b478c5d8ec100 100644
--- a/llvm/lib/Target/AArch64/AArch64.h
+++ b/llvm/lib/Target/AArch64/AArch64.h
@@ -50,7 +50,7 @@ ModulePass *createAArch64LowerHomogeneousPrologEpilogPass();
FunctionPass *createAArch64SIMDInstrOptPass();
ModulePass *createAArch64PromoteConstantPass();
FunctionPass *createAArch64ConditionOptimizerLegacyPass();
-FunctionPass *createAArch64A57FPLoadBalancing();
+FunctionPass *createAArch64A57FPLoadBalancingLegacyPass();
FunctionPass *createAArch64A53Fix835769LegacyPass();
FunctionPass *createFalkorHWPFFixPass();
FunctionPass *createFalkorMarkStridedAccessesPass();
@@ -81,7 +81,7 @@ FunctionPass *createAArch64StackTaggingPreRAPass();
ModulePass *createAArch64Arm64ECCallLoweringPass();
void initializeAArch64A53Fix835769LegacyPass(PassRegistry &);
-void initializeAArch64A57FPLoadBalancingPass(PassRegistry&);
+void initializeAArch64A57FPLoadBalancingLegacyPass(PassRegistry&);
void initializeAArch64AdvSIMDScalarLegacyPass(PassRegistry &);
void initializeAArch64AsmPrinterPass(PassRegistry &);
void initializeAArch64PointerAuthLegacyPass(PassRegistry &);
@@ -123,6 +123,12 @@ void initializeAArch64SRLTDefineSuperRegsPass(PassRegistry &);
void initializeSVEIntrinsicOptsPass(PassRegistry &);
void initializeAArch64Arm64ECCallLoweringPass(PassRegistry &);
+class AArch64A57FPLoadBalancingPass : public PassInfoMixin<AArch64A57FPLoadBalancingPass> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+};
+
class AArch64LoadStoreOptPass : public PassInfoMixin<AArch64LoadStoreOptPass> {
public:
PreservedAnalyses run(MachineFunction &MF,
diff --git a/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp b/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
index b816f11508bed..d8d045a47c252 100644
--- a/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
+++ b/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
@@ -105,14 +105,33 @@ static const char *ColorNames[2] = { "Even", "Odd" };
class Chain;
-class AArch64A57FPLoadBalancing : public MachineFunctionPass {
+class AArch64A57FPLoadBalancingImpl {
+public:
+ bool run(MachineFunction &MF);
+
+private:
MachineRegisterInfo *MRI;
const TargetRegisterInfo *TRI;
RegisterClassInfo RCI;
+ bool runOnBasicBlock(MachineBasicBlock &MBB);
+ bool colorChainSet(std::vector<Chain*> GV, MachineBasicBlock &MBB,
+ int &Balance);
+ bool colorChain(Chain *G, Color C, MachineBasicBlock &MBB);
+ int scavengeRegister(Chain *G, Color C, MachineBasicBlock &MBB);
+ void scanInstruction(MachineInstr *MI, unsigned Idx,
+ std::map<unsigned, Chain*> &Active,
+ std::vector<std::unique_ptr<Chain>> &AllChains);
+ void maybeKillChain(MachineOperand &MO, unsigned Idx,
+ std::map<unsigned, Chain*> &RegChains);
+ Color getColor(unsigned Register);
+ Chain *getAndEraseNext(Color PreferredColor, std::vector<Chain*> &L);
+};
+
+class AArch64A57FPLoadBalancingLegacy : public MachineFunctionPass {
public:
static char ID;
- explicit AArch64A57FPLoadBalancing() : MachineFunctionPass(ID) {}
+ explicit AArch64A57FPLoadBalancingLegacy() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &F) override;
@@ -128,28 +147,14 @@ class AArch64A57FPLoadBalancing : public MachineFunctionPass {
AU.setPreservesCFG();
MachineFunctionPass::getAnalysisUsage(AU);
}
-
-private:
- bool runOnBasicBlock(MachineBasicBlock &MBB);
- bool colorChainSet(std::vector<Chain*> GV, MachineBasicBlock &MBB,
- int &Balance);
- bool colorChain(Chain *G, Color C, MachineBasicBlock &MBB);
- int scavengeRegister(Chain *G, Color C, MachineBasicBlock &MBB);
- void scanInstruction(MachineInstr *MI, unsigned Idx,
- std::map<unsigned, Chain*> &Active,
- std::vector<std::unique_ptr<Chain>> &AllChains);
- void maybeKillChain(MachineOperand &MO, unsigned Idx,
- std::map<unsigned, Chain*> &RegChains);
- Color getColor(unsigned Register);
- Chain *getAndEraseNext(Color PreferredColor, std::vector<Chain*> &L);
};
}
-char AArch64A57FPLoadBalancing::ID = 0;
+char AArch64A57FPLoadBalancingLegacy::ID = 0;
-INITIALIZE_PASS_BEGIN(AArch64A57FPLoadBalancing, DEBUG_TYPE,
+INITIALIZE_PASS_BEGIN(AArch64A57FPLoadBalancingLegacy, DEBUG_TYPE,
"AArch64 A57 FP Load-Balancing", false, false)
-INITIALIZE_PASS_END(AArch64A57FPLoadBalancing, DEBUG_TYPE,
+INITIALIZE_PASS_END(AArch64A57FPLoadBalancingLegacy, DEBUG_TYPE,
"AArch64 A57 FP Load-Balancing", false, false)
namespace {
@@ -302,10 +307,7 @@ class Chain {
//===----------------------------------------------------------------------===//
-bool AArch64A57FPLoadBalancing::runOnMachineFunction(MachineFunction &F) {
- if (skipFunction(F.getFunction()))
- return false;
-
+bool AArch64A57FPLoadBalancingImpl::run(MachineFunction &F) {
if (!F.getSubtarget<AArch64Subtarget>().balanceFPOps())
return false;
@@ -323,7 +325,23 @@ bool AArch64A57FPLoadBalancing::runOnMachineFunction(MachineFunction &F) {
return Changed;
}
-bool AArch64A57FPLoadBalancing::runOnBasicBlock(MachineBasicBlock &MBB) {
+bool AArch64A57FPLoadBalancingLegacy::runOnMachineFunction(MachineFunction &F) {
+ if (skipFunction(F.getFunction()))
+ return false;
+
+ AArch64A57FPLoadBalancingImpl Impl;
+ return Impl.run(F);
+}
+
+PreservedAnalyses AArch64A57FPLoadBalancingPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ AArch64A57FPLoadBalancingImpl Impl;
+ if (Impl.run(MF))
+ return PreservedAnalyses::none();
+ return PreservedAnalyses::all();
+}
+
+bool AArch64A57FPLoadBalancingImpl::runOnBasicBlock(MachineBasicBlock &MBB) {
bool Changed = false;
LLVM_DEBUG(dbgs() << "Running on MBB: " << MBB
<< " - scanning instructions...\n");
@@ -398,7 +416,7 @@ bool AArch64A57FPLoadBalancing::runOnBasicBlock(MachineBasicBlock &MBB) {
return Changed;
}
-Chain *AArch64A57FPLoadBalancing::getAndEraseNext(Color PreferredColor,
+Chain *AArch64A57FPLoadBalancingImpl::getAndEraseNext(Color PreferredColor,
std::vector<Chain*> &L) {
if (L.empty())
return nullptr;
@@ -434,7 +452,7 @@ Chain *AArch64A57FPLoadBalancing::getAndEraseNext(Color PreferredColor,
return Ch;
}
-bool AArch64A57FPLoadBalancing::colorChainSet(std::vector<Chain*> GV,
+bool AArch64A57FPLoadBalancingImpl::colorChainSet(std::vector<Chain*> GV,
MachineBasicBlock &MBB,
int &Parity) {
bool Changed = false;
@@ -491,7 +509,7 @@ bool AArch64A57FPLoadBalancing::colorChainSet(std::vector<Chain*> GV,
return Changed;
}
-int AArch64A57FPLoadBalancing::scavengeRegister(Chain *G, Color C,
+int AArch64A57FPLoadBalancingImpl::scavengeRegister(Chain *G, Color C,
MachineBasicBlock &MBB) {
// Can we find an appropriate register that is available throughout the life
// of the chain? Simulate liveness backwards until the end of the chain.
@@ -525,7 +543,7 @@ int AArch64A57FPLoadBalancing::scavengeRegister(Chain *G, Color C,
return -1;
}
-bool AArch64A57FPLoadBalancing::colorChain(Chain *G, Color C,
+bool AArch64A57FPLoadBalancingImpl::colorChain(Chain *G, Color C,
MachineBasicBlock &MBB) {
bool Changed = false;
LLVM_DEBUG(dbgs() << " - colorChain(" << G->str() << ", "
@@ -595,7 +613,7 @@ bool AArch64A57FPLoadBalancing::colorChain(Chain *G, Color C,
return Changed;
}
-void AArch64A57FPLoadBalancing::scanInstruction(
+void AArch64A57FPLoadBalancingImpl::scanInstruction(
MachineInstr *MI, unsigned Idx, std::map<unsigned, Chain *> &ActiveChains,
std::vector<std::unique_ptr<Chain>> &AllChains) {
// Inspect "MI", updating ActiveChains and AllChains.
@@ -675,8 +693,7 @@ void AArch64A57FPLoadBalancing::scanInstruction(
}
}
-void AArch64A57FPLoadBalancing::
-maybeKillChain(MachineOperand &MO, unsigned Idx,
+void AArch64A57FPLoadBalancingImpl::maybeKillChain(MachineOperand &MO, unsigned Idx,
std::map<unsigned, Chain*> &ActiveChains) {
// Given an operand and the set of active chains (keyed by register),
// determine if a chain should be ended and remove from ActiveChains.
@@ -708,7 +725,7 @@ maybeKillChain(MachineOperand &MO, unsigned Idx,
}
}
-Color AArch64A57FPLoadBalancing::getColor(unsigned Reg) {
+Color AArch64A57FPLoadBalancingImpl::getColor(unsigned Reg) {
if ((TRI->getEncodingValue(Reg) % 2) == 0)
return Color::Even;
else
@@ -716,6 +733,6 @@ Color AArch64A57FPLoadBalancing::getColor(unsigned Reg) {
}
// Factory function used by AArch64TargetMachine to add the pass to the passmanager.
-FunctionPass *llvm::createAArch64A57FPLoadBalancing() {
- return new AArch64A57FPLoadBalancing();
+FunctionPass *llvm::createAArch64A57FPLoadBalancingLegacyPass() {
+ return new AArch64A57FPLoadBalancingLegacy();
}
diff --git a/llvm/lib/Target/AArch64/AArch64PassRegistry.def b/llvm/lib/Target/AArch64/AArch64PassRegistry.def
index 9567d76ccf64c..d6f9e17a299a4 100644
--- a/llvm/lib/Target/AArch64/AArch64PassRegistry.def
+++ b/llvm/lib/Target/AArch64/AArch64PassRegistry.def
@@ -26,6 +26,7 @@
#ifndef MACHINE_FUNCTION_PASS
#define MACHINE_FUNCTION_PASS(NAME, CREATE_PASS)
#endif
+MACHINE_FUNCTION_PASS("aarch64-a57-fp-load-balancing", AArch64A57FPLoadBalancingPass())
MACHINE_FUNCTION_PASS("aarch64-branch-targets", AArch64BranchTargetsPass())
MACHINE_FUNCTION_PASS("aarch64-collect-loh", AArch64CollectLOHPass())
MACHINE_FUNCTION_PASS("aarch64-condopt", AArch64ConditionOptimizerPass())
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index e491cbbde415e..6a8d21e70b77b 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -244,7 +244,7 @@ LLVMInitializeAArch64Target() {
auto &PR = *PassRegistry::getPassRegistry();
initializeGlobalISel(PR);
initializeAArch64A53Fix835769LegacyPass(PR);
- initializeAArch64A57FPLoadBalancingPass(PR);
+ initializeAArch64A57FPLoadBalancingLegacyPass(PR);
initializeAArch64AdvSIMDScalarLegacyPass(PR);
initializeAArch64AsmPrinterPass(PR);
initializeAArch64BranchTargetsLegacyPass(PR);
@@ -867,7 +867,7 @@ void AArch64PassConfig::addPostRegAlloc() {
if (TM->getOptLevel() != CodeGenOptLevel::None && usingDefaultRegAlloc())
// Improve performance for some FP/SIMD code for A57.
- addPass(createAArch64A57FPLoadBalancing());
+ addPass(createAArch64A57FPLoadBalancingLegacyPass());
}
void AArch64PassConfig::addPreSched2() {
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