[llvm] b44d2c9 - [RISCV] Use a vector MemVT when converting store+extractelt into a vector store. (#190107)

[via llvm-commits]

Author: Craig Topper
Date: 2026-04-06T09:58:04-07:00
New Revision: b44d2c977ce2e5dbf9f227bd6ade5d85ae69a463

URL: https://github.com/llvm/llvm-project/commit/b44d2c977ce2e5dbf9f227bd6ade5d85ae69a463
DIFF: https://github.com/llvm/llvm-project/commit/b44d2c977ce2e5dbf9f227bd6ade5d85ae69a463.diff

LOG: [RISCV] Use a vector MemVT when converting store+extractelt into a vector store. (#190107)

This is needed so that `allowsMemoryAccessForAlignment` checks for
unaligned vector memory
support instead of unaligned scalar memory support when called from
`RISCVTargetLowering::expandUnalignedVPStore`

While there remove incorrect setting of the truncating store flag
on the vector instruction. And restrict the transform to simple stores
since we don't have tests for volatile or atomic.

Fixes #189037

Added: 
    llvm/test/CodeGen/RISCV/rvv/pr189037.ll

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d00b734f64509..51d8c1ef24608 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -22378,16 +22378,18 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
       SDValue Src = Val.getOperand(0);
       MVT VecVT = Src.getSimpleValueType();
       // VecVT should be scalable and memory VT should match the element type.
-      if (!Store->isIndexed() && VecVT.isScalableVector() &&
-          MemVT == VecVT.getVectorElementType()) {
+      if (!Store->isIndexed() && Store->isSimple() &&
+          VecVT.isScalableVector() && MemVT == VecVT.getVectorElementType()) {
         SDLoc DL(N);
         MVT MaskVT = getMaskTypeFor(VecVT);
+        // Create a vector memory VT so allowsMisalignedMemoryAccesses will
+        // work correctly.
+        MemVT = EVT::getVectorVT(*DAG.getContext(), MemVT, 1);
         return DAG.getStoreVP(
             Store->getChain(), DL, Src, Store->getBasePtr(), Store->getOffset(),
             DAG.getConstant(1, DL, MaskVT),
             DAG.getConstant(1, DL, Subtarget.getXLenVT()), MemVT,
-            Store->getMemOperand(), Store->getAddressingMode(),
-            Store->isTruncatingStore(), /*IsCompress*/ false);
+            Store->getMemOperand(), Store->getAddressingMode());
       }
     }
 

diff  --git a/llvm/test/CodeGen/RISCV/rvv/pr189037.ll b/llvm/test/CodeGen/RISCV/rvv/pr189037.ll
new file mode 100644
index 0000000000000..b0165d2073f13
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/pr189037.ll
@@ -0,0 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+unaligned-scalar-mem | FileCheck %s
+
+; We should produce a vse8 due to the align 1
+define void @test(ptr %out, <1 x i16> %v) {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-NEXT:    vse8.v v8, (a0)
+; CHECK-NEXT:    ret
+  %coerce.val.ii.i = extractelement <1 x i16> %v, i64 0
+  store i16 %coerce.val.ii.i, ptr %out, align 1
+  ret void
+}