[llvm] [RISCV] Improve lowering of llvm.vector.reduce.mul (PR #190628)

[Philip Reames via llvm-commits]

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@@ -1519,16 +1519,18 @@ define signext i8 @vpreduce_mul_v32i8(i8 signext %s, <32 x i8> %v, <32 x i1> %m,
 ; RV32-NEXT:    vsetvli zero, zero, e8, m2, ta, ma
 ; RV32-NEXT:    vmv.v.i v10, 1
 ; RV32-NEXT:    vmerge.vvm v8, v10, v8, v0
+; RV32-NEXT:    vsetivli zero, 16, e8, m2, ta, ma
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preames wrote:

I believe this to be a bad interaction with VL reduction, and the fact that VSETVLI insertion doesn't handle the "require any greater VL" case.  I don't believe it is blocking.  

https://github.com/llvm/llvm-project/pull/190628