[llvm] [LSV][AMDGPU] Vectorize unordered and monotonic atomic loads (PR #190152)

[Andrei Elovikov via llvm-commits]

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@@ -398,6 +398,17 @@ unsigned GCNTTIImpl::getLoadStoreVecRegBitWidth(unsigned AddrSpace) const {
   return 128;
 }
 
+bool GCNTTIImpl::isLegalToVectorizeLoad(LoadInst *LI) const {
+  // Simple (non-atomic, non-volatile) loads are always legal.
+  if (LI->isSimple())
+    return true;
+  // Allow unordered and monotonic atomic loads to be vectorized. These
+  // orderings impose no cross address synchronization constraints, so merging
+  // adjacent accesses into a wider load is safe. The hardware guarantees
+  // atomicity for naturally aligned loads up to 128 bits.
+  return !LI->isVolatile() && !isStrongerThanMonotonic(LI->getOrdering());
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eas wrote:

Does this affect other vectorizers (SLP, loop)?

https://github.com/llvm/llvm-project/pull/190152