[llvm] [AMDGPU] Add v2i32 and/or patterns for VOP3 AND_OR and OR3 operations (PR #188375)

Wooseok Lee via llvm-commits llvm-commits at lists.llvm.org
Mon Apr 6 08:55:12 PDT 2026 

https://github.com/wooseoklee updated https://github.com/llvm/llvm-project/pull/188375

>From d3e3cc4a2d5c95584631d6097f54990882e17c80 Mon Sep 17 00:00:00 2001
From: wooseoklee <wolee at amd.com>
Date: Tue, 24 Mar 2026 17:43:01 -0500
Subject: [PATCH 1/7] [AMDGPU] Add v2i32 and/or patterns for VOP3 AND_OR and
 OR3 operations

Add ThreeOp_v2i32_Pats pattern class to support v2i32 vector operations for
AND_OR_B32 and OR3_B32 instructions. The new pattern extracts individual
32-bit elements from v2i32 operands and applies the operations.
---
 llvm/lib/Target/AMDGPU/VOP3Instructions.td | 20 +++++++++++++++++++
 llvm/test/CodeGen/AMDGPU/and_or.ll         | 23 ++++++++++++++++++++++
 llvm/test/CodeGen/AMDGPU/or3.ll            | 22 +++++++++++++++++++++
 3 files changed, 65 insertions(+)

diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index 36975ab7e49e5..fe41f203f9eb2 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -955,6 +955,26 @@ def : ThreeOp_i32_Pats<and, or, V_AND_OR_B32_e64>;
 def : ThreeOp_i32_Pats<or, or, V_OR3_B32_e64>;
 def : ThreeOp_i32_Pats<xor, add, V_XAD_U32_e64>;
 
+class ThreeOp_v2i32_Pats <SDPatternOperator op1, SDPatternOperator op2, Instruction inst> : GCNPat <
+  // This matches (op2 (op1 v2i32:$src0, v2i32:$src1), v2i32:$src2) with conditions.
+  (ThreeOpFrag<op1, op2> v2i32:$src0, v2i32:$src1, v2i32:$src2),
+  (REG_SEQUENCE VReg_64,
+    (inst
+      (i32 (EXTRACT_SUBREG $src0, sub0)),
+      (i32 (EXTRACT_SUBREG $src1, sub0)),
+      (i32 (EXTRACT_SUBREG $src2, sub0))
+    ), sub0,
+    (inst
+      (i32 (EXTRACT_SUBREG $src0, sub1)),
+      (i32 (EXTRACT_SUBREG $src1, sub1)),
+      (i32 (EXTRACT_SUBREG $src2, sub1))
+    ), sub1
+  )
+>;
+
+def : ThreeOp_v2i32_Pats<and, or, V_AND_OR_B32_e64>;
+def : ThreeOp_v2i32_Pats<or, or, V_OR3_B32_e64>;
+
 let SubtargetPredicate = HasMadU32Inst, AddedComplexity = 10 in
   def : ThreeOp_i32_Pats<mul, add, V_MAD_U32_e64>;
 
diff --git a/llvm/test/CodeGen/AMDGPU/and_or.ll b/llvm/test/CodeGen/AMDGPU/and_or.ll
index 3fdf1b7e4cb2e..89c8ca210e90c 100644
--- a/llvm/test/CodeGen/AMDGPU/and_or.ll
+++ b/llvm/test/CodeGen/AMDGPU/and_or.ll
@@ -142,3 +142,26 @@ define amdgpu_ps float @and_or_vgpr_inline_const_x2(i32 %a) {
   %bc = bitcast i32 %result to float
   ret float %bc
 }
+
+define <2 x i32> @and_or_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
+; VI-LABEL: and_or_v2i32:
+; VI:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-DAG:    v_and_b32_e32 v0, v0, v2
+; VI-DAG:    v_and_b32_e32 v1, v1, v3
+; VI-CHECK-NOT: {{.}}
+; VI-DAG:    v_or_b32_e32 v0, v0, v4
+; VI-DAG:    v_or_b32_e32 v1, v1, v5
+;
+; GFX9-LABEL: and_or_v2i32:
+; GFX9:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-DAG:     v_and_or_b32 v0, v0, v2, v4
+; GFX9-DAG:     v_and_or_b32 v1, v1, v3, v5
+;
+; GFX10-LABEL: and_or_v2i32:
+; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:     v_and_or_b32 v0, v0, v2, v4
+; GFX10-DAG:     v_and_or_b32 v1, v1, v3, v5
+  %x = and <2 x i32> %a, %b
+  %result = or <2 x i32> %x, %c
+  ret <2 x i32> %result
+}
diff --git a/llvm/test/CodeGen/AMDGPU/or3.ll b/llvm/test/CodeGen/AMDGPU/or3.ll
index 0726cd587d7cf..f0f819676d77c 100644
--- a/llvm/test/CodeGen/AMDGPU/or3.ll
+++ b/llvm/test/CodeGen/AMDGPU/or3.ll
@@ -120,3 +120,25 @@ define amdgpu_ps float @or3_vgpr_const(i32 %a, i32 %b) {
   %bc = bitcast i32 %result to float
   ret float %bc
 }
+
+define <2 x i32> @or3_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
+; VI-LABEL: or3_v2i32:
+; VI:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-DAG:    v_or_b32_e32 v0, v0, v2
+; VI-DAG:    v_or_b32_e32 v1, v1, v3
+; VI-DAG:    v_or_b32_e32 v0, v0, v4
+; VI-DAG:    v_or_b32_e32 v1, v1, v5
+;
+; GFX9-LABEL: or3_v2i32:
+; GFX9:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-DAG:     v_or3_b32 v0, v0, v2, v4
+; GFX9-DAG:     v_or3_b32 v1, v1, v3, v5
+;
+; GFX10-LABEL: or3_v2i32:
+; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:     v_or3_b32 v0, v0, v2, v4
+; GFX10-DAG:     v_or3_b32 v1, v1, v3, v5
+  %x = or <2 x i32> %a, %b
+  %result = or <2 x i32> %x, %c
+  ret <2 x i32> %result
+}

>From d1cb8913983ba860a99ed10ee7aed011c7b7a1f7 Mon Sep 17 00:00:00 2001
From: wooseoklee <wolee at amd.com>
Date: Wed, 25 Mar 2026 14:36:06 -0500
Subject: [PATCH 2/7] Add more test cases

---
 llvm/test/CodeGen/AMDGPU/and_or.ll | 212 ++++++++++++++++++++++++++++-
 llvm/test/CodeGen/AMDGPU/or3.ll    | 128 +++++++++++++++++
 2 files changed, 339 insertions(+), 1 deletion(-)

diff --git a/llvm/test/CodeGen/AMDGPU/and_or.ll b/llvm/test/CodeGen/AMDGPU/and_or.ll
index 89c8ca210e90c..3d07d7b480215 100644
--- a/llvm/test/CodeGen/AMDGPU/and_or.ll
+++ b/llvm/test/CodeGen/AMDGPU/and_or.ll
@@ -145,7 +145,7 @@ define amdgpu_ps float @and_or_vgpr_inline_const_x2(i32 %a) {
 
 define <2 x i32> @and_or_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
 ; VI-LABEL: and_or_v2i32:
-; VI:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-DAG:    v_and_b32_e32 v0, v0, v2
 ; VI-DAG:    v_and_b32_e32 v1, v1, v3
 ; VI-CHECK-NOT: {{.}}
@@ -165,3 +165,213 @@ define <2 x i32> @and_or_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
   %result = or <2 x i32> %x, %c
   ret <2 x i32> %result
 }
+
+; ThreeOp instruction variant not used due to Constant Bus Limitations
+define <2 x i32> @and_or_v2i32_b(<2 x i32> inreg %a, <2 x i32> %b, <2 x i32> inreg %c) {
+; VI-LABEL: and_or_v2i32_b:
+; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-DAG:    v_and_b32_e32 v0, s16, v0
+; VI-DAG:    v_and_b32_e32 v1, s17, v1
+; VI-CHECK-NOT: {{.}}
+; VI-DAG:    v_or_b32_e32 v0, s18, v0
+; VI-DAG:    v_or_b32_e32 v1, s19, v1
+;
+; GFX9-LABEL: and_or_v2i32_b:
+; GFX9:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-DAG:    v_and_b32_e32 v0, s16, v0
+; GFX9-DAG:    v_and_b32_e32 v1, s17, v1
+; GFX9-CHECK-NOT: {{.}}
+; GFX9-DAG:    v_or_b32_e32 v0, s18, v0
+; GFX9-DAG:    v_or_b32_e32 v1, s19, v1
+;
+; GFX10-LABEL: and_or_v2i32_b:
+; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:     v_and_or_b32 v0, s{{[0-9]+}}, v0, s{{[0-9]+}}
+; GFX10-DAG:     v_and_or_b32 v1, s{{[0-9]+}}, v1, s{{[0-9]+}}
+  %x = and <2 x i32> %a, %b
+  %result = or <2 x i32> %x, %c
+  ret <2 x i32> %result
+}
+
+define <2 x i32> @and_or_v2i32_ab(<2 x i32> %a, <2 x i32> %b, <2 x i32> inreg %c) {
+; VI-LABEL: and_or_v2i32_ab:
+; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-DAG:    v_and_b32_e32 v0, v0, v2
+; VI-DAG:    v_and_b32_e32 v1, v1, v3
+; VI-CHECK-NOT: {{.}}
+; VI-DAG:    v_or_b32_e32 v0, s16, v0
+; VI-DAG:    v_or_b32_e32 v1, s17, v1
+;
+; GFX9-LABEL: and_or_v2i32_ab:
+; GFX9:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-DAG:     v_and_or_b32 v0, v0, v2, s16
+; GFX9-DAG:     v_and_or_b32 v1, v1, v3, s17
+;
+; GFX10-LABEL: and_or_v2i32_ab:
+; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:     v_and_or_b32 v0, v0, v2, s{{[0-9]+}}
+; GFX10-DAG:     v_and_or_b32 v1, v1, v3, s{{[0-9]+}}
+  %x = and <2 x i32> %a, %b
+  %result = or <2 x i32> %x, %c
+  ret <2 x i32> %result
+}
+
+define <2 x i32> @and_or_v2i32_const(<2 x i32> %a, <2 x i32> %b) {
+; VI-LABEL: and_or_v2i32_const:
+; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-DAG:    v_and_b32_e32 v0, 4, v0
+; VI-DAG:    v_and_b32_e32 v1, 16, v1
+; VI-CHECK-NOT: {{.}}
+; VI-DAG:    v_or_b32_e32 v0, v0, v2
+; VI-DAG:    v_or_b32_e32 v1, v1, v3
+;
+; GFX9-LABEL: and_or_v2i32_const:
+; GFX9:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-DAG:    v_and_or_b32 v0, v0, 4, v2
+; GFX9-DAG:    v_and_or_b32 v1, v1, 16, v3
+;
+; GFX10-LABEL: and_or_v2i32_const:
+; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:     v_and_or_b32 v0, v0, 4, v2
+; GFX10-DAG:     v_and_or_b32 v1, v1, 16, v3
+  %x = and <2 x i32> %a, <i32 4, i32 16>
+  %result = or <2 x i32> %x, %b
+  ret <2 x i32> %result
+}
+
+define <2 x i32> @and_or_v2i32_inline_const(<2 x i32> %a, <2 x i32> %b) {
+; VI-LABEL: and_or_v2i32_inline_const:
+; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-DAG:    v_and_b32_e32 v0, 0x808, v0
+; VI-DAG:    v_and_b32_e32 v1, 0x809, v1
+; VI-CHECK-NOT: {{.}}
+; VI-DAG:    v_or_b32_e32 v0, v0, v2
+; VI-DAG:    v_or_b32_e32 v1, v1, v3
+;
+; GFX9-LABEL: and_or_v2i32_inline_const:
+; GFX9:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    s_movk_i32 s4, 0x809
+; GFX9-NEXT:    v_and_or_b32 v1, v1, s4, v3
+; GFX9-NEXT:    s_movk_i32 s4, 0x808
+; GFX9-NEXT:    v_and_or_b32 v0, v0, s4, v2
+;
+; GFX10-LABEL: and_or_v2i32_inline_const:
+; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:     v_and_or_b32 v0, 0x808, v0, v2
+; GFX10-DAG:     v_and_or_b32 v1, 0x809, v1, v3
+  %x = and <2 x i32> %a, <i32 2056, i32 2057>
+  %result = or <2 x i32> %x, %b
+  ret <2 x i32> %result
+}
+
+define <2 x i32> @and_or_v2i32_inline_const_x2(<2 x i32> %a) {
+; VI-LABEL: and_or_v2i32_inline_const_x2:
+; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-DAG:    v_and_b32_e32 v0, 0x808, v0
+; VI-DAG:    v_and_b32_e32 v1, 0x809, v1
+; VI-CHECK-NOT: {{.}}
+; VI-DAG:    v_or_b32_e32 v0, 4, v0
+; VI-DAG:    v_or_b32_e32 v1, 16, v1
+;
+; GFX9-LABEL: and_or_v2i32_inline_const_x2:
+; GFX9:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-DAG:    v_and_b32_e32 v0, 0x808, v0
+; GFX9-DAG:    v_and_b32_e32 v1, 0x809, v1
+; GFX9-CHECK-NOT: {{.}}
+; GFX9-DAG:    v_or_b32_e32 v0, 4, v0
+; GFX9-DAG:    v_or_b32_e32 v1, 16, v1
+;
+; GFX10-LABEL: and_or_v2i32_inline_const_x2:
+; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:     v_and_or_b32 v0, 0x808, v0, 4
+; GFX10-DAG:     v_and_or_b32 v1, 0x809, v1, 16
+  %x = and <2 x i32> %a, <i32 2056, i32 2057>
+  %result = or <2 x i32> %x, <i32 4, i32 16>
+  ret <2 x i32> %result
+}
+
+define <2 x i32> @and_or_v2i32_inline_const_x3(<2 x i32> %a) {
+; VI-LABEL: and_or_v2i32_inline_const_x3:
+; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-DAG:    v_and_b32_e32 v0, 0x808, v0
+; VI-DAG:    v_and_b32_e32 v1, 0x809, v1
+; VI-CHECK-NOT: {{.}}
+; VI-DAG:    v_or_b32_e32 v0, 0x81, v0
+; VI-DAG:    v_or_b32_e32 v1, 16, v1
+;
+; GFX9-LABEL: and_or_v2i32_inline_const_x3:
+; GFX9:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-DAG:    v_and_b32_e32 v0, 0x808, v0
+; GFX9-DAG:    v_and_b32_e32 v1, 0x809, v1
+; GFX9-CHECK-NOT: {{.}}
+; GFX9-DAG:    v_or_b32_e32 v0, 0x81, v0
+; GFX9-DAG:    v_or_b32_e32 v1, 16, v1
+;
+; GFX10-LABEL: and_or_v2i32_inline_const_x3:
+; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_movk_i32 [[SR:s[0-9]+]], 0x808
+; GFX10-DAG:     v_and_or_b32 v0, v0, [[SR]], 0x81
+; GFX10-DAG:     v_and_or_b32 v1, 0x809, v1, 16
+  %x = and <2 x i32> %a, <i32 2056, i32 2057>
+  %result = or <2 x i32> %x, <i32 129, i32 16>
+  ret <2 x i32> %result
+}
+
+define <2 x i32> @and_or_v2i32_inline_const_x4(<2 x i32> %a) {
+; VI-LABEL: and_or_v2i32_inline_const_x4:
+; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-DAG:    v_and_b32_e32 v0, 0x808, v0
+; VI-DAG:    v_and_b32_e32 v1, 0x809, v1
+; VI-CHECK-NOT: {{.}}
+; VI-DAG:    v_or_b32_e32 v0, 0x81, v0
+; VI-DAG:    v_or_b32_e32 v1, 0x101, v1
+;
+; GFX9-LABEL: and_or_v2i32_inline_const_x4:
+; GFX9:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-DAG:    v_and_b32_e32 v0, 0x808, v0
+; GFX9-DAG:    v_and_b32_e32 v1, 0x809, v1
+; GFX9-CHECK-NOT: {{.}}
+; GFX9-DAG:    v_or_b32_e32 v0, 0x81, v0
+; GFX9-DAG:    v_or_b32_e32 v1, 0x101, v1
+;
+; GFX10-LABEL: and_or_v2i32_inline_const_x4:
+; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:     s_movk_i32 [[SR0:s[0-9]+]], 0x808
+; GFX10-DAG:     s_movk_i32 [[SR1:s[0-9]+]], 0x809
+; GFX10-CHECK-NOT: {{.}}
+; GFX10-DAG:     v_and_or_b32 v0, v0, [[SR0]], 0x81
+; GFX10-DAG:     v_and_or_b32 v1, v1, [[SR1]], 0x101
+  %x = and <2 x i32> %a, <i32 2056, i32 2057>
+  %result = or <2 x i32> %x, <i32 129, i32 257>
+  ret <2 x i32> %result
+}
+
+define <2 x i32> @and_or_v2i32_multi_use(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
+; VI-LABEL: and_or_v2i32_multi_use:
+; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-DAG:    v_and_b32_e32 v0, v0, v2
+; VI-DAG:    v_and_b32_e32 v1, v1, v3
+; VI-CHECK-NOT: {{.}}
+; VI-DAG:    v_or_b32_e32 v3, v0, v4
+; VI-DAG:    v_or_b32_e32 v2, v1, v5
+;
+; GFX9-LABEL: and_or_v2i32_multi_use:
+; GFX9:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-DAG:    v_and_b32_e32 v0, v0, v2
+; GFX9-DAG:    v_and_b32_e32 v1, v1, v3
+; GFX9-CHECK-NOT: {{.}}
+; GFX9-DAG:    v_or_b32_e32 v{{[0-9]+}}, v0, v4
+; GFX9-DAG:    v_or_b32_e32 v{{[0-9]+}}, v1, v5
+;
+; GFX10-LABEL: and_or_v2i32_multi_use:
+; GFX10:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:    v_and_b32_e32 v0, v0, v2
+; GFX10-DAG:    v_and_b32_e32 v1, v1, v3
+; GFX10-CHECK-NOT: {{.}}
+; GFX10-DAG:    v_or_b32_e32 v{{[0-9]+}}, v0, v4
+; GFX10-DAG:    v_or_b32_e32 v{{[0-9]+}}, v1, v5
+  %x = and <2 x i32> %a, %b
+  %y = or <2 x i32> %x, %c
+  %result = add <2 x i32> %x, %y
+  ret <2 x i32> %result
+}
diff --git a/llvm/test/CodeGen/AMDGPU/or3.ll b/llvm/test/CodeGen/AMDGPU/or3.ll
index f0f819676d77c..6b0815f262120 100644
--- a/llvm/test/CodeGen/AMDGPU/or3.ll
+++ b/llvm/test/CodeGen/AMDGPU/or3.ll
@@ -142,3 +142,131 @@ define <2 x i32> @or3_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
   %result = or <2 x i32> %x, %c
   ret <2 x i32> %result
 }
+
+; ThreeOp instruction variant not used due to Constant Bus Limitations
+define <2 x i32> @or3_v2i32_b(<2 x i32> inreg %a, <2 x i32> %b, <2 x i32> inreg %c) {
+; VI-LABEL: or3_v2i32_b:
+; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-DAG:    v_or_b32_e32 v0, s16, v0
+; VI-DAG:    v_or_b32_e32 v1, s17, v1
+; VI-CHECK-NOT: {{.}}
+; VI-DAG:    v_or_b32_e32 v0, s18, v0
+; VI-DAG:    v_or_b32_e32 v1, s19, v1
+;
+; GFX9-LABEL: or3_v2i32_b:
+; GFX9:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-DAG:    v_or_b32_e32 v0, s16, v0
+; GFX9-DAG:    v_or_b32_e32 v1, s17, v1
+; GFX9-CHECK-NOT: {{.}}
+; GFX9-DAG:    v_or_b32_e32 v0, s18, v0
+; GFX9-DAG:    v_or_b32_e32 v1, s19, v1
+;
+; GFX10-LABEL: or3_v2i32_b:
+; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:     v_or3_b32 v0, s{{[0-9]+}}, v0, s{{[0-9]+}}
+; GFX10-DAG:     v_or3_b32 v1, s{{[0-9]+}}, v1, s{{[0-9]+}}
+  %x = or <2 x i32> %a, %b
+  %result = or <2 x i32> %x, %c
+  ret <2 x i32> %result
+}
+
+define <2 x i32> @or3_v2i32_ab(<2 x i32> %a, <2 x i32> %b, <2 x i32> inreg %c) {
+; VI-LABEL: or3_v2i32_ab:
+; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-DAG:    v_or_b32_e32 v0, v0, v2
+; VI-DAG:    v_or_b32_e32 v1, v1, v3
+; VI-CHECK-NOT: {{.}}
+; VI-DAG:    v_or_b32_e32 v0, s16, v0
+; VI-DAG:    v_or_b32_e32 v1, s17, v1
+;
+; GFX9-LABEL: or3_v2i32_ab:
+; GFX9:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-DAG:     v_or3_b32 v0, v0, v2, s16
+; GFX9-DAG:     v_or3_b32 v1, v1, v3, s17
+;
+; GFX10-LABEL: or3_v2i32_ab:
+; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:     v_or3_b32 v0, v0, v2, s{{[0-9]+}}
+; GFX10-DAG:     v_or3_b32 v1, v1, v3, s{{[0-9]+}}
+  %x = or <2 x i32> %a, %b
+  %result = or <2 x i32> %x, %c
+  ret <2 x i32> %result
+}
+
+define <2 x i32> @or3_v2i32_const(<2 x i32> %a, <2 x i32> %b) {
+; VI-LABEL: or3_v2i32_const:
+; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-DAG:    v_or_b32_e32 v0, 4, v0
+; VI-DAG:    v_or_b32_e32 v1, 16, v1
+; VI-CHECK-NOT: {{.}}
+; VI-DAG:    v_or_b32_e32 v0, v0, v2
+; VI-DAG:    v_or_b32_e32 v1, v1, v3
+;
+; GFX9-LABEL: or3_v2i32_const:
+; GFX9:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-DAG:    v_or3_b32 v0, v0, v2, 4
+; GFX9-DAG:    v_or3_b32 v1, v1, v3, 16
+;
+; GFX10-LABEL: or3_v2i32_const:
+; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:     v_or3_b32 v0, v0, v2, 4
+; GFX10-DAG:     v_or3_b32 v1, v1, v3, 16
+  %x = or <2 x i32> %a, <i32 4, i32 16>
+  %result = or <2 x i32> %x, %b
+  ret <2 x i32> %result
+}
+
+define <2 x i32> @or3_v2i32_inline_const(<2 x i32> %a, <2 x i32> %b) {
+; VI-LABEL: or3_v2i32_inline_const:
+; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-DAG:    v_or_b32_e32 v0, 0x808, v0
+; VI-DAG:    v_or_b32_e32 v1, 0x809, v1
+; VI-CHECK-NOT: {{.}}
+; VI-DAG:    v_or_b32_e32 v0, v0, v2
+; VI-DAG:    v_or_b32_e32 v1, v1, v3
+;
+; GFX9-LABEL: or3_v2i32_inline_const:
+; GFX9:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    s_movk_i32 s4, 0x809
+; GFX9-NEXT:    v_or3_b32 v1, v1, v3, s4
+; GFX9-NEXT:    s_movk_i32 s4, 0x808
+; GFX9-NEXT:    v_or3_b32 v0, v0, v2, s4
+;
+; GFX10-LABEL: or3_v2i32_inline_const:
+; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:     v_or3_b32 v0, v0, v2, 0x808
+; GFX10-DAG:     v_or3_b32 v1, v1, v3, 0x809
+  %x = or <2 x i32> %a, <i32 2056, i32 2057>
+  %result = or <2 x i32> %x, %b
+  ret <2 x i32> %result
+}
+
+define <2 x i32> @or3_v2i32_multi_use(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
+; VI-LABEL: or3_v2i32_multi_use:
+; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-DAG:    v_or_b32_e32 v0, v0, v2
+; VI-DAG:    v_or_b32_e32 v1, v1, v3
+; VI-CHECK-NOT: {{.}}
+; VI-DAG:    v_or_b32_e32 v3, v0, v4
+; VI-DAG:    v_or_b32_e32 v2, v1, v5
+;
+; GFX9-LABEL: or3_v2i32_multi_use:
+; GFX9:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-DAG:    v_or_b32_e32 v0, v0, v2
+; GFX9-DAG:    v_or_b32_e32 v1, v1, v3
+; GFX9-CHECK-NOT: {{.}}
+; GFX9-DAG:    v_or_b32_e32 v{{[0-9]+}}, v0, v4
+; GFX9-DAG:    v_or_b32_e32 v{{[0-9]+}}, v1, v5
+;
+; GFX10-LABEL: or3_v2i32_multi_use:
+; GFX10:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:    v_or_b32_e32 v0, v0, v2
+; GFX10-DAG:    v_or_b32_e32 v1, v1, v3
+; GFX10-CHECK-NOT: {{.}}
+; GFX10-DAG:    v_or_b32_e32 v{{[0-9]+}}, v0, v4
+; GFX10-DAG:    v_or_b32_e32 v{{[0-9]+}}, v1, v5
+  %x = or <2 x i32> %a, %b
+  %y = or <2 x i32> %x, %c
+  %result = add <2 x i32> %x, %y
+  ret <2 x i32> %result
+}

>From feb16febe1c83d8eae81914f83b2ec8dc4ca08a9 Mon Sep 17 00:00:00 2001
From: wooseoklee <wolee at amd.com>
Date: Tue, 31 Mar 2026 12:59:18 -0500
Subject: [PATCH 3/7] Add missing test check and cases

---
 llvm/test/CodeGen/AMDGPU/and_or.ll | 20 ++++++++++++++++++++
 llvm/test/CodeGen/AMDGPU/or3.ll    | 21 +++++++++++++++++++++
 2 files changed, 41 insertions(+)

diff --git a/llvm/test/CodeGen/AMDGPU/and_or.ll b/llvm/test/CodeGen/AMDGPU/and_or.ll
index 3d07d7b480215..866e0fe2f25a1 100644
--- a/llvm/test/CodeGen/AMDGPU/and_or.ll
+++ b/llvm/test/CodeGen/AMDGPU/and_or.ll
@@ -216,6 +216,26 @@ define <2 x i32> @and_or_v2i32_ab(<2 x i32> %a, <2 x i32> %b, <2 x i32> inreg %c
   ret <2 x i32> %result
 }
 
+define <2 x i32> @and_or_v2i32_abc(<2 x i32> inreg %a, <2 x i32> inreg %b, <2 x i32> inreg %c) {
+; VI-LABEL: and_or_v2i32_abc:
+; VI:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    s_and_b64 s[4:5], s[16:17], s[18:19]
+; VI-NEXT:    s_or_b64 s[4:5], s[4:5], s[20:21]
+;
+; GFX9-LABEL: and_or_v2i32_abc:
+; GFX9:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    s_and_b64 s[4:5], s[16:17], s[18:19]
+; GFX9-NEXT:    s_or_b64 s[4:5], s[4:5], s[20:21]
+;
+; GFX10-LABEL: and_or_v2i32_abc:
+; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_and_b64 [[SV0:s\[[0-9]+:[0-9]+\]]], [[SV1:s\[[0-9]+:[0-9]+\]]], [[SV2:s\[[0-9]+:[0-9]+\]]]
+; GFX10-NEXT:    s_or_b64 [[SV0]], [[SV0]], [[SV3:s\[[0-9]+:[0-9]+\]]]
+  %x = and <2 x i32> %a, %b
+  %result = or <2 x i32> %x, %c
+  ret <2 x i32> %result
+}
+
 define <2 x i32> @and_or_v2i32_const(<2 x i32> %a, <2 x i32> %b) {
 ; VI-LABEL: and_or_v2i32_const:
 ; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/or3.ll b/llvm/test/CodeGen/AMDGPU/or3.ll
index 6b0815f262120..9aff206a583ee 100644
--- a/llvm/test/CodeGen/AMDGPU/or3.ll
+++ b/llvm/test/CodeGen/AMDGPU/or3.ll
@@ -126,6 +126,7 @@ define <2 x i32> @or3_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
 ; VI:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-DAG:    v_or_b32_e32 v0, v0, v2
 ; VI-DAG:    v_or_b32_e32 v1, v1, v3
+; VI-CHECK-NOT: {{.}}
 ; VI-DAG:    v_or_b32_e32 v0, v0, v4
 ; VI-DAG:    v_or_b32_e32 v1, v1, v5
 ;
@@ -193,6 +194,26 @@ define <2 x i32> @or3_v2i32_ab(<2 x i32> %a, <2 x i32> %b, <2 x i32> inreg %c) {
   ret <2 x i32> %result
 }
 
+define <2 x i32> @or3_v2i32_abc(<2 x i32> inreg %a, <2 x i32> inreg %b, <2 x i32> inreg %c) {
+; VI-LABEL: or3_v2i32_abc:
+; VI:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    s_or_b64 s[4:5], s[16:17], s[18:19]
+; VI-NEXT:    s_or_b64 s[4:5], s[4:5], s[20:21]
+;
+; GFX9-LABEL: or3_v2i32_abc:
+; GFX9:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    s_or_b64 s[4:5], s[16:17], s[18:19]
+; GFX9-NEXT:    s_or_b64 s[4:5], s[4:5], s[20:21]
+;
+; GFX10-LABEL: or3_v2i32_abc:
+; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_or_b64 [[SV0:s\[[0-9]+:[0-9]+\]]], [[SV1:s\[[0-9]+:[0-9]+\]]], [[SV2:s\[[0-9]+:[0-9]+\]]]
+; GFX10-NEXT:    s_or_b64 [[SV0]], [[SV0]], [[SV3:s\[[0-9]+:[0-9]+\]]]
+  %x = or <2 x i32> %a, %b
+  %result = or <2 x i32> %x, %c
+  ret <2 x i32> %result
+}
+
 define <2 x i32> @or3_v2i32_const(<2 x i32> %a, <2 x i32> %b) {
 ; VI-LABEL: or3_v2i32_const:
 ; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

>From 4eb8aaf3ea684e5a3e9dfa6dd9b5d4215a25a299 Mon Sep 17 00:00:00 2001
From: wooseoklee <wolee at amd.com>
Date: Tue, 31 Mar 2026 15:05:59 -0500
Subject: [PATCH 4/7] Fix confusing test name

---
 llvm/test/CodeGen/AMDGPU/and_or.ll | 8 ++++----
 llvm/test/CodeGen/AMDGPU/or3.ll    | 8 ++++----
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/and_or.ll b/llvm/test/CodeGen/AMDGPU/and_or.ll
index 866e0fe2f25a1..6b13403dc5a05 100644
--- a/llvm/test/CodeGen/AMDGPU/and_or.ll
+++ b/llvm/test/CodeGen/AMDGPU/and_or.ll
@@ -216,18 +216,18 @@ define <2 x i32> @and_or_v2i32_ab(<2 x i32> %a, <2 x i32> %b, <2 x i32> inreg %c
   ret <2 x i32> %result
 }
 
-define <2 x i32> @and_or_v2i32_abc(<2 x i32> inreg %a, <2 x i32> inreg %b, <2 x i32> inreg %c) {
-; VI-LABEL: and_or_v2i32_abc:
+define <2 x i32> @and_or_v2i32_scalar(<2 x i32> inreg %a, <2 x i32> inreg %b, <2 x i32> inreg %c) {
+; VI-LABEL: and_or_v2i32_scalar:
 ; VI:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    s_and_b64 s[4:5], s[16:17], s[18:19]
 ; VI-NEXT:    s_or_b64 s[4:5], s[4:5], s[20:21]
 ;
-; GFX9-LABEL: and_or_v2i32_abc:
+; GFX9-LABEL: and_or_v2i32_scalar:
 ; GFX9:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_and_b64 s[4:5], s[16:17], s[18:19]
 ; GFX9-NEXT:    s_or_b64 s[4:5], s[4:5], s[20:21]
 ;
-; GFX10-LABEL: and_or_v2i32_abc:
+; GFX10-LABEL: and_or_v2i32_scalar:
 ; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_and_b64 [[SV0:s\[[0-9]+:[0-9]+\]]], [[SV1:s\[[0-9]+:[0-9]+\]]], [[SV2:s\[[0-9]+:[0-9]+\]]]
 ; GFX10-NEXT:    s_or_b64 [[SV0]], [[SV0]], [[SV3:s\[[0-9]+:[0-9]+\]]]
diff --git a/llvm/test/CodeGen/AMDGPU/or3.ll b/llvm/test/CodeGen/AMDGPU/or3.ll
index 9aff206a583ee..a6e18a40dc7c8 100644
--- a/llvm/test/CodeGen/AMDGPU/or3.ll
+++ b/llvm/test/CodeGen/AMDGPU/or3.ll
@@ -194,18 +194,18 @@ define <2 x i32> @or3_v2i32_ab(<2 x i32> %a, <2 x i32> %b, <2 x i32> inreg %c) {
   ret <2 x i32> %result
 }
 
-define <2 x i32> @or3_v2i32_abc(<2 x i32> inreg %a, <2 x i32> inreg %b, <2 x i32> inreg %c) {
-; VI-LABEL: or3_v2i32_abc:
+define <2 x i32> @or3_v2i32_scalar(<2 x i32> inreg %a, <2 x i32> inreg %b, <2 x i32> inreg %c) {
+; VI-LABEL: or3_v2i32_scalar:
 ; VI:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    s_or_b64 s[4:5], s[16:17], s[18:19]
 ; VI-NEXT:    s_or_b64 s[4:5], s[4:5], s[20:21]
 ;
-; GFX9-LABEL: or3_v2i32_abc:
+; GFX9-LABEL: or3_v2i32_scalar:
 ; GFX9:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_or_b64 s[4:5], s[16:17], s[18:19]
 ; GFX9-NEXT:    s_or_b64 s[4:5], s[4:5], s[20:21]
 ;
-; GFX10-LABEL: or3_v2i32_abc:
+; GFX10-LABEL: or3_v2i32_scalar:
 ; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_or_b64 [[SV0:s\[[0-9]+:[0-9]+\]]], [[SV1:s\[[0-9]+:[0-9]+\]]], [[SV2:s\[[0-9]+:[0-9]+\]]]
 ; GFX10-NEXT:    s_or_b64 [[SV0]], [[SV0]], [[SV3:s\[[0-9]+:[0-9]+\]]]

>From 6b397c0325144972259e560bb9264f8d69c0f1d7 Mon Sep 17 00:00:00 2001
From: wooseoklee <wolee at amd.com>
Date: Wed, 1 Apr 2026 10:27:11 -0500
Subject: [PATCH 5/7] Adjust tests to use scalar calling convention

---
 llvm/test/CodeGen/AMDGPU/and_or.ll | 26 +++++++++++++-------------
 llvm/test/CodeGen/AMDGPU/or3.ll    | 26 +++++++++++++-------------
 2 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/and_or.ll b/llvm/test/CodeGen/AMDGPU/and_or.ll
index 6b13403dc5a05..bbafaf5d55308 100644
--- a/llvm/test/CodeGen/AMDGPU/and_or.ll
+++ b/llvm/test/CodeGen/AMDGPU/and_or.ll
@@ -216,21 +216,21 @@ define <2 x i32> @and_or_v2i32_ab(<2 x i32> %a, <2 x i32> %b, <2 x i32> inreg %c
   ret <2 x i32> %result
 }
 
-define <2 x i32> @and_or_v2i32_scalar(<2 x i32> inreg %a, <2 x i32> inreg %b, <2 x i32> inreg %c) {
-; VI-LABEL: and_or_v2i32_scalar:
-; VI:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT:    s_and_b64 s[4:5], s[16:17], s[18:19]
-; VI-NEXT:    s_or_b64 s[4:5], s[4:5], s[20:21]
+define amdgpu_ps <2 x i32> @s_and_or_v2i32(<2 x i32> inreg %a, <2 x i32> inreg %b, <2 x i32> inreg %c) {
+; VI-LABEL: s_and_or_v2i32:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_and_b64 s[0:1], s[2:3], s[4:5]
+; VI-NEXT:    s_or_b64 s[0:1], s[0:1], s[6:7]
 ;
-; GFX9-LABEL: and_or_v2i32_scalar:
-; GFX9:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    s_and_b64 s[4:5], s[16:17], s[18:19]
-; GFX9-NEXT:    s_or_b64 s[4:5], s[4:5], s[20:21]
+; GFX9-LABEL: s_and_or_v2i32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_and_b64 s[0:1], s[2:3], s[4:5]
+; GFX9-NEXT:    s_or_b64 s[0:1], s[0:1], s[6:7]
 ;
-; GFX10-LABEL: and_or_v2i32_scalar:
-; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_and_b64 [[SV0:s\[[0-9]+:[0-9]+\]]], [[SV1:s\[[0-9]+:[0-9]+\]]], [[SV2:s\[[0-9]+:[0-9]+\]]]
-; GFX10-NEXT:    s_or_b64 [[SV0]], [[SV0]], [[SV3:s\[[0-9]+:[0-9]+\]]]
+; GFX10-LABEL: s_and_or_v2i32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_and_b64 s[0:1], s[2:3], s[4:5]
+; GFX10-NEXT:    s_or_b64 s[0:1], s[0:1], s[6:7]
   %x = and <2 x i32> %a, %b
   %result = or <2 x i32> %x, %c
   ret <2 x i32> %result
diff --git a/llvm/test/CodeGen/AMDGPU/or3.ll b/llvm/test/CodeGen/AMDGPU/or3.ll
index a6e18a40dc7c8..373468c5f318f 100644
--- a/llvm/test/CodeGen/AMDGPU/or3.ll
+++ b/llvm/test/CodeGen/AMDGPU/or3.ll
@@ -194,21 +194,21 @@ define <2 x i32> @or3_v2i32_ab(<2 x i32> %a, <2 x i32> %b, <2 x i32> inreg %c) {
   ret <2 x i32> %result
 }
 
-define <2 x i32> @or3_v2i32_scalar(<2 x i32> inreg %a, <2 x i32> inreg %b, <2 x i32> inreg %c) {
-; VI-LABEL: or3_v2i32_scalar:
-; VI:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT:    s_or_b64 s[4:5], s[16:17], s[18:19]
-; VI-NEXT:    s_or_b64 s[4:5], s[4:5], s[20:21]
+define amdgpu_ps <2 x i32> @s_or3_v2i32(<2 x i32> inreg %a, <2 x i32> inreg %b, <2 x i32> inreg %c) {
+; VI-LABEL: s_or3_v2i32:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_or_b64 s[0:1], s[2:3], s[4:5]
+; VI-NEXT:    s_or_b64 s[0:1], s[0:1], s[6:7]
 ;
-; GFX9-LABEL: or3_v2i32_scalar:
-; GFX9:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    s_or_b64 s[4:5], s[16:17], s[18:19]
-; GFX9-NEXT:    s_or_b64 s[4:5], s[4:5], s[20:21]
+; GFX9-LABEL: s_or3_v2i32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_or_b64 s[0:1], s[2:3], s[4:5]
+; GFX9-NEXT:    s_or_b64 s[0:1], s[0:1], s[6:7]
 ;
-; GFX10-LABEL: or3_v2i32_scalar:
-; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_or_b64 [[SV0:s\[[0-9]+:[0-9]+\]]], [[SV1:s\[[0-9]+:[0-9]+\]]], [[SV2:s\[[0-9]+:[0-9]+\]]]
-; GFX10-NEXT:    s_or_b64 [[SV0]], [[SV0]], [[SV3:s\[[0-9]+:[0-9]+\]]]
+; GFX10-LABEL: s_or3_v2i32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_or_b64 s[0:1], s[2:3], s[4:5]
+; GFX10-NEXT:    s_or_b64 s[0:1], s[0:1], s[6:7]
   %x = or <2 x i32> %a, %b
   %result = or <2 x i32> %x, %c
   ret <2 x i32> %result

>From edf4385c2813dc71b002e35cb2c5715b5437a313 Mon Sep 17 00:00:00 2001
From: wooseoklee <wolee at amd.com>
Date: Mon, 6 Apr 2026 08:31:53 -0500
Subject: [PATCH 6/7] Use amdgpu_ps calling convetions for all tests and use
 update_llc_test_checks.py to update the test checks

---
 llvm/test/CodeGen/AMDGPU/and_or.ll | 476 +++++++++++++++++------------
 llvm/test/CodeGen/AMDGPU/or3.ll    | 302 ++++++++++--------
 2 files changed, 453 insertions(+), 325 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/and_or.ll b/llvm/test/CodeGen/AMDGPU/and_or.ll
index bbafaf5d55308..a2d46187fdf74 100644
--- a/llvm/test/CodeGen/AMDGPU/and_or.ll
+++ b/llvm/test/CodeGen/AMDGPU/and_or.ll
@@ -143,255 +143,329 @@ define amdgpu_ps float @and_or_vgpr_inline_const_x2(i32 %a) {
   ret float %bc
 }
 
-define <2 x i32> @and_or_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
-; VI-LABEL: and_or_v2i32:
-; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-DAG:    v_and_b32_e32 v0, v0, v2
-; VI-DAG:    v_and_b32_e32 v1, v1, v3
-; VI-CHECK-NOT: {{.}}
-; VI-DAG:    v_or_b32_e32 v0, v0, v4
-; VI-DAG:    v_or_b32_e32 v1, v1, v5
-;
-; GFX9-LABEL: and_or_v2i32:
-; GFX9:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-DAG:     v_and_or_b32 v0, v0, v2, v4
-; GFX9-DAG:     v_and_or_b32 v1, v1, v3, v5
-;
-; GFX10-LABEL: and_or_v2i32:
-; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-DAG:     v_and_or_b32 v0, v0, v2, v4
-; GFX10-DAG:     v_and_or_b32 v1, v1, v3, v5
+define amdgpu_ps <2 x i32> @v_and_or_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
+; VI-LABEL: v_and_or_v2i32:
+; VI:       ; %bb.0:
+; VI-NEXT:    v_and_b32_e32 v1, v1, v3
+; VI-NEXT:    v_and_b32_e32 v0, v0, v2
+; VI-NEXT:    v_or_b32_e32 v1, v1, v5
+; VI-NEXT:    v_or_b32_e32 v0, v0, v4
+; VI-NEXT:    v_readfirstlane_b32 s0, v0
+; VI-NEXT:    v_readfirstlane_b32 s1, v1
+; VI-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: v_and_or_v2i32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_and_or_b32 v1, v1, v3, v5
+; GFX9-NEXT:    v_and_or_b32 v0, v0, v2, v4
+; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: v_and_or_v2i32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_and_or_b32 v0, v0, v2, v4
+; GFX10-NEXT:    v_and_or_b32 v1, v1, v3, v5
+; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10-NEXT:    ; return to shader part epilog
   %x = and <2 x i32> %a, %b
   %result = or <2 x i32> %x, %c
   ret <2 x i32> %result
 }
 
 ; ThreeOp instruction variant not used due to Constant Bus Limitations
-define <2 x i32> @and_or_v2i32_b(<2 x i32> inreg %a, <2 x i32> %b, <2 x i32> inreg %c) {
-; VI-LABEL: and_or_v2i32_b:
-; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-DAG:    v_and_b32_e32 v0, s16, v0
-; VI-DAG:    v_and_b32_e32 v1, s17, v1
-; VI-CHECK-NOT: {{.}}
-; VI-DAG:    v_or_b32_e32 v0, s18, v0
-; VI-DAG:    v_or_b32_e32 v1, s19, v1
-;
-; GFX9-LABEL: and_or_v2i32_b:
-; GFX9:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-DAG:    v_and_b32_e32 v0, s16, v0
-; GFX9-DAG:    v_and_b32_e32 v1, s17, v1
-; GFX9-CHECK-NOT: {{.}}
-; GFX9-DAG:    v_or_b32_e32 v0, s18, v0
-; GFX9-DAG:    v_or_b32_e32 v1, s19, v1
-;
-; GFX10-LABEL: and_or_v2i32_b:
-; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-DAG:     v_and_or_b32 v0, s{{[0-9]+}}, v0, s{{[0-9]+}}
-; GFX10-DAG:     v_and_or_b32 v1, s{{[0-9]+}}, v1, s{{[0-9]+}}
-  %x = and <2 x i32> %a, %b
-  %result = or <2 x i32> %x, %c
-  ret <2 x i32> %result
-}
-
-define <2 x i32> @and_or_v2i32_ab(<2 x i32> %a, <2 x i32> %b, <2 x i32> inreg %c) {
-; VI-LABEL: and_or_v2i32_ab:
-; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-DAG:    v_and_b32_e32 v0, v0, v2
-; VI-DAG:    v_and_b32_e32 v1, v1, v3
-; VI-CHECK-NOT: {{.}}
-; VI-DAG:    v_or_b32_e32 v0, s16, v0
-; VI-DAG:    v_or_b32_e32 v1, s17, v1
-;
-; GFX9-LABEL: and_or_v2i32_ab:
-; GFX9:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-DAG:     v_and_or_b32 v0, v0, v2, s16
-; GFX9-DAG:     v_and_or_b32 v1, v1, v3, s17
-;
-; GFX10-LABEL: and_or_v2i32_ab:
-; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-DAG:     v_and_or_b32 v0, v0, v2, s{{[0-9]+}}
-; GFX10-DAG:     v_and_or_b32 v1, v1, v3, s{{[0-9]+}}
+define amdgpu_ps <2 x i32> @v_and_or_v2i32_b(<2 x i32> inreg %a, <2 x i32> %b, <2 x i32> inreg %c) {
+; VI-LABEL: v_and_or_v2i32_b:
+; VI:       ; %bb.0:
+; VI-NEXT:    v_and_b32_e32 v1, s3, v1
+; VI-NEXT:    v_and_b32_e32 v0, s2, v0
+; VI-NEXT:    v_or_b32_e32 v1, s5, v1
+; VI-NEXT:    v_or_b32_e32 v0, s4, v0
+; VI-NEXT:    v_readfirstlane_b32 s0, v0
+; VI-NEXT:    v_readfirstlane_b32 s1, v1
+; VI-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: v_and_or_v2i32_b:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_and_b32_e32 v1, s3, v1
+; GFX9-NEXT:    v_and_b32_e32 v0, s2, v0
+; GFX9-NEXT:    v_or_b32_e32 v1, s5, v1
+; GFX9-NEXT:    v_or_b32_e32 v0, s4, v0
+; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: v_and_or_v2i32_b:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_and_or_b32 v0, s2, v0, s4
+; GFX10-NEXT:    v_and_or_b32 v1, s3, v1, s5
+; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10-NEXT:    ; return to shader part epilog
   %x = and <2 x i32> %a, %b
   %result = or <2 x i32> %x, %c
   ret <2 x i32> %result
 }
 
-define amdgpu_ps <2 x i32> @s_and_or_v2i32(<2 x i32> inreg %a, <2 x i32> inreg %b, <2 x i32> inreg %c) {
-; VI-LABEL: s_and_or_v2i32:
+define amdgpu_ps <2 x i32> @v_and_or_v2i32_ab(<2 x i32> %a, <2 x i32> %b, <2 x i32> inreg %c) {
+; VI-LABEL: v_and_or_v2i32_ab:
 ; VI:       ; %bb.0:
-; VI-NEXT:    s_and_b64 s[0:1], s[2:3], s[4:5]
-; VI-NEXT:    s_or_b64 s[0:1], s[0:1], s[6:7]
+; VI-NEXT:    v_and_b32_e32 v1, v1, v3
+; VI-NEXT:    v_and_b32_e32 v0, v0, v2
+; VI-NEXT:    v_or_b32_e32 v1, s3, v1
+; VI-NEXT:    v_or_b32_e32 v0, s2, v0
+; VI-NEXT:    v_readfirstlane_b32 s0, v0
+; VI-NEXT:    v_readfirstlane_b32 s1, v1
+; VI-NEXT:    ; return to shader part epilog
 ;
-; GFX9-LABEL: s_and_or_v2i32:
+; GFX9-LABEL: v_and_or_v2i32_ab:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_and_b64 s[0:1], s[2:3], s[4:5]
-; GFX9-NEXT:    s_or_b64 s[0:1], s[0:1], s[6:7]
+; GFX9-NEXT:    v_and_or_b32 v1, v1, v3, s3
+; GFX9-NEXT:    v_and_or_b32 v0, v0, v2, s2
+; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_and_or_v2i32:
+; GFX10-LABEL: v_and_or_v2i32_ab:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_and_b64 s[0:1], s[2:3], s[4:5]
-; GFX10-NEXT:    s_or_b64 s[0:1], s[0:1], s[6:7]
+; GFX10-NEXT:    v_and_or_b32 v0, v0, v2, s2
+; GFX10-NEXT:    v_and_or_b32 v1, v1, v3, s3
+; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10-NEXT:    ; return to shader part epilog
   %x = and <2 x i32> %a, %b
   %result = or <2 x i32> %x, %c
   ret <2 x i32> %result
 }
 
-define <2 x i32> @and_or_v2i32_const(<2 x i32> %a, <2 x i32> %b) {
-; VI-LABEL: and_or_v2i32_const:
-; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-DAG:    v_and_b32_e32 v0, 4, v0
-; VI-DAG:    v_and_b32_e32 v1, 16, v1
-; VI-CHECK-NOT: {{.}}
-; VI-DAG:    v_or_b32_e32 v0, v0, v2
-; VI-DAG:    v_or_b32_e32 v1, v1, v3
-;
-; GFX9-LABEL: and_or_v2i32_const:
-; GFX9:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-DAG:    v_and_or_b32 v0, v0, 4, v2
-; GFX9-DAG:    v_and_or_b32 v1, v1, 16, v3
-;
-; GFX10-LABEL: and_or_v2i32_const:
-; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-DAG:     v_and_or_b32 v0, v0, 4, v2
-; GFX10-DAG:     v_and_or_b32 v1, v1, 16, v3
+define amdgpu_ps <2 x i32> @v_and_or_v2i32_const(<2 x i32> %a, <2 x i32> %b) {
+; VI-LABEL: v_and_or_v2i32_const:
+; VI:       ; %bb.0:
+; VI-NEXT:    v_and_b32_e32 v1, 16, v1
+; VI-NEXT:    v_and_b32_e32 v0, 4, v0
+; VI-NEXT:    v_or_b32_e32 v1, v1, v3
+; VI-NEXT:    v_or_b32_e32 v0, v0, v2
+; VI-NEXT:    v_readfirstlane_b32 s0, v0
+; VI-NEXT:    v_readfirstlane_b32 s1, v1
+; VI-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: v_and_or_v2i32_const:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_and_or_b32 v1, v1, 16, v3
+; GFX9-NEXT:    v_and_or_b32 v0, v0, 4, v2
+; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: v_and_or_v2i32_const:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_and_or_b32 v0, v0, 4, v2
+; GFX10-NEXT:    v_and_or_b32 v1, v1, 16, v3
+; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10-NEXT:    ; return to shader part epilog
   %x = and <2 x i32> %a, <i32 4, i32 16>
   %result = or <2 x i32> %x, %b
   ret <2 x i32> %result
 }
 
-define <2 x i32> @and_or_v2i32_inline_const(<2 x i32> %a, <2 x i32> %b) {
-; VI-LABEL: and_or_v2i32_inline_const:
-; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-DAG:    v_and_b32_e32 v0, 0x808, v0
-; VI-DAG:    v_and_b32_e32 v1, 0x809, v1
-; VI-CHECK-NOT: {{.}}
-; VI-DAG:    v_or_b32_e32 v0, v0, v2
-; VI-DAG:    v_or_b32_e32 v1, v1, v3
-;
-; GFX9-LABEL: and_or_v2i32_inline_const:
-; GFX9:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    s_movk_i32 s4, 0x809
-; GFX9-NEXT:    v_and_or_b32 v1, v1, s4, v3
-; GFX9-NEXT:    s_movk_i32 s4, 0x808
-; GFX9-NEXT:    v_and_or_b32 v0, v0, s4, v2
-;
-; GFX10-LABEL: and_or_v2i32_inline_const:
-; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-DAG:     v_and_or_b32 v0, 0x808, v0, v2
-; GFX10-DAG:     v_and_or_b32 v1, 0x809, v1, v3
+define amdgpu_ps <2 x i32> @v_and_or_v2i32_inline_const(<2 x i32> %a, <2 x i32> %b) {
+; VI-LABEL: v_and_or_v2i32_inline_const:
+; VI:       ; %bb.0:
+; VI-NEXT:    v_and_b32_e32 v1, 0x809, v1
+; VI-NEXT:    v_and_b32_e32 v0, 0x808, v0
+; VI-NEXT:    v_or_b32_e32 v1, v1, v3
+; VI-NEXT:    v_or_b32_e32 v0, v0, v2
+; VI-NEXT:    v_readfirstlane_b32 s0, v0
+; VI-NEXT:    v_readfirstlane_b32 s1, v1
+; VI-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: v_and_or_v2i32_inline_const:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_movk_i32 s0, 0x809
+; GFX9-NEXT:    v_and_or_b32 v1, v1, s0, v3
+; GFX9-NEXT:    s_movk_i32 s0, 0x808
+; GFX9-NEXT:    v_and_or_b32 v0, v0, s0, v2
+; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: v_and_or_v2i32_inline_const:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_and_or_b32 v0, 0x808, v0, v2
+; GFX10-NEXT:    v_and_or_b32 v1, 0x809, v1, v3
+; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10-NEXT:    ; return to shader part epilog
   %x = and <2 x i32> %a, <i32 2056, i32 2057>
   %result = or <2 x i32> %x, %b
   ret <2 x i32> %result
 }
 
-define <2 x i32> @and_or_v2i32_inline_const_x2(<2 x i32> %a) {
-; VI-LABEL: and_or_v2i32_inline_const_x2:
-; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-DAG:    v_and_b32_e32 v0, 0x808, v0
-; VI-DAG:    v_and_b32_e32 v1, 0x809, v1
-; VI-CHECK-NOT: {{.}}
-; VI-DAG:    v_or_b32_e32 v0, 4, v0
-; VI-DAG:    v_or_b32_e32 v1, 16, v1
-;
-; GFX9-LABEL: and_or_v2i32_inline_const_x2:
-; GFX9:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-DAG:    v_and_b32_e32 v0, 0x808, v0
-; GFX9-DAG:    v_and_b32_e32 v1, 0x809, v1
-; GFX9-CHECK-NOT: {{.}}
-; GFX9-DAG:    v_or_b32_e32 v0, 4, v0
-; GFX9-DAG:    v_or_b32_e32 v1, 16, v1
-;
-; GFX10-LABEL: and_or_v2i32_inline_const_x2:
-; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-DAG:     v_and_or_b32 v0, 0x808, v0, 4
-; GFX10-DAG:     v_and_or_b32 v1, 0x809, v1, 16
+define amdgpu_ps <2 x i32> @v_and_or_v2i32_inline_const_x2(<2 x i32> %a) {
+; VI-LABEL: v_and_or_v2i32_inline_const_x2:
+; VI:       ; %bb.0:
+; VI-NEXT:    v_and_b32_e32 v1, 0x809, v1
+; VI-NEXT:    v_and_b32_e32 v0, 0x808, v0
+; VI-NEXT:    v_or_b32_e32 v1, 16, v1
+; VI-NEXT:    v_or_b32_e32 v0, 4, v0
+; VI-NEXT:    v_readfirstlane_b32 s0, v0
+; VI-NEXT:    v_readfirstlane_b32 s1, v1
+; VI-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: v_and_or_v2i32_inline_const_x2:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_and_b32_e32 v1, 0x809, v1
+; GFX9-NEXT:    v_and_b32_e32 v0, 0x808, v0
+; GFX9-NEXT:    v_or_b32_e32 v1, 16, v1
+; GFX9-NEXT:    v_or_b32_e32 v0, 4, v0
+; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: v_and_or_v2i32_inline_const_x2:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_and_or_b32 v0, 0x808, v0, 4
+; GFX10-NEXT:    v_and_or_b32 v1, 0x809, v1, 16
+; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10-NEXT:    ; return to shader part epilog
   %x = and <2 x i32> %a, <i32 2056, i32 2057>
   %result = or <2 x i32> %x, <i32 4, i32 16>
   ret <2 x i32> %result
 }
 
-define <2 x i32> @and_or_v2i32_inline_const_x3(<2 x i32> %a) {
-; VI-LABEL: and_or_v2i32_inline_const_x3:
-; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-DAG:    v_and_b32_e32 v0, 0x808, v0
-; VI-DAG:    v_and_b32_e32 v1, 0x809, v1
-; VI-CHECK-NOT: {{.}}
-; VI-DAG:    v_or_b32_e32 v0, 0x81, v0
-; VI-DAG:    v_or_b32_e32 v1, 16, v1
-;
-; GFX9-LABEL: and_or_v2i32_inline_const_x3:
-; GFX9:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-DAG:    v_and_b32_e32 v0, 0x808, v0
-; GFX9-DAG:    v_and_b32_e32 v1, 0x809, v1
-; GFX9-CHECK-NOT: {{.}}
-; GFX9-DAG:    v_or_b32_e32 v0, 0x81, v0
-; GFX9-DAG:    v_or_b32_e32 v1, 16, v1
-;
-; GFX10-LABEL: and_or_v2i32_inline_const_x3:
-; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    s_movk_i32 [[SR:s[0-9]+]], 0x808
-; GFX10-DAG:     v_and_or_b32 v0, v0, [[SR]], 0x81
-; GFX10-DAG:     v_and_or_b32 v1, 0x809, v1, 16
+define amdgpu_ps <2 x i32> @v_and_or_v2i32_inline_const_x3(<2 x i32> %a) {
+; VI-LABEL: v_and_or_v2i32_inline_const_x3:
+; VI:       ; %bb.0:
+; VI-NEXT:    v_and_b32_e32 v1, 0x809, v1
+; VI-NEXT:    v_and_b32_e32 v0, 0x808, v0
+; VI-NEXT:    v_or_b32_e32 v1, 16, v1
+; VI-NEXT:    v_or_b32_e32 v0, 0x81, v0
+; VI-NEXT:    v_readfirstlane_b32 s0, v0
+; VI-NEXT:    v_readfirstlane_b32 s1, v1
+; VI-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: v_and_or_v2i32_inline_const_x3:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_and_b32_e32 v1, 0x809, v1
+; GFX9-NEXT:    v_and_b32_e32 v0, 0x808, v0
+; GFX9-NEXT:    v_or_b32_e32 v1, 16, v1
+; GFX9-NEXT:    v_or_b32_e32 v0, 0x81, v0
+; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: v_and_or_v2i32_inline_const_x3:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_movk_i32 s0, 0x808
+; GFX10-NEXT:    v_and_or_b32 v1, 0x809, v1, 16
+; GFX10-NEXT:    v_and_or_b32 v0, v0, s0, 0x81
+; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10-NEXT:    ; return to shader part epilog
   %x = and <2 x i32> %a, <i32 2056, i32 2057>
   %result = or <2 x i32> %x, <i32 129, i32 16>
   ret <2 x i32> %result
 }
 
-define <2 x i32> @and_or_v2i32_inline_const_x4(<2 x i32> %a) {
-; VI-LABEL: and_or_v2i32_inline_const_x4:
-; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-DAG:    v_and_b32_e32 v0, 0x808, v0
-; VI-DAG:    v_and_b32_e32 v1, 0x809, v1
-; VI-CHECK-NOT: {{.}}
-; VI-DAG:    v_or_b32_e32 v0, 0x81, v0
-; VI-DAG:    v_or_b32_e32 v1, 0x101, v1
-;
-; GFX9-LABEL: and_or_v2i32_inline_const_x4:
-; GFX9:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-DAG:    v_and_b32_e32 v0, 0x808, v0
-; GFX9-DAG:    v_and_b32_e32 v1, 0x809, v1
-; GFX9-CHECK-NOT: {{.}}
-; GFX9-DAG:    v_or_b32_e32 v0, 0x81, v0
-; GFX9-DAG:    v_or_b32_e32 v1, 0x101, v1
-;
-; GFX10-LABEL: and_or_v2i32_inline_const_x4:
-; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-DAG:     s_movk_i32 [[SR0:s[0-9]+]], 0x808
-; GFX10-DAG:     s_movk_i32 [[SR1:s[0-9]+]], 0x809
-; GFX10-CHECK-NOT: {{.}}
-; GFX10-DAG:     v_and_or_b32 v0, v0, [[SR0]], 0x81
-; GFX10-DAG:     v_and_or_b32 v1, v1, [[SR1]], 0x101
+define amdgpu_ps <2 x i32> @v_and_or_v2i32_inline_const_x4(<2 x i32> %a) {
+; VI-LABEL: v_and_or_v2i32_inline_const_x4:
+; VI:       ; %bb.0:
+; VI-NEXT:    v_and_b32_e32 v1, 0x809, v1
+; VI-NEXT:    v_and_b32_e32 v0, 0x808, v0
+; VI-NEXT:    v_or_b32_e32 v1, 0x101, v1
+; VI-NEXT:    v_or_b32_e32 v0, 0x81, v0
+; VI-NEXT:    v_readfirstlane_b32 s0, v0
+; VI-NEXT:    v_readfirstlane_b32 s1, v1
+; VI-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: v_and_or_v2i32_inline_const_x4:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_and_b32_e32 v1, 0x809, v1
+; GFX9-NEXT:    v_and_b32_e32 v0, 0x808, v0
+; GFX9-NEXT:    v_or_b32_e32 v1, 0x101, v1
+; GFX9-NEXT:    v_or_b32_e32 v0, 0x81, v0
+; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: v_and_or_v2i32_inline_const_x4:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_movk_i32 s0, 0x808
+; GFX10-NEXT:    s_movk_i32 s1, 0x809
+; GFX10-NEXT:    v_and_or_b32 v0, v0, s0, 0x81
+; GFX10-NEXT:    v_and_or_b32 v1, v1, s1, 0x101
+; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10-NEXT:    ; return to shader part epilog
   %x = and <2 x i32> %a, <i32 2056, i32 2057>
   %result = or <2 x i32> %x, <i32 129, i32 257>
   ret <2 x i32> %result
 }
 
-define <2 x i32> @and_or_v2i32_multi_use(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
-; VI-LABEL: and_or_v2i32_multi_use:
-; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-DAG:    v_and_b32_e32 v0, v0, v2
-; VI-DAG:    v_and_b32_e32 v1, v1, v3
-; VI-CHECK-NOT: {{.}}
-; VI-DAG:    v_or_b32_e32 v3, v0, v4
-; VI-DAG:    v_or_b32_e32 v2, v1, v5
-;
-; GFX9-LABEL: and_or_v2i32_multi_use:
-; GFX9:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-DAG:    v_and_b32_e32 v0, v0, v2
-; GFX9-DAG:    v_and_b32_e32 v1, v1, v3
-; GFX9-CHECK-NOT: {{.}}
-; GFX9-DAG:    v_or_b32_e32 v{{[0-9]+}}, v0, v4
-; GFX9-DAG:    v_or_b32_e32 v{{[0-9]+}}, v1, v5
-;
-; GFX10-LABEL: and_or_v2i32_multi_use:
-; GFX10:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-DAG:    v_and_b32_e32 v0, v0, v2
-; GFX10-DAG:    v_and_b32_e32 v1, v1, v3
-; GFX10-CHECK-NOT: {{.}}
-; GFX10-DAG:    v_or_b32_e32 v{{[0-9]+}}, v0, v4
-; GFX10-DAG:    v_or_b32_e32 v{{[0-9]+}}, v1, v5
+define amdgpu_ps <2 x i32> @v_and_or_v2i32_multi_use(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
+; VI-LABEL: v_and_or_v2i32_multi_use:
+; VI:       ; %bb.0:
+; VI-NEXT:    v_and_b32_e32 v1, v1, v3
+; VI-NEXT:    v_and_b32_e32 v0, v0, v2
+; VI-NEXT:    v_or_b32_e32 v2, v1, v5
+; VI-NEXT:    v_or_b32_e32 v3, v0, v4
+; VI-NEXT:    v_add_u32_e32 v1, vcc, v1, v2
+; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v3
+; VI-NEXT:    v_readfirstlane_b32 s0, v0
+; VI-NEXT:    v_readfirstlane_b32 s1, v1
+; VI-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: v_and_or_v2i32_multi_use:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_and_b32_e32 v1, v1, v3
+; GFX9-NEXT:    v_and_b32_e32 v0, v0, v2
+; GFX9-NEXT:    v_or_b32_e32 v2, v1, v5
+; GFX9-NEXT:    v_or_b32_e32 v3, v0, v4
+; GFX9-NEXT:    v_add_u32_e32 v1, v1, v2
+; GFX9-NEXT:    v_add_u32_e32 v0, v0, v3
+; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: v_and_or_v2i32_multi_use:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_and_b32_e32 v0, v0, v2
+; GFX10-NEXT:    v_and_b32_e32 v1, v1, v3
+; GFX10-NEXT:    v_or_b32_e32 v2, v0, v4
+; GFX10-NEXT:    v_or_b32_e32 v3, v1, v5
+; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v2
+; GFX10-NEXT:    v_add_nc_u32_e32 v1, v1, v3
+; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10-NEXT:    ; return to shader part epilog
   %x = and <2 x i32> %a, %b
   %y = or <2 x i32> %x, %c
   %result = add <2 x i32> %x, %y
   ret <2 x i32> %result
 }
+
+define amdgpu_ps <2 x i32> @s_and_or_v2i32(<2 x i32> inreg %a, <2 x i32> inreg %b, <2 x i32> inreg %c) {
+; VI-LABEL: s_and_or_v2i32:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_and_b64 s[0:1], s[2:3], s[4:5]
+; VI-NEXT:    s_or_b64 s[0:1], s[0:1], s[6:7]
+; VI-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: s_and_or_v2i32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_and_b64 s[0:1], s[2:3], s[4:5]
+; GFX9-NEXT:    s_or_b64 s[0:1], s[0:1], s[6:7]
+; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: s_and_or_v2i32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_and_b64 s[0:1], s[2:3], s[4:5]
+; GFX10-NEXT:    s_or_b64 s[0:1], s[0:1], s[6:7]
+; GFX10-NEXT:    ; return to shader part epilog
+  %x = and <2 x i32> %a, %b
+  %result = or <2 x i32> %x, %c
+  ret <2 x i32> %result
+}
diff --git a/llvm/test/CodeGen/AMDGPU/or3.ll b/llvm/test/CodeGen/AMDGPU/or3.ll
index 373468c5f318f..2973ec67b78c4 100644
--- a/llvm/test/CodeGen/AMDGPU/or3.ll
+++ b/llvm/test/CodeGen/AMDGPU/or3.ll
@@ -121,173 +121,227 @@ define amdgpu_ps float @or3_vgpr_const(i32 %a, i32 %b) {
   ret float %bc
 }
 
-define <2 x i32> @or3_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
-; VI-LABEL: or3_v2i32:
-; VI:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-DAG:    v_or_b32_e32 v0, v0, v2
-; VI-DAG:    v_or_b32_e32 v1, v1, v3
-; VI-CHECK-NOT: {{.}}
-; VI-DAG:    v_or_b32_e32 v0, v0, v4
-; VI-DAG:    v_or_b32_e32 v1, v1, v5
+define amdgpu_ps <2 x i32> @v_or3_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
+; VI-LABEL: v_or3_v2i32:
+; VI:       ; %bb.0:
+; VI-NEXT:    v_or_b32_e32 v1, v1, v3
+; VI-NEXT:    v_or_b32_e32 v0, v0, v2
+; VI-NEXT:    v_or_b32_e32 v1, v1, v5
+; VI-NEXT:    v_or_b32_e32 v0, v0, v4
+; VI-NEXT:    v_readfirstlane_b32 s0, v0
+; VI-NEXT:    v_readfirstlane_b32 s1, v1
+; VI-NEXT:    ; return to shader part epilog
 ;
-; GFX9-LABEL: or3_v2i32:
-; GFX9:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-DAG:     v_or3_b32 v0, v0, v2, v4
-; GFX9-DAG:     v_or3_b32 v1, v1, v3, v5
+; GFX9-LABEL: v_or3_v2i32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_or3_b32 v1, v1, v3, v5
+; GFX9-NEXT:    v_or3_b32 v0, v0, v2, v4
+; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: or3_v2i32:
-; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-DAG:     v_or3_b32 v0, v0, v2, v4
-; GFX10-DAG:     v_or3_b32 v1, v1, v3, v5
+; GFX10-LABEL: v_or3_v2i32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_or3_b32 v0, v0, v2, v4
+; GFX10-NEXT:    v_or3_b32 v1, v1, v3, v5
+; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10-NEXT:    ; return to shader part epilog
   %x = or <2 x i32> %a, %b
   %result = or <2 x i32> %x, %c
   ret <2 x i32> %result
 }
 
 ; ThreeOp instruction variant not used due to Constant Bus Limitations
-define <2 x i32> @or3_v2i32_b(<2 x i32> inreg %a, <2 x i32> %b, <2 x i32> inreg %c) {
-; VI-LABEL: or3_v2i32_b:
-; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-DAG:    v_or_b32_e32 v0, s16, v0
-; VI-DAG:    v_or_b32_e32 v1, s17, v1
-; VI-CHECK-NOT: {{.}}
-; VI-DAG:    v_or_b32_e32 v0, s18, v0
-; VI-DAG:    v_or_b32_e32 v1, s19, v1
-;
-; GFX9-LABEL: or3_v2i32_b:
-; GFX9:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-DAG:    v_or_b32_e32 v0, s16, v0
-; GFX9-DAG:    v_or_b32_e32 v1, s17, v1
-; GFX9-CHECK-NOT: {{.}}
-; GFX9-DAG:    v_or_b32_e32 v0, s18, v0
-; GFX9-DAG:    v_or_b32_e32 v1, s19, v1
-;
-; GFX10-LABEL: or3_v2i32_b:
-; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-DAG:     v_or3_b32 v0, s{{[0-9]+}}, v0, s{{[0-9]+}}
-; GFX10-DAG:     v_or3_b32 v1, s{{[0-9]+}}, v1, s{{[0-9]+}}
-  %x = or <2 x i32> %a, %b
-  %result = or <2 x i32> %x, %c
-  ret <2 x i32> %result
-}
-
-define <2 x i32> @or3_v2i32_ab(<2 x i32> %a, <2 x i32> %b, <2 x i32> inreg %c) {
-; VI-LABEL: or3_v2i32_ab:
-; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-DAG:    v_or_b32_e32 v0, v0, v2
-; VI-DAG:    v_or_b32_e32 v1, v1, v3
-; VI-CHECK-NOT: {{.}}
-; VI-DAG:    v_or_b32_e32 v0, s16, v0
-; VI-DAG:    v_or_b32_e32 v1, s17, v1
+define amdgpu_ps <2 x i32> @v_or3_v2i32_b(<2 x i32> inreg %a, <2 x i32> %b, <2 x i32> inreg %c) {
+; VI-LABEL: v_or3_v2i32_b:
+; VI:       ; %bb.0:
+; VI-NEXT:    v_or_b32_e32 v1, s3, v1
+; VI-NEXT:    v_or_b32_e32 v0, s2, v0
+; VI-NEXT:    v_or_b32_e32 v1, s5, v1
+; VI-NEXT:    v_or_b32_e32 v0, s4, v0
+; VI-NEXT:    v_readfirstlane_b32 s0, v0
+; VI-NEXT:    v_readfirstlane_b32 s1, v1
+; VI-NEXT:    ; return to shader part epilog
 ;
-; GFX9-LABEL: or3_v2i32_ab:
-; GFX9:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-DAG:     v_or3_b32 v0, v0, v2, s16
-; GFX9-DAG:     v_or3_b32 v1, v1, v3, s17
+; GFX9-LABEL: v_or3_v2i32_b:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_or_b32_e32 v1, s3, v1
+; GFX9-NEXT:    v_or_b32_e32 v0, s2, v0
+; GFX9-NEXT:    v_or_b32_e32 v1, s5, v1
+; GFX9-NEXT:    v_or_b32_e32 v0, s4, v0
+; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: or3_v2i32_ab:
-; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-DAG:     v_or3_b32 v0, v0, v2, s{{[0-9]+}}
-; GFX10-DAG:     v_or3_b32 v1, v1, v3, s{{[0-9]+}}
+; GFX10-LABEL: v_or3_v2i32_b:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_or3_b32 v0, s2, v0, s4
+; GFX10-NEXT:    v_or3_b32 v1, s3, v1, s5
+; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10-NEXT:    ; return to shader part epilog
   %x = or <2 x i32> %a, %b
   %result = or <2 x i32> %x, %c
   ret <2 x i32> %result
 }
 
-define amdgpu_ps <2 x i32> @s_or3_v2i32(<2 x i32> inreg %a, <2 x i32> inreg %b, <2 x i32> inreg %c) {
-; VI-LABEL: s_or3_v2i32:
+define amdgpu_ps <2 x i32> @v_or3_v2i32_ab(<2 x i32> %a, <2 x i32> %b, <2 x i32> inreg %c) {
+; VI-LABEL: v_or3_v2i32_ab:
 ; VI:       ; %bb.0:
-; VI-NEXT:    s_or_b64 s[0:1], s[2:3], s[4:5]
-; VI-NEXT:    s_or_b64 s[0:1], s[0:1], s[6:7]
+; VI-NEXT:    v_or_b32_e32 v1, v1, v3
+; VI-NEXT:    v_or_b32_e32 v0, v0, v2
+; VI-NEXT:    v_or_b32_e32 v1, s3, v1
+; VI-NEXT:    v_or_b32_e32 v0, s2, v0
+; VI-NEXT:    v_readfirstlane_b32 s0, v0
+; VI-NEXT:    v_readfirstlane_b32 s1, v1
+; VI-NEXT:    ; return to shader part epilog
 ;
-; GFX9-LABEL: s_or3_v2i32:
+; GFX9-LABEL: v_or3_v2i32_ab:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_or_b64 s[0:1], s[2:3], s[4:5]
-; GFX9-NEXT:    s_or_b64 s[0:1], s[0:1], s[6:7]
+; GFX9-NEXT:    v_or3_b32 v1, v1, v3, s3
+; GFX9-NEXT:    v_or3_b32 v0, v0, v2, s2
+; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: s_or3_v2i32:
+; GFX10-LABEL: v_or3_v2i32_ab:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_or_b64 s[0:1], s[2:3], s[4:5]
-; GFX10-NEXT:    s_or_b64 s[0:1], s[0:1], s[6:7]
+; GFX10-NEXT:    v_or3_b32 v0, v0, v2, s2
+; GFX10-NEXT:    v_or3_b32 v1, v1, v3, s3
+; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10-NEXT:    ; return to shader part epilog
   %x = or <2 x i32> %a, %b
   %result = or <2 x i32> %x, %c
   ret <2 x i32> %result
 }
 
-define <2 x i32> @or3_v2i32_const(<2 x i32> %a, <2 x i32> %b) {
-; VI-LABEL: or3_v2i32_const:
-; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-DAG:    v_or_b32_e32 v0, 4, v0
-; VI-DAG:    v_or_b32_e32 v1, 16, v1
-; VI-CHECK-NOT: {{.}}
-; VI-DAG:    v_or_b32_e32 v0, v0, v2
-; VI-DAG:    v_or_b32_e32 v1, v1, v3
+define amdgpu_ps <2 x i32> @v_or3_v2i32_const(<2 x i32> %a, <2 x i32> %b) {
+; VI-LABEL: v_or3_v2i32_const:
+; VI:       ; %bb.0:
+; VI-NEXT:    v_or_b32_e32 v1, v1, v3
+; VI-NEXT:    v_or_b32_e32 v0, v0, v2
+; VI-NEXT:    v_or_b32_e32 v1, 16, v1
+; VI-NEXT:    v_or_b32_e32 v0, 4, v0
+; VI-NEXT:    v_readfirstlane_b32 s0, v0
+; VI-NEXT:    v_readfirstlane_b32 s1, v1
+; VI-NEXT:    ; return to shader part epilog
 ;
-; GFX9-LABEL: or3_v2i32_const:
-; GFX9:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-DAG:    v_or3_b32 v0, v0, v2, 4
-; GFX9-DAG:    v_or3_b32 v1, v1, v3, 16
+; GFX9-LABEL: v_or3_v2i32_const:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_or3_b32 v1, v1, v3, 16
+; GFX9-NEXT:    v_or3_b32 v0, v0, v2, 4
+; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: or3_v2i32_const:
-; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-DAG:     v_or3_b32 v0, v0, v2, 4
-; GFX10-DAG:     v_or3_b32 v1, v1, v3, 16
+; GFX10-LABEL: v_or3_v2i32_const:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_or3_b32 v0, v0, v2, 4
+; GFX10-NEXT:    v_or3_b32 v1, v1, v3, 16
+; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10-NEXT:    ; return to shader part epilog
   %x = or <2 x i32> %a, <i32 4, i32 16>
   %result = or <2 x i32> %x, %b
   ret <2 x i32> %result
 }
 
-define <2 x i32> @or3_v2i32_inline_const(<2 x i32> %a, <2 x i32> %b) {
-; VI-LABEL: or3_v2i32_inline_const:
-; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-DAG:    v_or_b32_e32 v0, 0x808, v0
-; VI-DAG:    v_or_b32_e32 v1, 0x809, v1
-; VI-CHECK-NOT: {{.}}
-; VI-DAG:    v_or_b32_e32 v0, v0, v2
-; VI-DAG:    v_or_b32_e32 v1, v1, v3
+define amdgpu_ps <2 x i32> @v_or3_v2i32_inline_const(<2 x i32> %a, <2 x i32> %b) {
+; VI-LABEL: v_or3_v2i32_inline_const:
+; VI:       ; %bb.0:
+; VI-NEXT:    v_or_b32_e32 v1, v1, v3
+; VI-NEXT:    v_or_b32_e32 v0, v0, v2
+; VI-NEXT:    v_or_b32_e32 v1, 0x809, v1
+; VI-NEXT:    v_or_b32_e32 v0, 0x808, v0
+; VI-NEXT:    v_readfirstlane_b32 s0, v0
+; VI-NEXT:    v_readfirstlane_b32 s1, v1
+; VI-NEXT:    ; return to shader part epilog
 ;
-; GFX9-LABEL: or3_v2i32_inline_const:
-; GFX9:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    s_movk_i32 s4, 0x809
-; GFX9-NEXT:    v_or3_b32 v1, v1, v3, s4
-; GFX9-NEXT:    s_movk_i32 s4, 0x808
-; GFX9-NEXT:    v_or3_b32 v0, v0, v2, s4
+; GFX9-LABEL: v_or3_v2i32_inline_const:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_movk_i32 s0, 0x809
+; GFX9-NEXT:    v_or3_b32 v1, v1, v3, s0
+; GFX9-NEXT:    s_movk_i32 s0, 0x808
+; GFX9-NEXT:    v_or3_b32 v0, v0, v2, s0
+; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: or3_v2i32_inline_const:
-; GFX10:         s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-DAG:     v_or3_b32 v0, v0, v2, 0x808
-; GFX10-DAG:     v_or3_b32 v1, v1, v3, 0x809
+; GFX10-LABEL: v_or3_v2i32_inline_const:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_or3_b32 v0, v0, v2, 0x808
+; GFX10-NEXT:    v_or3_b32 v1, v1, v3, 0x809
+; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10-NEXT:    ; return to shader part epilog
   %x = or <2 x i32> %a, <i32 2056, i32 2057>
   %result = or <2 x i32> %x, %b
   ret <2 x i32> %result
 }
 
-define <2 x i32> @or3_v2i32_multi_use(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
-; VI-LABEL: or3_v2i32_multi_use:
-; VI:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-DAG:    v_or_b32_e32 v0, v0, v2
-; VI-DAG:    v_or_b32_e32 v1, v1, v3
-; VI-CHECK-NOT: {{.}}
-; VI-DAG:    v_or_b32_e32 v3, v0, v4
-; VI-DAG:    v_or_b32_e32 v2, v1, v5
+define amdgpu_ps <2 x i32> @v_or3_v2i32_multi_use(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
+; VI-LABEL: v_or3_v2i32_multi_use:
+; VI:       ; %bb.0:
+; VI-NEXT:    v_or_b32_e32 v1, v1, v3
+; VI-NEXT:    v_or_b32_e32 v0, v0, v2
+; VI-NEXT:    v_or_b32_e32 v2, v1, v5
+; VI-NEXT:    v_or_b32_e32 v3, v0, v4
+; VI-NEXT:    v_add_u32_e32 v1, vcc, v1, v2
+; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v3
+; VI-NEXT:    v_readfirstlane_b32 s0, v0
+; VI-NEXT:    v_readfirstlane_b32 s1, v1
+; VI-NEXT:    ; return to shader part epilog
 ;
-; GFX9-LABEL: or3_v2i32_multi_use:
-; GFX9:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-DAG:    v_or_b32_e32 v0, v0, v2
-; GFX9-DAG:    v_or_b32_e32 v1, v1, v3
-; GFX9-CHECK-NOT: {{.}}
-; GFX9-DAG:    v_or_b32_e32 v{{[0-9]+}}, v0, v4
-; GFX9-DAG:    v_or_b32_e32 v{{[0-9]+}}, v1, v5
+; GFX9-LABEL: v_or3_v2i32_multi_use:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX9-NEXT:    v_or_b32_e32 v2, v1, v5
+; GFX9-NEXT:    v_or_b32_e32 v3, v0, v4
+; GFX9-NEXT:    v_add_u32_e32 v1, v1, v2
+; GFX9-NEXT:    v_add_u32_e32 v0, v0, v3
+; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX9-NEXT:    ; return to shader part epilog
 ;
-; GFX10-LABEL: or3_v2i32_multi_use:
-; GFX10:        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-DAG:    v_or_b32_e32 v0, v0, v2
-; GFX10-DAG:    v_or_b32_e32 v1, v1, v3
-; GFX10-CHECK-NOT: {{.}}
-; GFX10-DAG:    v_or_b32_e32 v{{[0-9]+}}, v0, v4
-; GFX10-DAG:    v_or_b32_e32 v{{[0-9]+}}, v1, v5
+; GFX10-LABEL: v_or3_v2i32_multi_use:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX10-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX10-NEXT:    v_or_b32_e32 v2, v0, v4
+; GFX10-NEXT:    v_or_b32_e32 v3, v1, v5
+; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v2
+; GFX10-NEXT:    v_add_nc_u32_e32 v1, v1, v3
+; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX10-NEXT:    ; return to shader part epilog
   %x = or <2 x i32> %a, %b
   %y = or <2 x i32> %x, %c
   %result = add <2 x i32> %x, %y
   ret <2 x i32> %result
 }
+
+define amdgpu_ps <2 x i32> @s_or3_v2i32(<2 x i32> inreg %a, <2 x i32> inreg %b, <2 x i32> inreg %c) {
+; VI-LABEL: s_or3_v2i32:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_or_b64 s[0:1], s[2:3], s[4:5]
+; VI-NEXT:    s_or_b64 s[0:1], s[0:1], s[6:7]
+; VI-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: s_or3_v2i32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_or_b64 s[0:1], s[2:3], s[4:5]
+; GFX9-NEXT:    s_or_b64 s[0:1], s[0:1], s[6:7]
+; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: s_or3_v2i32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_or_b64 s[0:1], s[2:3], s[4:5]
+; GFX10-NEXT:    s_or_b64 s[0:1], s[0:1], s[6:7]
+; GFX10-NEXT:    ; return to shader part epilog
+  %x = or <2 x i32> %a, %b
+  %result = or <2 x i32> %x, %c
+  ret <2 x i32> %result
+}

>From dd354a516654fa95a26feeaa93189117d925fc7f Mon Sep 17 00:00:00 2001
From: wooseoklee <wolee at amd.com>
Date: Mon, 6 Apr 2026 10:54:41 -0500
Subject: [PATCH 7/7] Restore amdgpu_ps use for some tests and adjust some
 autogenerated tests after using update_llc_test.py

---
 llvm/test/CodeGen/AMDGPU/and_or.ll | 210 +++++++++++++----------------
 llvm/test/CodeGen/AMDGPU/or3.ll    | 144 +++++++++-----------
 2 files changed, 153 insertions(+), 201 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/and_or.ll b/llvm/test/CodeGen/AMDGPU/and_or.ll
index a2d46187fdf74..460cc4bbadb02 100644
--- a/llvm/test/CodeGen/AMDGPU/and_or.ll
+++ b/llvm/test/CodeGen/AMDGPU/and_or.ll
@@ -143,304 +143,276 @@ define amdgpu_ps float @and_or_vgpr_inline_const_x2(i32 %a) {
   ret float %bc
 }
 
-define amdgpu_ps <2 x i32> @v_and_or_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
+define <2 x i32> @v_and_or_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
 ; VI-LABEL: v_and_or_v2i32:
 ; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_and_b32_e32 v1, v1, v3
 ; VI-NEXT:    v_and_b32_e32 v0, v0, v2
 ; VI-NEXT:    v_or_b32_e32 v1, v1, v5
 ; VI-NEXT:    v_or_b32_e32 v0, v0, v4
-; VI-NEXT:    v_readfirstlane_b32 s0, v0
-; VI-NEXT:    v_readfirstlane_b32 s1, v1
-; VI-NEXT:    ; return to shader part epilog
+; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_and_or_v2i32:
 ; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_and_or_b32 v1, v1, v3, v5
 ; GFX9-NEXT:    v_and_or_b32 v0, v0, v2, v4
-; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX9-NEXT:    ; return to shader part epilog
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_and_or_v2i32:
 ; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    v_and_or_b32 v0, v0, v2, v4
 ; GFX10-NEXT:    v_and_or_b32 v1, v1, v3, v5
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %x = and <2 x i32> %a, %b
   %result = or <2 x i32> %x, %c
   ret <2 x i32> %result
 }
 
 ; ThreeOp instruction variant not used due to Constant Bus Limitations
-define amdgpu_ps <2 x i32> @v_and_or_v2i32_b(<2 x i32> inreg %a, <2 x i32> %b, <2 x i32> inreg %c) {
+define <2 x i32> @v_and_or_v2i32_b(<2 x i32> inreg %a, <2 x i32> %b, <2 x i32> inreg %c) {
 ; VI-LABEL: v_and_or_v2i32_b:
 ; VI:       ; %bb.0:
-; VI-NEXT:    v_and_b32_e32 v1, s3, v1
-; VI-NEXT:    v_and_b32_e32 v0, s2, v0
-; VI-NEXT:    v_or_b32_e32 v1, s5, v1
-; VI-NEXT:    v_or_b32_e32 v0, s4, v0
-; VI-NEXT:    v_readfirstlane_b32 s0, v0
-; VI-NEXT:    v_readfirstlane_b32 s1, v1
-; VI-NEXT:    ; return to shader part epilog
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_and_b32_e32 v1, s17, v1
+; VI-NEXT:    v_and_b32_e32 v0, s16, v0
+; VI-NEXT:    v_or_b32_e32 v1, s19, v1
+; VI-NEXT:    v_or_b32_e32 v0, s18, v0
+; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_and_or_v2i32_b:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    v_and_b32_e32 v1, s3, v1
-; GFX9-NEXT:    v_and_b32_e32 v0, s2, v0
-; GFX9-NEXT:    v_or_b32_e32 v1, s5, v1
-; GFX9-NEXT:    v_or_b32_e32 v0, s4, v0
-; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX9-NEXT:    ; return to shader part epilog
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_and_b32_e32 v1, s17, v1
+; GFX9-NEXT:    v_and_b32_e32 v0, s16, v0
+; GFX9-NEXT:    v_or_b32_e32 v1, s19, v1
+; GFX9-NEXT:    v_or_b32_e32 v0, s18, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_and_or_v2i32_b:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_and_or_b32 v0, s2, v0, s4
-; GFX10-NEXT:    v_and_or_b32 v1, s3, v1, s5
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:     v_and_or_b32 v0, s{{[0-9]+}}, v0, s{{[0-9]+}}
+; GFX10-DAG:     v_and_or_b32 v1, s{{[0-9]+}}, v1, s{{[0-9]+}}
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %x = and <2 x i32> %a, %b
   %result = or <2 x i32> %x, %c
   ret <2 x i32> %result
 }
 
-define amdgpu_ps <2 x i32> @v_and_or_v2i32_ab(<2 x i32> %a, <2 x i32> %b, <2 x i32> inreg %c) {
+define <2 x i32> @v_and_or_v2i32_ab(<2 x i32> %a, <2 x i32> %b, <2 x i32> inreg %c) {
 ; VI-LABEL: v_and_or_v2i32_ab:
 ; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_and_b32_e32 v1, v1, v3
 ; VI-NEXT:    v_and_b32_e32 v0, v0, v2
-; VI-NEXT:    v_or_b32_e32 v1, s3, v1
-; VI-NEXT:    v_or_b32_e32 v0, s2, v0
-; VI-NEXT:    v_readfirstlane_b32 s0, v0
-; VI-NEXT:    v_readfirstlane_b32 s1, v1
-; VI-NEXT:    ; return to shader part epilog
+; VI-NEXT:    v_or_b32_e32 v1, s17, v1
+; VI-NEXT:    v_or_b32_e32 v0, s16, v0
+; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_and_or_v2i32_ab:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    v_and_or_b32 v1, v1, v3, s3
-; GFX9-NEXT:    v_and_or_b32 v0, v0, v2, s2
-; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX9-NEXT:    ; return to shader part epilog
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_and_or_b32 v1, v1, v3, s17
+; GFX9-NEXT:    v_and_or_b32 v0, v0, v2, s16
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_and_or_v2i32_ab:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_and_or_b32 v0, v0, v2, s2
-; GFX10-NEXT:    v_and_or_b32 v1, v1, v3, s3
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:     v_and_or_b32 v1, v1, v3, {{s[0-9]+}}
+; GFX10-DAG:     v_and_or_b32 v0, v0, v2, {{s[0-9]+}}
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %x = and <2 x i32> %a, %b
   %result = or <2 x i32> %x, %c
   ret <2 x i32> %result
 }
 
-define amdgpu_ps <2 x i32> @v_and_or_v2i32_const(<2 x i32> %a, <2 x i32> %b) {
+define <2 x i32> @v_and_or_v2i32_const(<2 x i32> %a, <2 x i32> %b) {
 ; VI-LABEL: v_and_or_v2i32_const:
 ; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_and_b32_e32 v1, 16, v1
 ; VI-NEXT:    v_and_b32_e32 v0, 4, v0
 ; VI-NEXT:    v_or_b32_e32 v1, v1, v3
 ; VI-NEXT:    v_or_b32_e32 v0, v0, v2
-; VI-NEXT:    v_readfirstlane_b32 s0, v0
-; VI-NEXT:    v_readfirstlane_b32 s1, v1
-; VI-NEXT:    ; return to shader part epilog
+; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_and_or_v2i32_const:
 ; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_and_or_b32 v1, v1, 16, v3
 ; GFX9-NEXT:    v_and_or_b32 v0, v0, 4, v2
-; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX9-NEXT:    ; return to shader part epilog
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_and_or_v2i32_const:
 ; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    v_and_or_b32 v0, v0, 4, v2
 ; GFX10-NEXT:    v_and_or_b32 v1, v1, 16, v3
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %x = and <2 x i32> %a, <i32 4, i32 16>
   %result = or <2 x i32> %x, %b
   ret <2 x i32> %result
 }
 
-define amdgpu_ps <2 x i32> @v_and_or_v2i32_inline_const(<2 x i32> %a, <2 x i32> %b) {
+define <2 x i32> @v_and_or_v2i32_inline_const(<2 x i32> %a, <2 x i32> %b) {
 ; VI-LABEL: v_and_or_v2i32_inline_const:
 ; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_and_b32_e32 v1, 0x809, v1
 ; VI-NEXT:    v_and_b32_e32 v0, 0x808, v0
 ; VI-NEXT:    v_or_b32_e32 v1, v1, v3
 ; VI-NEXT:    v_or_b32_e32 v0, v0, v2
-; VI-NEXT:    v_readfirstlane_b32 s0, v0
-; VI-NEXT:    v_readfirstlane_b32 s1, v1
-; VI-NEXT:    ; return to shader part epilog
+; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_and_or_v2i32_inline_const:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_movk_i32 s0, 0x809
-; GFX9-NEXT:    v_and_or_b32 v1, v1, s0, v3
-; GFX9-NEXT:    s_movk_i32 s0, 0x808
-; GFX9-NEXT:    v_and_or_b32 v0, v0, s0, v2
-; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX9-NEXT:    ; return to shader part epilog
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    s_movk_i32 s4, 0x809
+; GFX9-NEXT:    v_and_or_b32 v1, v1, s4, v3
+; GFX9-NEXT:    s_movk_i32 s4, 0x808
+; GFX9-NEXT:    v_and_or_b32 v0, v0, s4, v2
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_and_or_v2i32_inline_const:
 ; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    v_and_or_b32 v0, 0x808, v0, v2
 ; GFX10-NEXT:    v_and_or_b32 v1, 0x809, v1, v3
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %x = and <2 x i32> %a, <i32 2056, i32 2057>
   %result = or <2 x i32> %x, %b
   ret <2 x i32> %result
 }
 
-define amdgpu_ps <2 x i32> @v_and_or_v2i32_inline_const_x2(<2 x i32> %a) {
+define <2 x i32> @v_and_or_v2i32_inline_const_x2(<2 x i32> %a) {
 ; VI-LABEL: v_and_or_v2i32_inline_const_x2:
 ; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_and_b32_e32 v1, 0x809, v1
 ; VI-NEXT:    v_and_b32_e32 v0, 0x808, v0
 ; VI-NEXT:    v_or_b32_e32 v1, 16, v1
 ; VI-NEXT:    v_or_b32_e32 v0, 4, v0
-; VI-NEXT:    v_readfirstlane_b32 s0, v0
-; VI-NEXT:    v_readfirstlane_b32 s1, v1
-; VI-NEXT:    ; return to shader part epilog
+; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_and_or_v2i32_inline_const_x2:
 ; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_and_b32_e32 v1, 0x809, v1
 ; GFX9-NEXT:    v_and_b32_e32 v0, 0x808, v0
 ; GFX9-NEXT:    v_or_b32_e32 v1, 16, v1
 ; GFX9-NEXT:    v_or_b32_e32 v0, 4, v0
-; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX9-NEXT:    ; return to shader part epilog
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_and_or_v2i32_inline_const_x2:
 ; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    v_and_or_b32 v0, 0x808, v0, 4
 ; GFX10-NEXT:    v_and_or_b32 v1, 0x809, v1, 16
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %x = and <2 x i32> %a, <i32 2056, i32 2057>
   %result = or <2 x i32> %x, <i32 4, i32 16>
   ret <2 x i32> %result
 }
 
-define amdgpu_ps <2 x i32> @v_and_or_v2i32_inline_const_x3(<2 x i32> %a) {
+define <2 x i32> @v_and_or_v2i32_inline_const_x3(<2 x i32> %a) {
 ; VI-LABEL: v_and_or_v2i32_inline_const_x3:
 ; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_and_b32_e32 v1, 0x809, v1
 ; VI-NEXT:    v_and_b32_e32 v0, 0x808, v0
 ; VI-NEXT:    v_or_b32_e32 v1, 16, v1
 ; VI-NEXT:    v_or_b32_e32 v0, 0x81, v0
-; VI-NEXT:    v_readfirstlane_b32 s0, v0
-; VI-NEXT:    v_readfirstlane_b32 s1, v1
-; VI-NEXT:    ; return to shader part epilog
+; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_and_or_v2i32_inline_const_x3:
 ; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_and_b32_e32 v1, 0x809, v1
 ; GFX9-NEXT:    v_and_b32_e32 v0, 0x808, v0
 ; GFX9-NEXT:    v_or_b32_e32 v1, 16, v1
 ; GFX9-NEXT:    v_or_b32_e32 v0, 0x81, v0
-; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX9-NEXT:    ; return to shader part epilog
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_and_or_v2i32_inline_const_x3:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_movk_i32 s0, 0x808
-; GFX10-NEXT:    v_and_or_b32 v1, 0x809, v1, 16
-; GFX10-NEXT:    v_and_or_b32 v0, v0, s0, 0x81
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_movk_i32 [[SR:s[0-9]+]], 0x808
+; GFX10-DAG:     v_and_or_b32 v0, v0, [[SR]], 0x81
+; GFX10-DAG:     v_and_or_b32 v1, 0x809, v1, 16
   %x = and <2 x i32> %a, <i32 2056, i32 2057>
   %result = or <2 x i32> %x, <i32 129, i32 16>
   ret <2 x i32> %result
 }
 
-define amdgpu_ps <2 x i32> @v_and_or_v2i32_inline_const_x4(<2 x i32> %a) {
+define <2 x i32> @v_and_or_v2i32_inline_const_x4(<2 x i32> %a) {
 ; VI-LABEL: v_and_or_v2i32_inline_const_x4:
 ; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_and_b32_e32 v1, 0x809, v1
 ; VI-NEXT:    v_and_b32_e32 v0, 0x808, v0
 ; VI-NEXT:    v_or_b32_e32 v1, 0x101, v1
 ; VI-NEXT:    v_or_b32_e32 v0, 0x81, v0
-; VI-NEXT:    v_readfirstlane_b32 s0, v0
-; VI-NEXT:    v_readfirstlane_b32 s1, v1
-; VI-NEXT:    ; return to shader part epilog
+; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_and_or_v2i32_inline_const_x4:
 ; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_and_b32_e32 v1, 0x809, v1
 ; GFX9-NEXT:    v_and_b32_e32 v0, 0x808, v0
 ; GFX9-NEXT:    v_or_b32_e32 v1, 0x101, v1
 ; GFX9-NEXT:    v_or_b32_e32 v0, 0x81, v0
-; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX9-NEXT:    ; return to shader part epilog
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_and_or_v2i32_inline_const_x4:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_movk_i32 s0, 0x808
-; GFX10-NEXT:    s_movk_i32 s1, 0x809
-; GFX10-NEXT:    v_and_or_b32 v0, v0, s0, 0x81
-; GFX10-NEXT:    v_and_or_b32 v1, v1, s1, 0x101
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:     s_movk_i32 [[SR0:s[0-9]+]], 0x808
+; GFX10-DAG:     s_movk_i32 [[SR1:s[0-9]+]], 0x809
+; GFX10-CHECK-NOT: {{.}}
+; GFX10-DAG:     v_and_or_b32 v0, v0, [[SR0]], 0x81
+; GFX10-DAG:     v_and_or_b32 v1, v1, [[SR1]], 0x101
   %x = and <2 x i32> %a, <i32 2056, i32 2057>
   %result = or <2 x i32> %x, <i32 129, i32 257>
   ret <2 x i32> %result
 }
 
-define amdgpu_ps <2 x i32> @v_and_or_v2i32_multi_use(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
+define <2 x i32> @v_and_or_v2i32_multi_use(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
 ; VI-LABEL: v_and_or_v2i32_multi_use:
 ; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_and_b32_e32 v1, v1, v3
 ; VI-NEXT:    v_and_b32_e32 v0, v0, v2
 ; VI-NEXT:    v_or_b32_e32 v2, v1, v5
 ; VI-NEXT:    v_or_b32_e32 v3, v0, v4
-; VI-NEXT:    v_add_u32_e32 v1, vcc, v1, v2
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v3
-; VI-NEXT:    v_readfirstlane_b32 s0, v0
-; VI-NEXT:    v_readfirstlane_b32 s1, v1
-; VI-NEXT:    ; return to shader part epilog
+; VI-NEXT:    v_add_u32_e32 v1, vcc, v1, v2
+; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_and_or_v2i32_multi_use:
 ; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_and_b32_e32 v1, v1, v3
 ; GFX9-NEXT:    v_and_b32_e32 v0, v0, v2
 ; GFX9-NEXT:    v_or_b32_e32 v2, v1, v5
 ; GFX9-NEXT:    v_or_b32_e32 v3, v0, v4
-; GFX9-NEXT:    v_add_u32_e32 v1, v1, v2
 ; GFX9-NEXT:    v_add_u32_e32 v0, v0, v3
-; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX9-NEXT:    ; return to shader part epilog
+; GFX9-NEXT:    v_add_u32_e32 v1, v1, v2
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_and_or_v2i32_multi_use:
 ; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    v_and_b32_e32 v0, v0, v2
 ; GFX10-NEXT:    v_and_b32_e32 v1, v1, v3
 ; GFX10-NEXT:    v_or_b32_e32 v2, v0, v4
 ; GFX10-NEXT:    v_or_b32_e32 v3, v1, v5
 ; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v2
 ; GFX10-NEXT:    v_add_nc_u32_e32 v1, v1, v3
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %x = and <2 x i32> %a, %b
   %y = or <2 x i32> %x, %c
   %result = add <2 x i32> %x, %y
diff --git a/llvm/test/CodeGen/AMDGPU/or3.ll b/llvm/test/CodeGen/AMDGPU/or3.ll
index 2973ec67b78c4..bf331ee6c6e3b 100644
--- a/llvm/test/CodeGen/AMDGPU/or3.ll
+++ b/llvm/test/CodeGen/AMDGPU/or3.ll
@@ -121,202 +121,182 @@ define amdgpu_ps float @or3_vgpr_const(i32 %a, i32 %b) {
   ret float %bc
 }
 
-define amdgpu_ps <2 x i32> @v_or3_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
+define <2 x i32> @v_or3_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
 ; VI-LABEL: v_or3_v2i32:
 ; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_or_b32_e32 v1, v1, v3
 ; VI-NEXT:    v_or_b32_e32 v0, v0, v2
 ; VI-NEXT:    v_or_b32_e32 v1, v1, v5
 ; VI-NEXT:    v_or_b32_e32 v0, v0, v4
-; VI-NEXT:    v_readfirstlane_b32 s0, v0
-; VI-NEXT:    v_readfirstlane_b32 s1, v1
-; VI-NEXT:    ; return to shader part epilog
+; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_or3_v2i32:
 ; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_or3_b32 v1, v1, v3, v5
 ; GFX9-NEXT:    v_or3_b32 v0, v0, v2, v4
-; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX9-NEXT:    ; return to shader part epilog
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_or3_v2i32:
 ; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    v_or3_b32 v0, v0, v2, v4
 ; GFX10-NEXT:    v_or3_b32 v1, v1, v3, v5
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %x = or <2 x i32> %a, %b
   %result = or <2 x i32> %x, %c
   ret <2 x i32> %result
 }
 
 ; ThreeOp instruction variant not used due to Constant Bus Limitations
-define amdgpu_ps <2 x i32> @v_or3_v2i32_b(<2 x i32> inreg %a, <2 x i32> %b, <2 x i32> inreg %c) {
+define <2 x i32> @v_or3_v2i32_b(<2 x i32> inreg %a, <2 x i32> %b, <2 x i32> inreg %c) {
 ; VI-LABEL: v_or3_v2i32_b:
 ; VI:       ; %bb.0:
-; VI-NEXT:    v_or_b32_e32 v1, s3, v1
-; VI-NEXT:    v_or_b32_e32 v0, s2, v0
-; VI-NEXT:    v_or_b32_e32 v1, s5, v1
-; VI-NEXT:    v_or_b32_e32 v0, s4, v0
-; VI-NEXT:    v_readfirstlane_b32 s0, v0
-; VI-NEXT:    v_readfirstlane_b32 s1, v1
-; VI-NEXT:    ; return to shader part epilog
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_or_b32_e32 v1, s17, v1
+; VI-NEXT:    v_or_b32_e32 v0, s16, v0
+; VI-NEXT:    v_or_b32_e32 v1, s19, v1
+; VI-NEXT:    v_or_b32_e32 v0, s18, v0
+; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_or3_v2i32_b:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    v_or_b32_e32 v1, s3, v1
-; GFX9-NEXT:    v_or_b32_e32 v0, s2, v0
-; GFX9-NEXT:    v_or_b32_e32 v1, s5, v1
-; GFX9-NEXT:    v_or_b32_e32 v0, s4, v0
-; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX9-NEXT:    ; return to shader part epilog
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_or_b32_e32 v1, s17, v1
+; GFX9-NEXT:    v_or_b32_e32 v0, s16, v0
+; GFX9-NEXT:    v_or_b32_e32 v1, s19, v1
+; GFX9-NEXT:    v_or_b32_e32 v0, s18, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_or3_v2i32_b:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_or3_b32 v0, s2, v0, s4
-; GFX10-NEXT:    v_or3_b32 v1, s3, v1, s5
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:     v_or3_b32 v0, s{{[0-9]+}}, v0, s{{[0-9]+}}
+; GFX10-DAG:     v_or3_b32 v1, s{{[0-9]+}}, v1, s{{[0-9]+}}
   %x = or <2 x i32> %a, %b
   %result = or <2 x i32> %x, %c
   ret <2 x i32> %result
 }
 
-define amdgpu_ps <2 x i32> @v_or3_v2i32_ab(<2 x i32> %a, <2 x i32> %b, <2 x i32> inreg %c) {
+define <2 x i32> @v_or3_v2i32_ab(<2 x i32> %a, <2 x i32> %b, <2 x i32> inreg %c) {
 ; VI-LABEL: v_or3_v2i32_ab:
 ; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_or_b32_e32 v1, v1, v3
 ; VI-NEXT:    v_or_b32_e32 v0, v0, v2
-; VI-NEXT:    v_or_b32_e32 v1, s3, v1
-; VI-NEXT:    v_or_b32_e32 v0, s2, v0
-; VI-NEXT:    v_readfirstlane_b32 s0, v0
-; VI-NEXT:    v_readfirstlane_b32 s1, v1
-; VI-NEXT:    ; return to shader part epilog
+; VI-NEXT:    v_or_b32_e32 v1, s17, v1
+; VI-NEXT:    v_or_b32_e32 v0, s16, v0
+; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_or3_v2i32_ab:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    v_or3_b32 v1, v1, v3, s3
-; GFX9-NEXT:    v_or3_b32 v0, v0, v2, s2
-; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX9-NEXT:    ; return to shader part epilog
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_or3_b32 v1, v1, v3, s17
+; GFX9-NEXT:    v_or3_b32 v0, v0, v2, s16
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_or3_v2i32_ab:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_or3_b32 v0, v0, v2, s2
-; GFX10-NEXT:    v_or3_b32 v1, v1, v3, s3
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-DAG:     v_or3_b32 v0, v0, v2, s{{[0-9]+}}
+; GFX10-DAG:     v_or3_b32 v1, v1, v3, s{{[0-9]+}}
   %x = or <2 x i32> %a, %b
   %result = or <2 x i32> %x, %c
   ret <2 x i32> %result
 }
 
-define amdgpu_ps <2 x i32> @v_or3_v2i32_const(<2 x i32> %a, <2 x i32> %b) {
+define <2 x i32> @v_or3_v2i32_const(<2 x i32> %a, <2 x i32> %b) {
 ; VI-LABEL: v_or3_v2i32_const:
 ; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_or_b32_e32 v1, v1, v3
 ; VI-NEXT:    v_or_b32_e32 v0, v0, v2
 ; VI-NEXT:    v_or_b32_e32 v1, 16, v1
 ; VI-NEXT:    v_or_b32_e32 v0, 4, v0
-; VI-NEXT:    v_readfirstlane_b32 s0, v0
-; VI-NEXT:    v_readfirstlane_b32 s1, v1
-; VI-NEXT:    ; return to shader part epilog
+; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_or3_v2i32_const:
 ; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_or3_b32 v1, v1, v3, 16
 ; GFX9-NEXT:    v_or3_b32 v0, v0, v2, 4
-; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX9-NEXT:    ; return to shader part epilog
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_or3_v2i32_const:
 ; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    v_or3_b32 v0, v0, v2, 4
 ; GFX10-NEXT:    v_or3_b32 v1, v1, v3, 16
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %x = or <2 x i32> %a, <i32 4, i32 16>
   %result = or <2 x i32> %x, %b
   ret <2 x i32> %result
 }
 
-define amdgpu_ps <2 x i32> @v_or3_v2i32_inline_const(<2 x i32> %a, <2 x i32> %b) {
+define <2 x i32> @v_or3_v2i32_inline_const(<2 x i32> %a, <2 x i32> %b) {
 ; VI-LABEL: v_or3_v2i32_inline_const:
 ; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_or_b32_e32 v1, v1, v3
 ; VI-NEXT:    v_or_b32_e32 v0, v0, v2
 ; VI-NEXT:    v_or_b32_e32 v1, 0x809, v1
 ; VI-NEXT:    v_or_b32_e32 v0, 0x808, v0
-; VI-NEXT:    v_readfirstlane_b32 s0, v0
-; VI-NEXT:    v_readfirstlane_b32 s1, v1
-; VI-NEXT:    ; return to shader part epilog
+; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_or3_v2i32_inline_const:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_movk_i32 s0, 0x809
-; GFX9-NEXT:    v_or3_b32 v1, v1, v3, s0
-; GFX9-NEXT:    s_movk_i32 s0, 0x808
-; GFX9-NEXT:    v_or3_b32 v0, v0, v2, s0
-; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX9-NEXT:    ; return to shader part epilog
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    s_movk_i32 s4, 0x809
+; GFX9-NEXT:    v_or3_b32 v1, v1, v3, s4
+; GFX9-NEXT:    s_movk_i32 s4, 0x808
+; GFX9-NEXT:    v_or3_b32 v0, v0, v2, s4
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_or3_v2i32_inline_const:
 ; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    v_or3_b32 v0, v0, v2, 0x808
 ; GFX10-NEXT:    v_or3_b32 v1, v1, v3, 0x809
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %x = or <2 x i32> %a, <i32 2056, i32 2057>
   %result = or <2 x i32> %x, %b
   ret <2 x i32> %result
 }
 
-define amdgpu_ps <2 x i32> @v_or3_v2i32_multi_use(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
+define <2 x i32> @v_or3_v2i32_multi_use(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
 ; VI-LABEL: v_or3_v2i32_multi_use:
 ; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_or_b32_e32 v1, v1, v3
 ; VI-NEXT:    v_or_b32_e32 v0, v0, v2
 ; VI-NEXT:    v_or_b32_e32 v2, v1, v5
 ; VI-NEXT:    v_or_b32_e32 v3, v0, v4
-; VI-NEXT:    v_add_u32_e32 v1, vcc, v1, v2
 ; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v3
-; VI-NEXT:    v_readfirstlane_b32 s0, v0
-; VI-NEXT:    v_readfirstlane_b32 s1, v1
-; VI-NEXT:    ; return to shader part epilog
+; VI-NEXT:    v_add_u32_e32 v1, vcc, v1, v2
+; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_or3_v2i32_multi_use:
 ; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
 ; GFX9-NEXT:    v_or_b32_e32 v0, v0, v2
 ; GFX9-NEXT:    v_or_b32_e32 v2, v1, v5
 ; GFX9-NEXT:    v_or_b32_e32 v3, v0, v4
-; GFX9-NEXT:    v_add_u32_e32 v1, v1, v2
 ; GFX9-NEXT:    v_add_u32_e32 v0, v0, v3
-; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX9-NEXT:    ; return to shader part epilog
+; GFX9-NEXT:    v_add_u32_e32 v1, v1, v2
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_or3_v2i32_multi_use:
 ; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    v_or_b32_e32 v0, v0, v2
 ; GFX10-NEXT:    v_or_b32_e32 v1, v1, v3
 ; GFX10-NEXT:    v_or_b32_e32 v2, v0, v4
 ; GFX10-NEXT:    v_or_b32_e32 v3, v1, v5
 ; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v2
 ; GFX10-NEXT:    v_add_nc_u32_e32 v1, v1, v3
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
-; GFX10-NEXT:    ; return to shader part epilog
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %x = or <2 x i32> %a, %b
   %y = or <2 x i32> %x, %c
   %result = add <2 x i32> %x, %y

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