[llvm] [PowerPC] Fixed issue https://github.com/llvm/llvm-project/issues/98598 (PR #190606)
zhijian lin via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 6 06:44:07 PDT 2026
https://github.com/diggerlin created https://github.com/llvm/llvm-project/pull/190606
The patch fixed issue [[PowerPC] Failure to optimize (x == 0) ? 0xFF : 0 to addic+subfe instead of cntlzw+srwi+neg ](https://github.com/llvm/llvm-project/issues/98598)
>From 1c67563237175183961e22aff21af37979a64d63 Mon Sep 17 00:00:00 2001
From: zhijian <zhijian at ca.ibm.com>
Date: Thu, 15 Jan 2026 20:07:48 +0000
Subject: [PATCH 1/2] implement combine the signed extend of setcc with zero
---
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 41 +++++++++++++++++++++
llvm/lib/Target/PowerPC/PPCISelLowering.h | 1 +
2 files changed, 42 insertions(+)
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index ef211bf8c8982..94d786760ebe8 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -15755,6 +15755,44 @@ static SDValue ConvertSETCCToXori(SDNode *N, SelectionDAG &DAG) {
llvm_unreachable("Should not reach here.");
}
+SDValue PPCTargetLowering::combineSignExtendSetCC(SDNode *N,
+ DAGCombinerInfo &DCI) const {
+ if (N->getValueType(0) != MVT::i32 && N->getValueType(0) != MVT::i64)
+ return SDValue();
+
+ SDValue N0 = N->getOperand(0);
+ if (N0.getOpcode() == ISD::SETCC) {
+ ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
+ SDValue LHS = N0.getOperand(0);
+ SDValue RHS = N0.getOperand(1);
+ // Match: sext (setcc x, 0, eq) or sext (setcc 0, x, eq)
+ if (CC == ISD::SETEQ && (isNullConstant(LHS) || isNullConstant(RHS))) {
+ SDLoc dl(N);
+ SelectionDAG &DAG = DCI.DAG;
+
+ EVT VT = N->getValueType(0);
+
+ SDValue X = isNullConstant(LHS) ? RHS : LHS;
+ EVT XVT = X.getValueType(); // The type of x in the setcc x, 0, eq.
+
+ // If input is i32 but result is i64, we need to extend first
+ if (XVT != VT) {
+ // Zero-extend i32 to i64 before ADDC
+ X = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, X);
+ }
+
+ // Generate: rlwinm(subfe(addic(x, -1), addic(x, -1)), 0, mask)
+ SDValue MinusOne = DAG.getAllOnesConstant(dl, VT);
+ SDValue Addic = DAG.getNode(PPCISD::ADDC, dl, DAG.getVTList(VT, MVT::i32),
+ X, MinusOne);
+ SDValue Carry = Addic.getValue(1);
+ return DAG.getNode(PPCISD::SUBE, dl, DAG.getVTList(VT, MVT::i32), Addic,
+ Addic, Carry);
+ }
+ }
+ return SDValue();
+}
+
SDValue PPCTargetLowering::combineSetCC(SDNode *N,
DAGCombinerInfo &DCI) const {
assert(N->getOpcode() == ISD::SETCC &&
@@ -17187,6 +17225,9 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
}
break;
case ISD::SIGN_EXTEND:
+ if (SDValue SECC = combineSignExtendSetCC(N, DCI))
+ return SECC;
+ [[fallthrough]];
case ISD::ZERO_EXTEND:
case ISD::ANY_EXTEND:
return DAGCombineExtBoolTrunc(N, DCI);
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
index daae839479c3c..3650176de762d 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -871,6 +871,7 @@ namespace llvm {
SDValue combineADD(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue combineFMALike(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const;
+ SDValue combineSignExtendSetCC(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue combineVectorShuffle(ShuffleVectorSDNode *SVN,
SelectionDAG &DAG) const;
>From ac5bdc895004be2a4a0f220db8f484681a8f04e0 Mon Sep 17 00:00:00 2001
From: zhijian <zhijian at ca.ibm.com>
Date: Mon, 9 Mar 2026 19:58:00 +0000
Subject: [PATCH 2/2] change test case and add some comment
---
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 14 ++++++++++++
.../test/CodeGen/PowerPC/testComparesieqsc.ll | 22 +++++++++----------
.../test/CodeGen/PowerPC/testComparesieqsi.ll | 22 +++++++++----------
.../test/CodeGen/PowerPC/testComparesieqss.ll | 22 +++++++++----------
.../test/CodeGen/PowerPC/testComparesiequc.ll | 20 +++++++----------
.../test/CodeGen/PowerPC/testComparesiequi.ll | 20 +++++++----------
.../test/CodeGen/PowerPC/testComparesiequs.ll | 20 +++++++----------
.../test/CodeGen/PowerPC/testComparesileuc.ll | 10 ++++-----
.../test/CodeGen/PowerPC/testComparesileui.ll | 10 ++++-----
.../test/CodeGen/PowerPC/testComparesileus.ll | 10 ++++-----
.../CodeGen/PowerPC/testCompareslleqsc.ll | 22 +++++++++----------
.../CodeGen/PowerPC/testCompareslleqsi.ll | 22 +++++++++----------
.../CodeGen/PowerPC/testCompareslleqss.ll | 22 +++++++++----------
.../CodeGen/PowerPC/testComparesllequc.ll | 20 +++++++----------
.../CodeGen/PowerPC/testComparesllequi.ll | 20 +++++++----------
.../CodeGen/PowerPC/testComparesllequs.ll | 20 +++++++----------
.../CodeGen/PowerPC/testComparesllleuc.ll | 10 ++++-----
.../CodeGen/PowerPC/testComparesllleui.ll | 10 ++++-----
.../CodeGen/PowerPC/testComparesllleus.ll | 10 ++++-----
19 files changed, 146 insertions(+), 180 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 94d786760ebe8..f012a4f8a5852 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -15755,8 +15755,22 @@ static SDValue ConvertSETCCToXori(SDNode *N, SelectionDAG &DAG) {
llvm_unreachable("Should not reach here.");
}
+// Match `sext(setcc X, 0, eq)` and turn it into an ADDIC/SUBFE sequence.
+//
+// This generates code for:
+// X == 0 ? -1 : 0
+//
+// On pre-ISA 3.1 targets, this is better than the longer CNTLZW/SRWI/NEG
+// sequence. This is useful for cases like:
+// uint8_t f(uint8_t x) { return (x == 0) ? -1 : 0; }
+//
+// ISA 3.1+ is skipped because those targets can use SETBC.
+
SDValue PPCTargetLowering::combineSignExtendSetCC(SDNode *N,
DAGCombinerInfo &DCI) const {
+ if (Subtarget.isISA3_1())
+ return SDValue();
+
if (N->getValueType(0) != MVT::i32 && N->getValueType(0) != MVT::i64)
return SDValue();
diff --git a/llvm/test/CodeGen/PowerPC/testComparesieqsc.ll b/llvm/test/CodeGen/PowerPC/testComparesieqsc.ll
index 4b11638fdd1c1..5690a0d362df2 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesieqsc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesieqsc.ll
@@ -100,16 +100,16 @@ define dso_local signext i32 @test_ieqsc_sext_z(i8 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsc_sext_z:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: cntlzw r3, r3
-; CHECK-BE-NEXT: srwi r3, r3, 5
-; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: clrldi r3, r3, 56
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsc_sext_z:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: cntlzw r3, r3
-; CHECK-LE-NEXT: srwi r3, r3, 5
-; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: clrldi r3, r3, 56
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
@@ -231,19 +231,17 @@ define dso_local void @test_ieqsc_sext_z_store(i8 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsc_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-BE-NEXT: srwi r3, r3, 5
-; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: stb r3, glob at toc@l(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsc_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-LE-NEXT: srwi r3, r3, 5
-; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: stb r3, glob at toc@l(r4)
; CHECK-LE-NEXT: blr
entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesieqsi.ll b/llvm/test/CodeGen/PowerPC/testComparesieqsi.ll
index 79b85475f9c2e..b43b5d6d636d5 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesieqsi.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesieqsi.ll
@@ -100,16 +100,16 @@ define dso_local signext i32 @test_ieqsi_sext_z(i32 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsi_sext_z:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: cntlzw r3, r3
-; CHECK-BE-NEXT: srwi r3, r3, 5
-; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: clrldi r3, r3, 32
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsi_sext_z:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: cntlzw r3, r3
-; CHECK-LE-NEXT: srwi r3, r3, 5
-; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: clrldi r3, r3, 32
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
@@ -231,19 +231,17 @@ define dso_local void @test_ieqsi_sext_z_store(i32 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsi_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-BE-NEXT: srwi r3, r3, 5
-; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: stw r3, glob at toc@l(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsi_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-LE-NEXT: srwi r3, r3, 5
-; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: stw r3, glob at toc@l(r4)
; CHECK-LE-NEXT: blr
entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesieqss.ll b/llvm/test/CodeGen/PowerPC/testComparesieqss.ll
index 4d565b5a539d2..eb629c16950eb 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesieqss.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesieqss.ll
@@ -100,16 +100,16 @@ define dso_local signext i32 @test_ieqss_sext_z(i16 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqss_sext_z:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: cntlzw r3, r3
-; CHECK-BE-NEXT: srwi r3, r3, 5
-; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: clrldi r3, r3, 48
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqss_sext_z:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: cntlzw r3, r3
-; CHECK-LE-NEXT: srwi r3, r3, 5
-; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: clrldi r3, r3, 48
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
@@ -231,19 +231,17 @@ define dso_local void @test_ieqss_sext_z_store(i16 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqss_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-BE-NEXT: srwi r3, r3, 5
-; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: sth r3, glob at toc@l(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqss_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-LE-NEXT: srwi r3, r3, 5
-; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: sth r3, glob at toc@l(r4)
; CHECK-LE-NEXT: blr
entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesiequc.ll b/llvm/test/CodeGen/PowerPC/testComparesiequc.ll
index 6e799716fe44d..da4b4ede5ab52 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesiequc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiequc.ll
@@ -100,16 +100,14 @@ define dso_local signext i32 @test_iequc_sext_z(i8 zeroext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequc_sext_z:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: cntlzw r3, r3
-; CHECK-BE-NEXT: srwi r3, r3, 5
-; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequc_sext_z:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: cntlzw r3, r3
-; CHECK-LE-NEXT: srwi r3, r3, 5
-; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
@@ -231,19 +229,17 @@ define dso_local void @test_iequc_sext_z_store(i8 zeroext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequc_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-BE-NEXT: srwi r3, r3, 5
-; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: stb r3, glob at toc@l(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequc_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-LE-NEXT: srwi r3, r3, 5
-; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: stb r3, glob at toc@l(r4)
; CHECK-LE-NEXT: blr
entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesiequi.ll b/llvm/test/CodeGen/PowerPC/testComparesiequi.ll
index a8ea8b5d942b2..7edf3b4b124ef 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesiequi.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiequi.ll
@@ -100,16 +100,14 @@ define dso_local signext i32 @test_iequi_sext_z(i32 zeroext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequi_sext_z:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: cntlzw r3, r3
-; CHECK-BE-NEXT: srwi r3, r3, 5
-; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequi_sext_z:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: cntlzw r3, r3
-; CHECK-LE-NEXT: srwi r3, r3, 5
-; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
@@ -231,19 +229,17 @@ define dso_local void @test_iequi_sext_z_store(i32 zeroext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequi_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-BE-NEXT: srwi r3, r3, 5
-; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: stw r3, glob at toc@l(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequi_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-LE-NEXT: srwi r3, r3, 5
-; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: stw r3, glob at toc@l(r4)
; CHECK-LE-NEXT: blr
entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesiequs.ll b/llvm/test/CodeGen/PowerPC/testComparesiequs.ll
index c8025880eb0ec..3f6be3f74ea15 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesiequs.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiequs.ll
@@ -100,16 +100,14 @@ define dso_local signext i32 @test_iequs_sext_z(i16 zeroext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequs_sext_z:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: cntlzw r3, r3
-; CHECK-BE-NEXT: srwi r3, r3, 5
-; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequs_sext_z:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: cntlzw r3, r3
-; CHECK-LE-NEXT: srwi r3, r3, 5
-; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
@@ -231,19 +229,17 @@ define dso_local void @test_iequs_sext_z_store(i16 zeroext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequs_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-BE-NEXT: srwi r3, r3, 5
-; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: sth r3, glob at toc@l(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequs_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-LE-NEXT: srwi r3, r3, 5
-; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: sth r3, glob at toc@l(r4)
; CHECK-LE-NEXT: blr
entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesileuc.ll b/llvm/test/CodeGen/PowerPC/testComparesileuc.ll
index 1b6d1ae17c9b0..6c78c41c462bd 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesileuc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesileuc.ll
@@ -53,9 +53,8 @@ entry:
define dso_local signext i32 @test_ileuc_sext_z(i8 zeroext %a) {
; CHECK-LABEL: test_ileuc_sext_z:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: addic r3, r3, -1
+; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ule i8 %a, 0
@@ -117,10 +116,9 @@ entry:
define dso_local void @test_ileuc_sext_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_ileuc_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: stb r3, glob at toc@l(r4)
; CHECK-NEXT: blr
entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesileui.ll b/llvm/test/CodeGen/PowerPC/testComparesileui.ll
index 4c1efde742db9..bd89710a44ab5 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesileui.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesileui.ll
@@ -53,9 +53,8 @@ entry:
define dso_local signext i32 @test_ileui_sext_z(i32 zeroext %a) {
; CHECK-LABEL: test_ileui_sext_z:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: addic r3, r3, -1
+; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
@@ -117,10 +116,9 @@ entry:
define dso_local void @test_ileui_sext_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_ileui_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: stw r3, glob at toc@l(r4)
; CHECK-NEXT: blr
entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesileus.ll b/llvm/test/CodeGen/PowerPC/testComparesileus.ll
index 31952081f3db9..a4cb1f21928d5 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesileus.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesileus.ll
@@ -53,9 +53,8 @@ entry:
define dso_local signext i32 @test_ileus_sext_z(i16 zeroext %a) {
; CHECK-LABEL: test_ileus_sext_z:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: addic r3, r3, -1
+; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ule i16 %a, 0
@@ -117,10 +116,9 @@ entry:
define dso_local void @test_ileus_sext_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_ileus_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: sth r3, glob at toc@l(r4)
; CHECK-NEXT: blr
entry:
diff --git a/llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll b/llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll
index 6184fe6845b50..1953756cde617 100644
--- a/llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll
+++ b/llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll
@@ -100,16 +100,16 @@ define i64 @test_lleqsc_sext_z(i8 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsc_sext_z:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: cntlzw r3, r3
-; CHECK-BE-NEXT: srwi r3, r3, 5
-; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: clrldi r3, r3, 56
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsc_sext_z:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: cntlzw r3, r3
-; CHECK-LE-NEXT: srwi r3, r3, 5
-; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: clrldi r3, r3, 56
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
@@ -231,19 +231,17 @@ define dso_local void @test_lleqsc_sext_z_store(i8 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsc_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-BE-NEXT: srwi r3, r3, 5
-; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: stb r3, glob at toc@l(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsc_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-LE-NEXT: srwi r3, r3, 5
-; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: stb r3, glob at toc@l(r4)
; CHECK-LE-NEXT: blr
entry:
diff --git a/llvm/test/CodeGen/PowerPC/testCompareslleqsi.ll b/llvm/test/CodeGen/PowerPC/testCompareslleqsi.ll
index c1d15c56bf976..958600bb40678 100644
--- a/llvm/test/CodeGen/PowerPC/testCompareslleqsi.ll
+++ b/llvm/test/CodeGen/PowerPC/testCompareslleqsi.ll
@@ -99,16 +99,16 @@ define i64 @test_lleqsi_sext_z(i32 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsi_sext_z:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: cntlzw r3, r3
-; CHECK-BE-NEXT: srwi r3, r3, 5
-; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: clrldi r3, r3, 32
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsi_sext_z:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: cntlzw r3, r3
-; CHECK-LE-NEXT: srwi r3, r3, 5
-; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: clrldi r3, r3, 32
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
@@ -230,19 +230,17 @@ define dso_local void @test_lleqsi_sext_z_store(i32 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsi_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-BE-NEXT: srwi r3, r3, 5
-; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: stw r3, glob at toc@l(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsi_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-LE-NEXT: srwi r3, r3, 5
-; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: stw r3, glob at toc@l(r4)
; CHECK-LE-NEXT: blr
entry:
diff --git a/llvm/test/CodeGen/PowerPC/testCompareslleqss.ll b/llvm/test/CodeGen/PowerPC/testCompareslleqss.ll
index d4d38232adb01..449f21bd49439 100644
--- a/llvm/test/CodeGen/PowerPC/testCompareslleqss.ll
+++ b/llvm/test/CodeGen/PowerPC/testCompareslleqss.ll
@@ -99,16 +99,16 @@ define i64 @test_lleqss_sext_z(i16 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqss_sext_z:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: cntlzw r3, r3
-; CHECK-BE-NEXT: srwi r3, r3, 5
-; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: clrldi r3, r3, 48
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqss_sext_z:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: cntlzw r3, r3
-; CHECK-LE-NEXT: srwi r3, r3, 5
-; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: clrldi r3, r3, 48
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
@@ -230,19 +230,17 @@ define dso_local void @test_lleqss_sext_z_store(i16 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqss_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-BE-NEXT: srwi r3, r3, 5
-; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: sth r3, glob at toc@l(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqss_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-LE-NEXT: srwi r3, r3, 5
-; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: sth r3, glob at toc@l(r4)
; CHECK-LE-NEXT: blr
entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllequc.ll b/llvm/test/CodeGen/PowerPC/testComparesllequc.ll
index 68dc0bde81942..c2fdd2cc41572 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesllequc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllequc.ll
@@ -99,16 +99,14 @@ define i64 @test_llequc_sext_z(i8 zeroext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequc_sext_z:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: cntlzw r3, r3
-; CHECK-BE-NEXT: srwi r3, r3, 5
-; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequc_sext_z:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: cntlzw r3, r3
-; CHECK-LE-NEXT: srwi r3, r3, 5
-; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
@@ -230,19 +228,17 @@ define dso_local void @test_llequc_sext_z_store(i8 zeroext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequc_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-BE-NEXT: srwi r3, r3, 5
-; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: stb r3, glob at toc@l(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequc_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-LE-NEXT: srwi r3, r3, 5
-; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: stb r3, glob at toc@l(r4)
; CHECK-LE-NEXT: blr
entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllequi.ll b/llvm/test/CodeGen/PowerPC/testComparesllequi.ll
index 70e9e62d84249..dc311b21a1094 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesllequi.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllequi.ll
@@ -99,16 +99,14 @@ define i64 @test_llequi_sext_z(i32 zeroext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequi_sext_z:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: cntlzw r3, r3
-; CHECK-BE-NEXT: srwi r3, r3, 5
-; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequi_sext_z:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: cntlzw r3, r3
-; CHECK-LE-NEXT: srwi r3, r3, 5
-; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
@@ -230,19 +228,17 @@ define dso_local void @test_llequi_sext_z_store(i32 zeroext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequi_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-BE-NEXT: srwi r3, r3, 5
-; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: stw r3, glob at toc@l(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequi_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-LE-NEXT: srwi r3, r3, 5
-; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: stw r3, glob at toc@l(r4)
; CHECK-LE-NEXT: blr
entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllequs.ll b/llvm/test/CodeGen/PowerPC/testComparesllequs.ll
index 37816e9b25243..840e6181f8fe6 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesllequs.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllequs.ll
@@ -99,16 +99,14 @@ define i64 @test_llequs_sext_z(i16 zeroext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequs_sext_z:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: cntlzw r3, r3
-; CHECK-BE-NEXT: srwi r3, r3, 5
-; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: addic r3, r3, -1
+; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequs_sext_z:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: cntlzw r3, r3
-; CHECK-LE-NEXT: srwi r3, r3, 5
-; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: addic r3, r3, -1
+; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
@@ -230,19 +228,17 @@ define dso_local void @test_llequs_sext_z_store(i16 zeroext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequs_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: cntlzw r3, r3
+; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-BE-NEXT: srwi r3, r3, 5
-; CHECK-BE-NEXT: neg r3, r3
+; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: sth r3, glob at toc@l(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_llequs_sext_z_store:
; CHECK-LE: # %bb.0: # %entry
-; CHECK-LE-NEXT: cntlzw r3, r3
+; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-LE-NEXT: srwi r3, r3, 5
-; CHECK-LE-NEXT: neg r3, r3
+; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: sth r3, glob at toc@l(r4)
; CHECK-LE-NEXT: blr
entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllleuc.ll b/llvm/test/CodeGen/PowerPC/testComparesllleuc.ll
index cfaa6e8fe1d83..8cfbdeea2eb68 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesllleuc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllleuc.ll
@@ -53,9 +53,8 @@ entry:
define i64 @test_llleuc_sext_z(i8 zeroext %a) {
; CHECK-LABEL: test_llleuc_sext_z:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: addic r3, r3, -1
+; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ule i8 %a, 0
@@ -117,10 +116,9 @@ entry:
define dso_local void @test_llleuc_sext_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_llleuc_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: stb r3, glob at toc@l(r4)
; CHECK-NEXT: blr
entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllleui.ll b/llvm/test/CodeGen/PowerPC/testComparesllleui.ll
index e438797cde772..73ca7808aab8b 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesllleui.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllleui.ll
@@ -53,9 +53,8 @@ entry:
define i64 @test_llleui_sext_z(i32 zeroext %a) {
; CHECK-LABEL: test_llleui_sext_z:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: addic r3, r3, -1
+; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ule i32 %a, 0
@@ -117,10 +116,9 @@ entry:
define dso_local void @test_llleui_sext_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_llleui_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: stw r3, glob at toc@l(r4)
; CHECK-NEXT: blr
entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllleus.ll b/llvm/test/CodeGen/PowerPC/testComparesllleus.ll
index 53b9b8a16d503..6bf51d3a5a767 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesllleus.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllleus.ll
@@ -53,9 +53,8 @@ entry:
define i64 @test_llleus_sext_z(i16 zeroext %a) {
; CHECK-LABEL: test_llleus_sext_z:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: cntlzw r3, r3
-; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: addic r3, r3, -1
+; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ule i16 %a, 0
@@ -117,10 +116,9 @@ entry:
define dso_local void @test_llleus_sext_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_llleus_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: addis r4, r2, glob at toc@ha
-; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: sth r3, glob at toc@l(r4)
; CHECK-NEXT: blr
entry:
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