[llvm] [NewPM] Adds a port for AArch64PreLegalizerCombiner (PR #190567)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 5 18:09:04 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: Anshul Nigham (nigham)
<details>
<summary>Changes</summary>
Standard porting (note that TargetPassConfig dependency was [removed earlier](https://github.com/llvm/llvm-project/commit/e27e7e433974b24c90fed9f0b646bed84e47681e)).
---
Patch is 111.25 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/190567.diff
121 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64.h (+15-1)
- (modified) llvm/lib/Target/AArch64/AArch64PassRegistry.def (+2)
- (modified) llvm/lib/Target/AArch64/AArch64TargetMachine.cpp (+1-1)
- (modified) llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp (+92-30)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-2-icmps-of-0-and-or.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-add-of-sub.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-addv.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-and-or-disjoint-mask.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-binop-neg.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-binop-undef-left-to-zero.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-build-vector.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-fcmp.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-icmp.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-cast.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-const-infinite-loop.mir (+2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-fp-const-lhs.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-int-const-lhs.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-const-fold-barrier-rhs.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-fma.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-fp-rounding.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-itofp-zero.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-copy.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-trunc.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-ext.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-extract-vec-elt.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-fabs.mir (+2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-flog2.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-fminimum-fmaximum.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-fminnum-fmaxnum.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-fneg.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-fpowi.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-fptrunc.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-freeze.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-fshl.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-fshr.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-fsqrt.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-of-binop-to-icmp-of-0.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-to-lhs-known-bits.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-inttoptr-ptrtoint.mir (+2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-logic-of-compare.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-mul-to-shl.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-mul.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-mulo-with-2.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-narrow-binop.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-neg-and-one-to-sext-inreg.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-op-trunc.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-overflow.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-ptradd-int2ptr.mir (+2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-ptradd-reassociation.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-ptrtoint.mir (+2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-same-op.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-sdiv.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir (+2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-shift-immed-mismatch-crash.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-shifts-undef.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-shufflevector.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-trunc.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-udivrem-use-bug.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-umulh-to-lshr.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-unary-undef-to-zero.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-use-vector-truncate-order.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/combine-vscale.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/fold-global-offsets-insertpt.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/fold-global-offsets-target-features.mir (+6)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/fold-global-offsets.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/lifetime-marker-no-dce.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/non-pow-2-extload-combine.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/observer-change-crash.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/opt-overlapping-and.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-addo-zero.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-binop-reassoc.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-conflict.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-crash.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-and-mask.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-or-pattern-align.mir (+2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-or-pattern.mir (+2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-mulo-zero.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-narrow-binop-feeding-add.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-select-to-fminmax.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-use-vector-truncate.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-ashr-shl-to-sext-inreg.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-binop-same-val.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-br.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-bzero.mir (+2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-commute-shift.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-concat-vectors.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-copy-prop-disabled.mir (+12)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir (+4)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-s1.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-funnel-shifts-to-rotates.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-hoist-same-hands.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-icmp-redundant-trunc.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-invert-cmp.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-not-really-equiv-insts.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-prop-extends-phi.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-ptradd-chain.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-select.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-sextload-from-sextinreg.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector-disjoint-mask.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector-undef-rhs.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-simplify-add.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-undef.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-xor-of-and-with-same-reg.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/uaddo-8-16-bits.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/extractvector-of-load.mir (+1)
- (modified) llvm/test/CodeGen/AArch64/extractvector-oob-load.mir (+1)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64.h b/llvm/lib/Target/AArch64/AArch64.h
index 6c3990842efb9..8a7c8680da63c 100644
--- a/llvm/lib/Target/AArch64/AArch64.h
+++ b/llvm/lib/Target/AArch64/AArch64.h
@@ -24,6 +24,7 @@
#include <memory>
struct AArch64O0PreLegalizerCombinerImplRuleConfig;
+struct AArch64PreLegalizerCombinerImplRuleConfig;
namespace llvm {
@@ -87,6 +88,19 @@ class AArch64O0PreLegalizerCombinerPass
MachineFunctionAnalysisManager &MFAM);
};
+class AArch64PreLegalizerCombinerPass
+ : public PassInfoMixin<AArch64PreLegalizerCombinerPass> {
+ std::unique_ptr<AArch64PreLegalizerCombinerImplRuleConfig> RuleConfig;
+
+public:
+ AArch64PreLegalizerCombinerPass();
+ AArch64PreLegalizerCombinerPass(AArch64PreLegalizerCombinerPass &&);
+ ~AArch64PreLegalizerCombinerPass();
+
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+};
+
FunctionPass *createAArch64O0PreLegalizerCombiner();
FunctionPass *createAArch64PreLegalizerCombiner();
FunctionPass *createAArch64PostLegalizerCombiner(bool IsOptNone);
@@ -119,7 +133,7 @@ void initializeAArch64PostCoalescerLegacyPass(PassRegistry &);
void initializeAArch64PostLegalizerCombinerPass(PassRegistry &);
void initializeAArch64PostLegalizerLoweringPass(PassRegistry &);
void initializeAArch64PostSelectOptimizePass(PassRegistry &);
-void initializeAArch64PreLegalizerCombinerPass(PassRegistry &);
+void initializeAArch64PreLegalizerCombinerLegacyPass(PassRegistry &);
void initializeAArch64PromoteConstantPass(PassRegistry&);
void initializeAArch64RedundantCopyEliminationPass(PassRegistry&);
void initializeAArch64RedundantCondBranchPass(PassRegistry &);
diff --git a/llvm/lib/Target/AArch64/AArch64PassRegistry.def b/llvm/lib/Target/AArch64/AArch64PassRegistry.def
index c5248f20b6f78..39085fc033c12 100644
--- a/llvm/lib/Target/AArch64/AArch64PassRegistry.def
+++ b/llvm/lib/Target/AArch64/AArch64PassRegistry.def
@@ -36,6 +36,8 @@ MACHINE_FUNCTION_PASS("aarch64-jump-tables", AArch64CompressJumpTablesPass())
MACHINE_FUNCTION_PASS("aarch64-ldst-opt", AArch64LoadStoreOptPass())
MACHINE_FUNCTION_PASS("aarch64-mi-peephole-opt", AArch64MIPeepholeOptPass())
MACHINE_FUNCTION_PASS("aarch64-post-coalescer", AArch64PostCoalescerPass())
+MACHINE_FUNCTION_PASS("aarch64-prelegalizer-combiner",
+ AArch64PreLegalizerCombinerPass())
MACHINE_FUNCTION_PASS("aarch64-ptrauth", AArch64PointerAuthPass())
MACHINE_FUNCTION_PASS("aarch64-simd-scalar", AArch64AdvSIMDScalarPass())
MACHINE_FUNCTION_PASS("aarch64-O0-prelegalizer-combiner",
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index 94fbe709d6fe1..950d274ceae75 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -258,7 +258,7 @@ LLVMInitializeAArch64Target() {
initializeAArch64MIPeepholeOptLegacyPass(PR);
initializeAArch64SIMDInstrOptPass(PR);
initializeAArch64O0PreLegalizerCombinerLegacyPass(PR);
- initializeAArch64PreLegalizerCombinerPass(PR);
+ initializeAArch64PreLegalizerCombinerLegacyPass(PR);
initializeAArch64PointerAuthLegacyPass(PR);
initializeAArch64PostCoalescerLegacyPass(PR);
initializeAArch64PostLegalizerCombinerPass(PR);
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
index cd35a27ea9e94..d872be652162b 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
@@ -11,6 +11,7 @@
//
//===----------------------------------------------------------------------===//
+#include "AArch64.h"
#include "AArch64GlobalISelUtils.h"
#include "AArch64TargetMachine.h"
#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
@@ -22,11 +23,15 @@
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/GlobalISel/Utils.h"
+#include "llvm/CodeGen/LibcallLoweringInfo.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/Instructions.h"
+#include <memory>
#define GET_GICOMBINER_DEPS
#include "AArch64GenPreLegalizeGICombiner.inc"
@@ -37,12 +42,12 @@
using namespace llvm;
using namespace MIPatternMatch;
-namespace {
-
#define GET_GICOMBINER_TYPES
#include "AArch64GenPreLegalizeGICombiner.inc"
#undef GET_GICOMBINER_TYPES
+namespace {
+
/// Try to match a G_ICMP of a G_TRUNC with zero, in which the truncated bits
/// are sign bits. In this case, we can transform the G_ICMP to directly compare
/// the wide value with a zero.
@@ -800,14 +805,38 @@ bool AArch64PreLegalizerCombinerImpl::tryCombineAll(MachineInstr &MI) const {
return false;
}
+bool runCombiner(MachineFunction &MF, GISelCSEInfo *CSEInfo,
+ GISelValueTracking *VT, MachineDominatorTree *MDT,
+ const LibcallLoweringInfo &Libcalls,
+ const AArch64PreLegalizerCombinerImplRuleConfig &RuleConfig,
+ bool EnableOpt) {
+ const AArch64Subtarget &ST = MF.getSubtarget<AArch64Subtarget>();
+ const auto *LI = ST.getLegalizerInfo();
+
+ const Function &F = MF.getFunction();
+
+ CombinerInfo CInfo(/*AllowIllegalOps=*/true, /*ShouldLegalizeIllegal=*/false,
+ /*LegalizerInfo=*/nullptr, EnableOpt, F.hasOptSize(),
+ F.hasMinSize());
+ // Disable fixed-point iteration to reduce compile-time
+ CInfo.MaxIterations = 1;
+ CInfo.ObserverLvl = CombinerInfo::ObserverLevel::SinglePass;
+ // This is the first Combiner, so the input IR might contain dead
+ // instructions.
+ CInfo.EnableFullDCE = true;
+ AArch64PreLegalizerCombinerImpl Impl(MF, CInfo, *VT, CSEInfo, RuleConfig, ST,
+ Libcalls, MDT, LI);
+ return Impl.combineMachineInstrs();
+}
+
// Pass boilerplate
// ================
-class AArch64PreLegalizerCombiner : public MachineFunctionPass {
+class AArch64PreLegalizerCombinerLegacy : public MachineFunctionPass {
public:
static char ID;
- AArch64PreLegalizerCombiner();
+ AArch64PreLegalizerCombinerLegacy();
StringRef getPassName() const override {
return "AArch64PreLegalizerCombiner";
@@ -822,7 +851,8 @@ class AArch64PreLegalizerCombiner : public MachineFunctionPass {
};
} // end anonymous namespace
-void AArch64PreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
+void AArch64PreLegalizerCombinerLegacy::getAnalysisUsage(
+ AnalysisUsage &AU) const {
AU.setPreservesCFG();
getSelectionDAGFallbackAnalysisUsage(AU);
AU.addRequired<GISelValueTrackingAnalysisLegacy>();
@@ -835,13 +865,14 @@ void AArch64PreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
MachineFunctionPass::getAnalysisUsage(AU);
}
-AArch64PreLegalizerCombiner::AArch64PreLegalizerCombiner()
+AArch64PreLegalizerCombinerLegacy::AArch64PreLegalizerCombinerLegacy()
: MachineFunctionPass(ID) {
if (!RuleConfig.parseCommandLineOption())
report_fatal_error("Invalid rule identifier");
}
-bool AArch64PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
+bool AArch64PreLegalizerCombinerLegacy::runOnMachineFunction(
+ MachineFunction &MF) {
if (MF.getProperties().hasFailedISel())
return false;
// Enable CSE.
@@ -851,47 +882,78 @@ bool AArch64PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
&Wrapper.get(getStandardCSEConfigForOpt(MF.getTarget().getOptLevel()));
const AArch64Subtarget &ST = MF.getSubtarget<AArch64Subtarget>();
- const auto *LI = ST.getLegalizerInfo();
-
- const Function &F = MF.getFunction();
-
const LibcallLoweringInfo &Libcalls =
getAnalysis<LibcallLoweringInfoWrapper>().getLibcallLowering(
- *F.getParent(), ST);
+ *MF.getFunction().getParent(), ST);
- bool EnableOpt =
- MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !skipFunction(F);
GISelValueTracking *VT =
&getAnalysis<GISelValueTrackingAnalysisLegacy>().get(MF);
MachineDominatorTree *MDT =
&getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
- CombinerInfo CInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
- /*LegalizerInfo*/ nullptr, EnableOpt, F.hasOptSize(),
- F.hasMinSize());
- // Disable fixed-point iteration to reduce compile-time
- CInfo.MaxIterations = 1;
- CInfo.ObserverLvl = CombinerInfo::ObserverLevel::SinglePass;
- // This is the first Combiner, so the input IR might contain dead
- // instructions.
- CInfo.EnableFullDCE = true;
- AArch64PreLegalizerCombinerImpl Impl(MF, CInfo, *VT, CSEInfo, RuleConfig, ST,
- Libcalls, MDT, LI);
- return Impl.combineMachineInstrs();
+ bool EnableOpt = MF.getTarget().getOptLevel() != CodeGenOptLevel::None &&
+ !skipFunction(MF.getFunction());
+ return runCombiner(MF, CSEInfo, VT, MDT, Libcalls, RuleConfig, EnableOpt);
}
-char AArch64PreLegalizerCombiner::ID = 0;
-INITIALIZE_PASS_BEGIN(AArch64PreLegalizerCombiner, DEBUG_TYPE,
+char AArch64PreLegalizerCombinerLegacy::ID = 0;
+INITIALIZE_PASS_BEGIN(AArch64PreLegalizerCombinerLegacy, DEBUG_TYPE,
"Combine AArch64 machine instrs before legalization",
false, false)
INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy)
INITIALIZE_PASS_DEPENDENCY(GISelCSEAnalysisWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LibcallLoweringInfoWrapper)
-INITIALIZE_PASS_END(AArch64PreLegalizerCombiner, DEBUG_TYPE,
+INITIALIZE_PASS_END(AArch64PreLegalizerCombinerLegacy, DEBUG_TYPE,
"Combine AArch64 machine instrs before legalization", false,
false)
+AArch64PreLegalizerCombinerPass::AArch64PreLegalizerCombinerPass()
+ : RuleConfig(
+ std::make_unique<AArch64PreLegalizerCombinerImplRuleConfig>()) {
+ if (!RuleConfig->parseCommandLineOption())
+ report_fatal_error("Invalid rule identifier");
+}
+
+AArch64PreLegalizerCombinerPass::AArch64PreLegalizerCombinerPass(
+ AArch64PreLegalizerCombinerPass &&) = default;
+
+AArch64PreLegalizerCombinerPass::~AArch64PreLegalizerCombinerPass() = default;
+
+PreservedAnalyses
+AArch64PreLegalizerCombinerPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ if (MF.getProperties().hasFailedISel())
+ return PreservedAnalyses::all();
+
+ auto *CSEInfo = MFAM.getResult<GISelCSEAnalysis>(MF).get();
+ GISelValueTracking &VT = MFAM.getResult<GISelValueTrackingAnalysis>(MF);
+ MachineDominatorTree &MDT = MFAM.getResult<MachineDominatorTreeAnalysis>(MF);
+
+ const AArch64Subtarget &ST = MF.getSubtarget<AArch64Subtarget>();
+ auto &MAMProxy =
+ MFAM.getResult<ModuleAnalysisManagerMachineFunctionProxy>(MF);
+ const LibcallLoweringModuleAnalysisResult *LibcallResult =
+ MAMProxy.getCachedResult<LibcallLoweringModuleAnalysis>(
+ *MF.getFunction().getParent());
+ if (!LibcallResult)
+ reportFatalUsageError("LibcallLoweringModuleAnalysis result not available");
+
+ const LibcallLoweringInfo &Libcalls = LibcallResult->getLibcallLowering(ST);
+
+ bool EnableOpt = MF.getTarget().getOptLevel() != CodeGenOptLevel::None;
+
+ if (!runCombiner(MF, CSEInfo, &VT, &MDT, Libcalls, *RuleConfig, EnableOpt))
+ return PreservedAnalyses::all();
+
+ PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ PA.preserve<GISelValueTrackingAnalysis>();
+ PA.preserve<MachineDominatorTreeAnalysis>();
+ PA.preserve<GISelCSEAnalysis>();
+ return PA;
+}
+
namespace llvm {
FunctionPass *createAArch64PreLegalizerCombiner() {
- return new AArch64PreLegalizerCombiner();
+ return new AArch64PreLegalizerCombinerLegacy();
}
} // end namespace llvm
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-2-icmps-of-0-and-or.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-2-icmps-of-0-and-or.mir
index 2ce5c693f3dbc..0d1831c8043dd 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-2-icmps-of-0-and-or.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-2-icmps-of-0-and-or.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
# REQUIRES: asserts
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-add-of-sub.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-add-of-sub.mir
index 6bd1d996da85f..137140e706d4b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-add-of-sub.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-add-of-sub.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir
index dc1a81f23d733..595568f921f73 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
---
name: add_lhs_sub_reg
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-addv.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-addv.mir
index 9482dc3c41063..8bc6e75954217 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-addv.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-addv.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -mtriple aarch64-unknown-unknown -mattr=+dotprod %s -o - | FileCheck %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown -mattr=+dotprod %s -o - | FileCheck %s
---
name: vecreduce_intrinsic
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-and-or-disjoint-mask.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-and-or-disjoint-mask.mir
index 82f387cddf2a3..fe50bf2b2675c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-and-or-disjoint-mask.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-and-or-disjoint-mask.mir
@@ -1,6 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner --aarch64prelegalizercombiner-only-enable-rule="and_or_disjoint_mask" -global-isel -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' --aarch64prelegalizercombiner-only-enable-rule="and_or_disjoint_mask" -global-isel %s -o - | FileCheck %s
# REQUIRES: asserts
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-binop-neg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-binop-neg.mir
index 4e0bf7cd7bb4e..371ff4696398b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-binop-neg.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-binop-neg.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
---
name: binop_with_neg_or
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-binop-undef-left-to-zero.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-binop-undef-left-to-zero.mir
index e7ddda957a54f..16d785c21316f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-binop-undef-left-to-zero.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-binop-undef-left-to-zero.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -o - -mtriple=aarch64-unknown-unknown -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s | FileCheck %s
---
name: test_combine_shl_undef_x_s32
body: |
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-build-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-build-vector.mir
index 5189582d0b6ac..ba1e165998160 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-build-vector.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-build-vector.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -o - -mtriple=aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s | FileCheck %s
---
name: full_extracts_from_build_vector
alignment: 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-fcmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-fcmp.mir
index 8c9885ef37934..d0a10b88a1f2a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-fcmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-fcmp.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s --check-prefixes=CHECK
+# RUN: llc -o - -mtriple=aarch64-unknown-unknown -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s | FileCheck %s --check-prefixes=CHECK
---
name: test_fcmp_canon
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-icmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-icmp.mir
index 3da5844d994dc..5f7bc181c1626 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-icmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-icmp.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s --check-prefixes=CHECK
+# RUN: llc -o - -mtriple=aarch64-unknown-unknown -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s | FileCheck %s --check-prefixes=CHECK
---
name: test_icmp_canon
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-cast.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-cast.mir
index 8eab47171e0d1..9ec19069e3983 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-cast.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-cast.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s --check-prefixes=CHECK,CHECK-PRE
+# RUN: llc -o - -mtriple=aarch64-u...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/190567
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