[llvm] [NewPM] Adds a port for AArch64PreLegalizerCombiner (PR #190567)
Anshul Nigham via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 5 18:08:33 PDT 2026
https://github.com/nigham created https://github.com/llvm/llvm-project/pull/190567
Standard porting (note that TargetPassConfig dependency was [removed earlier](https://github.com/llvm/llvm-project/commit/e27e7e433974b24c90fed9f0b646bed84e47681e)).
>From 8b75d4e1996b401a1f9144275c8537d4319370cc Mon Sep 17 00:00:00 2001
From: Anshul Nigham <nigham at google.com>
Date: Sun, 5 Apr 2026 18:06:10 -0700
Subject: [PATCH] [NewPM] Adds a port for AArch64PreLegalizerCombiner
---
llvm/lib/Target/AArch64/AArch64.h | 16 ++-
.../Target/AArch64/AArch64PassRegistry.def | 2 +
.../Target/AArch64/AArch64TargetMachine.cpp | 2 +-
.../GISel/AArch64PreLegalizerCombiner.cpp | 122 +++++++++++++-----
.../combine-2-icmps-of-0-and-or.mir | 1 +
.../AArch64/GlobalISel/combine-add-of-sub.mir | 1 +
.../AArch64/GlobalISel/combine-add.mir | 1 +
.../AArch64/GlobalISel/combine-addv.mir | 1 +
.../combine-and-or-disjoint-mask.mir | 1 +
.../AArch64/GlobalISel/combine-binop-neg.mir | 1 +
.../combine-binop-undef-left-to-zero.mir | 1 +
.../GlobalISel/combine-build-vector.mir | 1 +
.../GlobalISel/combine-canonicalize-fcmp.mir | 1 +
.../GlobalISel/combine-canonicalize-icmp.mir | 1 +
.../AArch64/GlobalISel/combine-cast.mir | 1 +
.../combine-commute-const-infinite-loop.mir | 2 +
.../combine-commute-fp-const-lhs.mir | 1 +
.../combine-commute-int-const-lhs.mir | 1 +
.../combine-const-fold-barrier-rhs.mir | 1 +
.../GlobalISel/combine-constant-fold-fma.mir | 1 +
.../combine-constant-fold-fp-rounding.mir | 1 +
.../combine-constant-fold-itofp-zero.mir | 1 +
.../AArch64/GlobalISel/combine-copy.mir | 1 +
.../AArch64/GlobalISel/combine-ext-trunc.mir | 1 +
.../AArch64/GlobalISel/combine-ext.mir | 1 +
.../GlobalISel/combine-extract-vec-elt.mir | 1 +
.../AArch64/GlobalISel/combine-fabs.mir | 2 +
.../AArch64/GlobalISel/combine-flog2.mir | 1 +
.../GlobalISel/combine-fminimum-fmaximum.mir | 1 +
.../GlobalISel/combine-fminnum-fmaxnum.mir | 1 +
.../AArch64/GlobalISel/combine-fneg.mir | 1 +
.../AArch64/GlobalISel/combine-fpowi.mir | 1 +
.../AArch64/GlobalISel/combine-fptrunc.mir | 1 +
.../AArch64/GlobalISel/combine-freeze.mir | 1 +
.../AArch64/GlobalISel/combine-fshl.mir | 1 +
.../AArch64/GlobalISel/combine-fshr.mir | 1 +
.../AArch64/GlobalISel/combine-fsqrt.mir | 1 +
.../combine-icmp-of-binop-to-icmp-of-0.mir | 1 +
.../combine-icmp-to-lhs-known-bits.mir | 1 +
.../GlobalISel/combine-insert-vec-elt.mir | 1 +
.../AArch64/GlobalISel/combine-integer.mir | 1 +
.../GlobalISel/combine-inttoptr-ptrtoint.mir | 2 +
.../GlobalISel/combine-logic-of-compare.mir | 1 +
.../AArch64/GlobalISel/combine-mul-to-shl.mir | 1 +
.../AArch64/GlobalISel/combine-mul.mir | 1 +
.../GlobalISel/combine-mulo-with-2.mir | 1 +
.../GlobalISel/combine-narrow-binop.mir | 1 +
.../combine-neg-and-one-to-sext-inreg.mir | 1 +
.../AArch64/GlobalISel/combine-op-trunc.mir | 1 +
.../AArch64/GlobalISel/combine-overflow.mir | 1 +
.../GlobalISel/combine-ptradd-int2ptr.mir | 2 +
.../combine-ptradd-reassociation.mir | 1 +
.../AArch64/GlobalISel/combine-ptrtoint.mir | 2 +
.../AArch64/GlobalISel/combine-same-op.mir | 1 +
.../AArch64/GlobalISel/combine-sdiv.mir | 1 +
.../AArch64/GlobalISel/combine-select.mir | 2 +
.../combine-shift-immed-mismatch-crash.mir | 1 +
.../GlobalISel/combine-shifts-undef.mir | 1 +
.../GlobalISel/combine-shufflevector.mir | 1 +
.../AArch64/GlobalISel/combine-sub.mir | 1 +
.../AArch64/GlobalISel/combine-trunc.mir | 1 +
.../AArch64/GlobalISel/combine-udiv.mir | 1 +
.../GlobalISel/combine-udivrem-use-bug.mir | 1 +
.../GlobalISel/combine-umulh-to-lshr.mir | 1 +
.../combine-unary-undef-to-zero.mir | 1 +
.../AArch64/GlobalISel/combine-unmerge.mir | 1 +
.../combine-use-vector-truncate-order.mir | 1 +
.../AArch64/GlobalISel/combine-vscale.mir | 1 +
.../fold-global-offsets-insertpt.mir | 1 +
.../fold-global-offsets-target-features.mir | 6 +
.../GlobalISel/fold-global-offsets.mir | 1 +
.../GlobalISel/inline-memcpy-forced.mir | 1 +
.../AArch64/GlobalISel/inline-memcpy.mir | 1 +
.../AArch64/GlobalISel/inline-memmove.mir | 1 +
.../AArch64/GlobalISel/inline-memset.mir | 1 +
.../GlobalISel/inline-small-memcpy.mir | 1 +
.../GlobalISel/lifetime-marker-no-dce.mir | 1 +
.../GlobalISel/non-pow-2-extload-combine.mir | 1 +
.../GlobalISel/observer-change-crash.mir | 1 +
.../GlobalISel/opt-overlapping-and.mir | 1 +
.../prelegalizer-combiner-addo-zero.mir | 1 +
.../prelegalizer-combiner-binop-reassoc.mir | 1 +
...izer-combiner-divrem-insertpt-conflict.mir | 1 +
...galizer-combiner-divrem-insertpt-crash.mir | 1 +
...combiner-icmp-to-true-false-known-bits.mir | 1 +
.../prelegalizer-combiner-load-and-mask.mir | 1 +
...galizer-combiner-load-or-pattern-align.mir | 2 +
.../prelegalizer-combiner-load-or-pattern.mir | 2 +
.../prelegalizer-combiner-mulo-zero.mir | 1 +
...izer-combiner-narrow-binop-feeding-add.mir | 1 +
...relegalizer-combiner-select-to-fminmax.mir | 1 +
...legalizer-combiner-use-vector-truncate.mir | 1 +
...galizercombiner-ashr-shl-to-sext-inreg.mir | 1 +
.../prelegalizercombiner-binop-same-val.mir | 1 +
.../GlobalISel/prelegalizercombiner-br.mir | 1 +
.../GlobalISel/prelegalizercombiner-bzero.mir | 2 +
.../prelegalizercombiner-commute-shift.mir | 1 +
.../prelegalizercombiner-concat-vectors.mir | 1 +
...relegalizercombiner-copy-prop-disabled.mir | 12 ++
...ercombiner-extending-loads-cornercases.mir | 4 +
...relegalizercombiner-extending-loads-s1.mir | 1 +
.../prelegalizercombiner-extending-loads.mir | 1 +
...lizercombiner-funnel-shifts-to-rotates.mir | 1 +
.../prelegalizercombiner-hoist-same-hands.mir | 1 +
...legalizercombiner-icmp-redundant-trunc.mir | 1 +
.../prelegalizercombiner-invert-cmp.mir | 1 +
...galizercombiner-not-really-equiv-insts.mir | 1 +
.../prelegalizercombiner-prop-extends-phi.mir | 1 +
.../prelegalizercombiner-ptradd-chain.mir | 1 +
.../prelegalizercombiner-select.mir | 1 +
...alizercombiner-sextload-from-sextinreg.mir | 1 +
...rcombiner-shuffle-vector-disjoint-mask.mir | 1 +
...lizercombiner-shuffle-vector-undef-rhs.mir | 1 +
.../prelegalizercombiner-shuffle-vector.mir | 1 +
.../prelegalizercombiner-simplify-add.mir | 1 +
.../prelegalizercombiner-trivial-arith.mir | 1 +
.../GlobalISel/prelegalizercombiner-undef.mir | 1 +
...lizercombiner-xor-of-and-with-same-reg.mir | 1 +
.../AArch64/GlobalISel/uaddo-8-16-bits.mir | 1 +
.../CodeGen/AArch64/extractvector-of-load.mir | 1 +
.../AArch64/extractvector-oob-load.mir | 1 +
121 files changed, 255 insertions(+), 32 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64.h b/llvm/lib/Target/AArch64/AArch64.h
index 6c3990842efb9..8a7c8680da63c 100644
--- a/llvm/lib/Target/AArch64/AArch64.h
+++ b/llvm/lib/Target/AArch64/AArch64.h
@@ -24,6 +24,7 @@
#include <memory>
struct AArch64O0PreLegalizerCombinerImplRuleConfig;
+struct AArch64PreLegalizerCombinerImplRuleConfig;
namespace llvm {
@@ -87,6 +88,19 @@ class AArch64O0PreLegalizerCombinerPass
MachineFunctionAnalysisManager &MFAM);
};
+class AArch64PreLegalizerCombinerPass
+ : public PassInfoMixin<AArch64PreLegalizerCombinerPass> {
+ std::unique_ptr<AArch64PreLegalizerCombinerImplRuleConfig> RuleConfig;
+
+public:
+ AArch64PreLegalizerCombinerPass();
+ AArch64PreLegalizerCombinerPass(AArch64PreLegalizerCombinerPass &&);
+ ~AArch64PreLegalizerCombinerPass();
+
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+};
+
FunctionPass *createAArch64O0PreLegalizerCombiner();
FunctionPass *createAArch64PreLegalizerCombiner();
FunctionPass *createAArch64PostLegalizerCombiner(bool IsOptNone);
@@ -119,7 +133,7 @@ void initializeAArch64PostCoalescerLegacyPass(PassRegistry &);
void initializeAArch64PostLegalizerCombinerPass(PassRegistry &);
void initializeAArch64PostLegalizerLoweringPass(PassRegistry &);
void initializeAArch64PostSelectOptimizePass(PassRegistry &);
-void initializeAArch64PreLegalizerCombinerPass(PassRegistry &);
+void initializeAArch64PreLegalizerCombinerLegacyPass(PassRegistry &);
void initializeAArch64PromoteConstantPass(PassRegistry&);
void initializeAArch64RedundantCopyEliminationPass(PassRegistry&);
void initializeAArch64RedundantCondBranchPass(PassRegistry &);
diff --git a/llvm/lib/Target/AArch64/AArch64PassRegistry.def b/llvm/lib/Target/AArch64/AArch64PassRegistry.def
index c5248f20b6f78..39085fc033c12 100644
--- a/llvm/lib/Target/AArch64/AArch64PassRegistry.def
+++ b/llvm/lib/Target/AArch64/AArch64PassRegistry.def
@@ -36,6 +36,8 @@ MACHINE_FUNCTION_PASS("aarch64-jump-tables", AArch64CompressJumpTablesPass())
MACHINE_FUNCTION_PASS("aarch64-ldst-opt", AArch64LoadStoreOptPass())
MACHINE_FUNCTION_PASS("aarch64-mi-peephole-opt", AArch64MIPeepholeOptPass())
MACHINE_FUNCTION_PASS("aarch64-post-coalescer", AArch64PostCoalescerPass())
+MACHINE_FUNCTION_PASS("aarch64-prelegalizer-combiner",
+ AArch64PreLegalizerCombinerPass())
MACHINE_FUNCTION_PASS("aarch64-ptrauth", AArch64PointerAuthPass())
MACHINE_FUNCTION_PASS("aarch64-simd-scalar", AArch64AdvSIMDScalarPass())
MACHINE_FUNCTION_PASS("aarch64-O0-prelegalizer-combiner",
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index 94fbe709d6fe1..950d274ceae75 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -258,7 +258,7 @@ LLVMInitializeAArch64Target() {
initializeAArch64MIPeepholeOptLegacyPass(PR);
initializeAArch64SIMDInstrOptPass(PR);
initializeAArch64O0PreLegalizerCombinerLegacyPass(PR);
- initializeAArch64PreLegalizerCombinerPass(PR);
+ initializeAArch64PreLegalizerCombinerLegacyPass(PR);
initializeAArch64PointerAuthLegacyPass(PR);
initializeAArch64PostCoalescerLegacyPass(PR);
initializeAArch64PostLegalizerCombinerPass(PR);
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
index cd35a27ea9e94..d872be652162b 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
@@ -11,6 +11,7 @@
//
//===----------------------------------------------------------------------===//
+#include "AArch64.h"
#include "AArch64GlobalISelUtils.h"
#include "AArch64TargetMachine.h"
#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
@@ -22,11 +23,15 @@
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/GlobalISel/Utils.h"
+#include "llvm/CodeGen/LibcallLoweringInfo.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/Instructions.h"
+#include <memory>
#define GET_GICOMBINER_DEPS
#include "AArch64GenPreLegalizeGICombiner.inc"
@@ -37,12 +42,12 @@
using namespace llvm;
using namespace MIPatternMatch;
-namespace {
-
#define GET_GICOMBINER_TYPES
#include "AArch64GenPreLegalizeGICombiner.inc"
#undef GET_GICOMBINER_TYPES
+namespace {
+
/// Try to match a G_ICMP of a G_TRUNC with zero, in which the truncated bits
/// are sign bits. In this case, we can transform the G_ICMP to directly compare
/// the wide value with a zero.
@@ -800,14 +805,38 @@ bool AArch64PreLegalizerCombinerImpl::tryCombineAll(MachineInstr &MI) const {
return false;
}
+bool runCombiner(MachineFunction &MF, GISelCSEInfo *CSEInfo,
+ GISelValueTracking *VT, MachineDominatorTree *MDT,
+ const LibcallLoweringInfo &Libcalls,
+ const AArch64PreLegalizerCombinerImplRuleConfig &RuleConfig,
+ bool EnableOpt) {
+ const AArch64Subtarget &ST = MF.getSubtarget<AArch64Subtarget>();
+ const auto *LI = ST.getLegalizerInfo();
+
+ const Function &F = MF.getFunction();
+
+ CombinerInfo CInfo(/*AllowIllegalOps=*/true, /*ShouldLegalizeIllegal=*/false,
+ /*LegalizerInfo=*/nullptr, EnableOpt, F.hasOptSize(),
+ F.hasMinSize());
+ // Disable fixed-point iteration to reduce compile-time
+ CInfo.MaxIterations = 1;
+ CInfo.ObserverLvl = CombinerInfo::ObserverLevel::SinglePass;
+ // This is the first Combiner, so the input IR might contain dead
+ // instructions.
+ CInfo.EnableFullDCE = true;
+ AArch64PreLegalizerCombinerImpl Impl(MF, CInfo, *VT, CSEInfo, RuleConfig, ST,
+ Libcalls, MDT, LI);
+ return Impl.combineMachineInstrs();
+}
+
// Pass boilerplate
// ================
-class AArch64PreLegalizerCombiner : public MachineFunctionPass {
+class AArch64PreLegalizerCombinerLegacy : public MachineFunctionPass {
public:
static char ID;
- AArch64PreLegalizerCombiner();
+ AArch64PreLegalizerCombinerLegacy();
StringRef getPassName() const override {
return "AArch64PreLegalizerCombiner";
@@ -822,7 +851,8 @@ class AArch64PreLegalizerCombiner : public MachineFunctionPass {
};
} // end anonymous namespace
-void AArch64PreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
+void AArch64PreLegalizerCombinerLegacy::getAnalysisUsage(
+ AnalysisUsage &AU) const {
AU.setPreservesCFG();
getSelectionDAGFallbackAnalysisUsage(AU);
AU.addRequired<GISelValueTrackingAnalysisLegacy>();
@@ -835,13 +865,14 @@ void AArch64PreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
MachineFunctionPass::getAnalysisUsage(AU);
}
-AArch64PreLegalizerCombiner::AArch64PreLegalizerCombiner()
+AArch64PreLegalizerCombinerLegacy::AArch64PreLegalizerCombinerLegacy()
: MachineFunctionPass(ID) {
if (!RuleConfig.parseCommandLineOption())
report_fatal_error("Invalid rule identifier");
}
-bool AArch64PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
+bool AArch64PreLegalizerCombinerLegacy::runOnMachineFunction(
+ MachineFunction &MF) {
if (MF.getProperties().hasFailedISel())
return false;
// Enable CSE.
@@ -851,47 +882,78 @@ bool AArch64PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
&Wrapper.get(getStandardCSEConfigForOpt(MF.getTarget().getOptLevel()));
const AArch64Subtarget &ST = MF.getSubtarget<AArch64Subtarget>();
- const auto *LI = ST.getLegalizerInfo();
-
- const Function &F = MF.getFunction();
-
const LibcallLoweringInfo &Libcalls =
getAnalysis<LibcallLoweringInfoWrapper>().getLibcallLowering(
- *F.getParent(), ST);
+ *MF.getFunction().getParent(), ST);
- bool EnableOpt =
- MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !skipFunction(F);
GISelValueTracking *VT =
&getAnalysis<GISelValueTrackingAnalysisLegacy>().get(MF);
MachineDominatorTree *MDT =
&getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
- CombinerInfo CInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
- /*LegalizerInfo*/ nullptr, EnableOpt, F.hasOptSize(),
- F.hasMinSize());
- // Disable fixed-point iteration to reduce compile-time
- CInfo.MaxIterations = 1;
- CInfo.ObserverLvl = CombinerInfo::ObserverLevel::SinglePass;
- // This is the first Combiner, so the input IR might contain dead
- // instructions.
- CInfo.EnableFullDCE = true;
- AArch64PreLegalizerCombinerImpl Impl(MF, CInfo, *VT, CSEInfo, RuleConfig, ST,
- Libcalls, MDT, LI);
- return Impl.combineMachineInstrs();
+ bool EnableOpt = MF.getTarget().getOptLevel() != CodeGenOptLevel::None &&
+ !skipFunction(MF.getFunction());
+ return runCombiner(MF, CSEInfo, VT, MDT, Libcalls, RuleConfig, EnableOpt);
}
-char AArch64PreLegalizerCombiner::ID = 0;
-INITIALIZE_PASS_BEGIN(AArch64PreLegalizerCombiner, DEBUG_TYPE,
+char AArch64PreLegalizerCombinerLegacy::ID = 0;
+INITIALIZE_PASS_BEGIN(AArch64PreLegalizerCombinerLegacy, DEBUG_TYPE,
"Combine AArch64 machine instrs before legalization",
false, false)
INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy)
INITIALIZE_PASS_DEPENDENCY(GISelCSEAnalysisWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LibcallLoweringInfoWrapper)
-INITIALIZE_PASS_END(AArch64PreLegalizerCombiner, DEBUG_TYPE,
+INITIALIZE_PASS_END(AArch64PreLegalizerCombinerLegacy, DEBUG_TYPE,
"Combine AArch64 machine instrs before legalization", false,
false)
+AArch64PreLegalizerCombinerPass::AArch64PreLegalizerCombinerPass()
+ : RuleConfig(
+ std::make_unique<AArch64PreLegalizerCombinerImplRuleConfig>()) {
+ if (!RuleConfig->parseCommandLineOption())
+ report_fatal_error("Invalid rule identifier");
+}
+
+AArch64PreLegalizerCombinerPass::AArch64PreLegalizerCombinerPass(
+ AArch64PreLegalizerCombinerPass &&) = default;
+
+AArch64PreLegalizerCombinerPass::~AArch64PreLegalizerCombinerPass() = default;
+
+PreservedAnalyses
+AArch64PreLegalizerCombinerPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ if (MF.getProperties().hasFailedISel())
+ return PreservedAnalyses::all();
+
+ auto *CSEInfo = MFAM.getResult<GISelCSEAnalysis>(MF).get();
+ GISelValueTracking &VT = MFAM.getResult<GISelValueTrackingAnalysis>(MF);
+ MachineDominatorTree &MDT = MFAM.getResult<MachineDominatorTreeAnalysis>(MF);
+
+ const AArch64Subtarget &ST = MF.getSubtarget<AArch64Subtarget>();
+ auto &MAMProxy =
+ MFAM.getResult<ModuleAnalysisManagerMachineFunctionProxy>(MF);
+ const LibcallLoweringModuleAnalysisResult *LibcallResult =
+ MAMProxy.getCachedResult<LibcallLoweringModuleAnalysis>(
+ *MF.getFunction().getParent());
+ if (!LibcallResult)
+ reportFatalUsageError("LibcallLoweringModuleAnalysis result not available");
+
+ const LibcallLoweringInfo &Libcalls = LibcallResult->getLibcallLowering(ST);
+
+ bool EnableOpt = MF.getTarget().getOptLevel() != CodeGenOptLevel::None;
+
+ if (!runCombiner(MF, CSEInfo, &VT, &MDT, Libcalls, *RuleConfig, EnableOpt))
+ return PreservedAnalyses::all();
+
+ PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ PA.preserve<GISelValueTrackingAnalysis>();
+ PA.preserve<MachineDominatorTreeAnalysis>();
+ PA.preserve<GISelCSEAnalysis>();
+ return PA;
+}
+
namespace llvm {
FunctionPass *createAArch64PreLegalizerCombiner() {
- return new AArch64PreLegalizerCombiner();
+ return new AArch64PreLegalizerCombinerLegacy();
}
} // end namespace llvm
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-2-icmps-of-0-and-or.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-2-icmps-of-0-and-or.mir
index 2ce5c693f3dbc..0d1831c8043dd 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-2-icmps-of-0-and-or.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-2-icmps-of-0-and-or.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
# REQUIRES: asserts
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-add-of-sub.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-add-of-sub.mir
index 6bd1d996da85f..137140e706d4b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-add-of-sub.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-add-of-sub.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir
index dc1a81f23d733..595568f921f73 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
---
name: add_lhs_sub_reg
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-addv.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-addv.mir
index 9482dc3c41063..8bc6e75954217 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-addv.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-addv.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -mtriple aarch64-unknown-unknown -mattr=+dotprod %s -o - | FileCheck %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown -mattr=+dotprod %s -o - | FileCheck %s
---
name: vecreduce_intrinsic
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-and-or-disjoint-mask.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-and-or-disjoint-mask.mir
index 82f387cddf2a3..fe50bf2b2675c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-and-or-disjoint-mask.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-and-or-disjoint-mask.mir
@@ -1,6 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner --aarch64prelegalizercombiner-only-enable-rule="and_or_disjoint_mask" -global-isel -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' --aarch64prelegalizercombiner-only-enable-rule="and_or_disjoint_mask" -global-isel %s -o - | FileCheck %s
# REQUIRES: asserts
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-binop-neg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-binop-neg.mir
index 4e0bf7cd7bb4e..371ff4696398b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-binop-neg.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-binop-neg.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
---
name: binop_with_neg_or
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-binop-undef-left-to-zero.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-binop-undef-left-to-zero.mir
index e7ddda957a54f..16d785c21316f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-binop-undef-left-to-zero.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-binop-undef-left-to-zero.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -o - -mtriple=aarch64-unknown-unknown -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s | FileCheck %s
---
name: test_combine_shl_undef_x_s32
body: |
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-build-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-build-vector.mir
index 5189582d0b6ac..ba1e165998160 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-build-vector.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-build-vector.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -o - -mtriple=aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s | FileCheck %s
---
name: full_extracts_from_build_vector
alignment: 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-fcmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-fcmp.mir
index 8c9885ef37934..d0a10b88a1f2a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-fcmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-fcmp.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s --check-prefixes=CHECK
+# RUN: llc -o - -mtriple=aarch64-unknown-unknown -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s | FileCheck %s --check-prefixes=CHECK
---
name: test_fcmp_canon
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-icmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-icmp.mir
index 3da5844d994dc..5f7bc181c1626 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-icmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-icmp.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s --check-prefixes=CHECK
+# RUN: llc -o - -mtriple=aarch64-unknown-unknown -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s | FileCheck %s --check-prefixes=CHECK
---
name: test_icmp_canon
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-cast.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-cast.mir
index 8eab47171e0d1..9ec19069e3983 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-cast.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-cast.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s --check-prefixes=CHECK,CHECK-PRE
+# RUN: llc -o - -mtriple=aarch64-unknown-unknown -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s | FileCheck %s --check-prefixes=CHECK,CHECK-PRE
# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s | FileCheck %s --check-prefixes=CHECK,CHECK-POST
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-const-infinite-loop.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-const-infinite-loop.mir
index 6efdc5e5e8c36..2cc81fde53a66 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-const-infinite-loop.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-const-infinite-loop.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner %s -o - \
# RUN: --aarch64prelegalizercombiner-disable-rule=constant_fold_binop | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - \
+# RUN: --aarch64prelegalizercombiner-disable-rule=constant_fold_binop | FileCheck %s
# REQUIRES: asserts
# `constant_fold_binop` is disabled to trigger the infinite loop in `commute_int_constant_to_rhs`.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-fp-const-lhs.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-fp-const-lhs.mir
index d791660b7a5eb..6287d25c20191 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-fp-const-lhs.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-fp-const-lhs.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
---
name: fadd
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-int-const-lhs.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-int-const-lhs.mir
index 16365494f5f4e..a7be4bffa3db4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-int-const-lhs.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-commute-int-const-lhs.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
---
name: add
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-const-fold-barrier-rhs.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-const-fold-barrier-rhs.mir
index c967e4f2ea5e8..78dbc668ae38d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-const-fold-barrier-rhs.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-const-fold-barrier-rhs.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
---
name: cfb_lhs
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-fma.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-fma.mir
index 73e03282f6c7f..0325cb1d14555 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-fma.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-fma.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
---
name: fma
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-fp-rounding.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-fp-rounding.mir
index 7318fa0ca3b57..b42cfa0737843 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-fp-rounding.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-fp-rounding.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
---
name: fceil
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-itofp-zero.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-itofp-zero.mir
index b696cdf3cb28a..15f9e7e0d1903 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-itofp-zero.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-constant-fold-itofp-zero.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
---
name: sitofp
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-copy.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-copy.mir
index 27b629f6e32ee..65725ba1b7d1d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-copy.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-copy.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64 -run-pass=aarch64-prelegalizer-combiner %s | FileCheck %s
+# RUN: llc -o - -mtriple=aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s | FileCheck %s
# Make sure we don't lose the register bank constraints when
# combining COPY instructions.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-trunc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-trunc.mir
index d034ec18aa271..d3c50deae6c09 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-trunc.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-trunc.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
---
name: zext_trunc_nuw
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext.mir
index 629238126380c..72dc2c2f3614d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-ext.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -o - -mtriple=aarch64-unknown-unknown -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s | FileCheck %s
---
name: test_combine_anyext_trunc
body: |
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-extract-vec-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-extract-vec-elt.mir
index e81447a1de4b6..7cf34958ec6de 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-extract-vec-elt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-extract-vec-elt.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -o - -mtriple=aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s | FileCheck %s
---
name: extract_from_build_vector
alignment: 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fabs.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fabs.mir
index d2f73675e9439..c3227d4988558 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fabs.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fabs.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
# RUN: llc -debugify-and-strip-all-safe -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -debugify-and-strip-all-safe -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
---
name: test_combine_fabs_fabs
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-flog2.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-flog2.mir
index dfa131fc396d7..51259f92d4e55 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-flog2.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-flog2.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
---
name: test_combine_half_flog2_constant
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fminimum-fmaximum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fminimum-fmaximum.mir
index 6e675c00d846b..429866e0881d2 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fminimum-fmaximum.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fminimum-fmaximum.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
---
name: test_combine_nan_rhs_fminimum_half
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fminnum-fmaxnum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fminnum-fmaxnum.mir
index 9f93205a38a5b..95de61a5a1803 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fminnum-fmaxnum.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fminnum-fmaxnum.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
---
name: test_combine_nan_rhs_fminnum_half
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fneg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fneg.mir
index db3ab3d451d4c..f3a093e64a6c7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fneg.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fneg.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -o - -mtriple=aarch64-unknown-unknown -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s | FileCheck %s
---
name: test_combine_fneg_fneg
body: |
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fpowi.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fpowi.mir
index 8b8158348e399..9ee950f2327cc 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fpowi.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fpowi.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -o - -mtriple=aarch64-unknown-unknown -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s | FileCheck %s
---
name: fpowi_s64_zero
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fptrunc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fptrunc.mir
index ab4c62e313703..66c8f560f3a6b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fptrunc.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fptrunc.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
---
name: test_combine_float_to_half_fptrunc_constant
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-freeze.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-freeze.mir
index fac1ef0242823..08fae417b2e35 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-freeze.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-freeze.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -o - -mtriple=aarch64-unknown-unknown -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fshl.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fshl.mir
index 176cf88ed5a96..c58cd4b34467e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fshl.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fshl.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# RUN: llc -mtriple=arm64-unknown-unknown -global-isel -run-pass=aarch64-prelegalizer-combiner %s -o - | FileCheck %s
+# RUN: llc -mtriple=arm64-unknown-unknown -global-isel -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
---
name: fshl_i8
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fshr.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fshr.mir
index 416a9a444a0b4..b07752bb8bd2d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fshr.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fshr.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# RUN: llc -mtriple=arm64-unknown-unknown -global-isel -run-pass=aarch64-prelegalizer-combiner %s -o - | FileCheck %s
+# RUN: llc -mtriple=arm64-unknown-unknown -global-isel -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
---
name: fshr_i8
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fsqrt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fsqrt.mir
index 4fe05c616eb3c..5eb5c1c4b60b7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fsqrt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fsqrt.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
---
name: test_combine_half_fsqrt_constant
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-of-binop-to-icmp-of-0.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-of-binop-to-icmp-of-0.mir
index 966b781463fd0..480af74608206 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-of-binop-to-icmp-of-0.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-of-binop-to-icmp-of-0.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
# Test:
# (X + Y) == X --> Y == 0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-to-lhs-known-bits.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-to-lhs-known-bits.mir
index da79a3a17ed0d..17356b7cfdb2c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-to-lhs-known-bits.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-to-lhs-known-bits.mir
@@ -1,6 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner --aarch64prelegalizercombiner-only-enable-rule="icmp_to_lhs_known_bits" -global-isel -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' --aarch64prelegalizercombiner-only-enable-rule="icmp_to_lhs_known_bits" -global-isel %s -o - | FileCheck %s
# REQUIRES: asserts
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir
index 86c0575961a17..ca521b7a533f3 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64 -run-pass=aarch64-prelegalizer-combiner %s | FileCheck %s
+# RUN: llc -o - -mtriple=aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s | FileCheck %s
---
name: test_combine_consecutive
body: |
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
index f77ab013e20f2..67558f2c83dd5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-inttoptr-ptrtoint.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-inttoptr-ptrtoint.mir
index afcb5f74059a4..5a5e7bd7e1f9e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-inttoptr-ptrtoint.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-inttoptr-ptrtoint.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
# RUN: llc -debugify-and-strip-all-safe -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -debugify-and-strip-all-safe -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
---
name: test_combine_inttoptr_same_addressspace
body: |
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-logic-of-compare.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-logic-of-compare.mir
index d5356711585fa..875c4151c14dc 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-logic-of-compare.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-logic-of-compare.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -debugify-and-strip-all-safe -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -debugify-and-strip-all-safe -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
---
# icmp (x, 1) && icmp (x, 2) -> x
name: test_icmp_and_icmp
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-mul-to-shl.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-mul-to-shl.mir
index 283c89b5ae474..c2481a0532b77 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-mul-to-shl.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-mul-to-shl.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
...
---
name: mul_to_shl
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-mul.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-mul.mir
index 30a13f8f8f393..a3bd757472898 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-mul.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-mul.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
---
name: mul_by_zero
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-mulo-with-2.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-mulo-with-2.mir
index 261201590e5e0..9cf0b0be7ab0c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-mulo-with-2.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-mulo-with-2.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -debugify-and-strip-all-safe -run-pass=aarch64-prelegalizer-combiner --aarch64prelegalizercombiner-only-enable-rule="mulo_by_2" -global-isel -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -debugify-and-strip-all-safe -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' --aarch64prelegalizercombiner-only-enable-rule="mulo_by_2" -global-isel %s -o - | FileCheck %s
# REQUIRES: asserts
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-narrow-binop.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-narrow-binop.mir
index e9d4af7da5d06..4a35de0fe7ac2 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-narrow-binop.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-narrow-binop.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s --check-prefixes=CHECK
+# RUN: llc -o - -mtriple=aarch64-unknown-unknown -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s | FileCheck %s --check-prefixes=CHECK
---
name: test_combine_trunc_xor_i64
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-neg-and-one-to-sext-inreg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-neg-and-one-to-sext-inreg.mir
index 194a15f940da7..7707852ee5319 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-neg-and-one-to-sext-inreg.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-neg-and-one-to-sext-inreg.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -o - -mtriple aarch64-- -run-pass=aarch64-prelegalizer-combiner %s | FileCheck %s
+# RUN: llc -o - -mtriple aarch64-- -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s | FileCheck %s
---
name: test_combine_neg_and_one_to_sext_inreg_s32
body: |
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-op-trunc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-op-trunc.mir
index 6a16b5b8b9e77..f3f0d78a86eaf 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-op-trunc.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-op-trunc.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -o - -mtriple=aarch64-unknown-unknown -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s | FileCheck %s
# Truncs with a single use get folded.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-overflow.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-overflow.mir
index 20cba54923548..751f254d08d6c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-overflow.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-overflow.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
---
name: add_unused
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-ptradd-int2ptr.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-ptradd-int2ptr.mir
index 492c1ce3f7115..a729153023d60 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-ptradd-int2ptr.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-ptradd-int2ptr.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
# RUN: llc -debugify-and-strip-all-safe -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -debugify-and-strip-all-safe -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
---
name: agc.test_combine_ptradd_constants_intres
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-ptradd-reassociation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-ptradd-reassociation.mir
index 764f1c06a9b93..d531a6aa76ca2 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-ptradd-reassociation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-ptradd-reassociation.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown --aarch64prelegalizercombiner-only-enable-rule="reassoc_ptradd" %s -o - | FileCheck %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown --aarch64prelegalizercombiner-only-enable-rule="reassoc_ptradd" %s -o - | FileCheck %s
# REQUIRES: asserts
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-ptrtoint.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-ptrtoint.mir
index 056ca6d28c0da..d582ef7bcb7ea 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-ptrtoint.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-ptrtoint.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
# RUN: llc -debugify-and-strip-all-safe -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -debugify-and-strip-all-safe -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
---
name: test_combine_ptrtoint
body: |
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-same-op.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-same-op.mir
index 4fc51fe28c7bd..6df2d3c3af9e8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-same-op.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-same-op.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
---
name: sub_same_op
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-sdiv.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-sdiv.mir
index fc73245e2b79b..05e09c6aefd0a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-sdiv.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-sdiv.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -o - -mtriple=aarch64-unknown-unknown -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir
index 4afa0d4378fe1..14fa36ff4d3c4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
# RUN: llc -debugify-and-strip-all-safe -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -debugify-and-strip-all-safe -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
# REQUIRES: asserts
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-shift-immed-mismatch-crash.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-shift-immed-mismatch-crash.mir
index 16a8f80897846..567431b843617 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-shift-immed-mismatch-crash.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-shift-immed-mismatch-crash.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
---
name: shift_immed_chain_mismatch_size_crash
alignment: 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-shifts-undef.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-shifts-undef.mir
index 236d49fc99c62..40f390fc0b0df 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-shifts-undef.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-shifts-undef.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
---
name: shl_by_ge_bw
alignment: 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-shufflevector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-shufflevector.mir
index fbcc87fc7012a..5fba30e4c00a5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-shufflevector.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-shufflevector.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -o - -mtriple=aarch64-unknown-unknown -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s | FileCheck %s
---
name: shuffle_concat_1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.mir
index 5a75e5d249e62..3b7d80ad4f40b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -o - -mtriple=aarch64-unknown-unknown -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s | FileCheck %s
---
name: sub_one_from_sub
body: |
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-trunc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-trunc.mir
index 9a2b9dd4b2b60..ee00c77d302bf 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-trunc.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-trunc.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s --check-prefixes=CHECK,CHECK-PRE
+# RUN: llc -o - -mtriple=aarch64-unknown-unknown -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s | FileCheck %s --check-prefixes=CHECK,CHECK-PRE
# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s | FileCheck %s --check-prefixes=CHECK,CHECK-POST
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.mir
index f8578a694e2d4..e1602204f23c0 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -o - -mtriple=aarch64-unknown-unknown -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s | FileCheck %s
---
name: udiv_by_scalar_const
body: |
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-udivrem-use-bug.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-udivrem-use-bug.mir
index 656900de5a30e..b856a8450bd92 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-udivrem-use-bug.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-udivrem-use-bug.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -o - -mtriple=aarch64-unknown-unknown -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s | FileCheck %s
# Check that we don't miscompile this into G_UDIVREM because of the different
# first operands.
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-umulh-to-lshr.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-umulh-to-lshr.mir
index 3ff72219810fb..3b87985b5642e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-umulh-to-lshr.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-umulh-to-lshr.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
---
name: mul_to_lshr
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-unary-undef-to-zero.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-unary-undef-to-zero.mir
index 1c5f5cbd17b3b..dbe32509b1c1e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-unary-undef-to-zero.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-unary-undef-to-zero.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=aarch64-unknown-unknown -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -o - %s | FileCheck %s
# Test unary_op(undef) -> 0 combines
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir
index f427f8648a301..731362498069e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -o - -mtriple=aarch64-unknown-unknown -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s | FileCheck %s
# Simple unmerge(merge) case with two operands.
# The sources of the merge can be used in place of
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-use-vector-truncate-order.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-use-vector-truncate-order.mir
index 5b7748a247a95..8cf2a9884fba1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-use-vector-truncate-order.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-use-vector-truncate-order.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
---
name: test_use_vector_truncate_reversed_order
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-vscale.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-vscale.mir
index 9b7a44954afdb..19ebeea5a32f4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-vscale.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-vscale.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -o - -mtriple=aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fold-global-offsets-insertpt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/fold-global-offsets-insertpt.mir
index 293f8cf0b952f..51a2c461ce732 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/fold-global-offsets-insertpt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/fold-global-offsets-insertpt.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -mtriple aarch64-apple-darwin -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64-apple-darwin -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-macosx13.5.0"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fold-global-offsets-target-features.mir b/llvm/test/CodeGen/AArch64/GlobalISel/fold-global-offsets-target-features.mir
index 8197bf9e63220..8e16cc7b5616b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/fold-global-offsets-target-features.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/fold-global-offsets-target-features.mir
@@ -1,10 +1,16 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=DEFAULT,CHECK
+# RUN: llc -mtriple aarch64-unknown-unknown -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s --check-prefixes=DEFAULT,CHECK
# RUN: llc -mtriple aarch64-apple-darwin -code-model=large -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=LARGE-MACHO,CHECK
+# RUN: llc -mtriple aarch64-apple-darwin -code-model=large -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s --check-prefixes=LARGE-MACHO,CHECK
# RUN: llc -mtriple aarch64-apple-darwin -code-model=small -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=SMALL-MACHO,CHECK
+# RUN: llc -mtriple aarch64-apple-darwin -code-model=small -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s --check-prefixes=SMALL-MACHO,CHECK
# RUN: llc -mtriple aarch64-linux-elf -code-model=large -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=LARGE-ELF,CHECK
+# RUN: llc -mtriple aarch64-linux-elf -code-model=large -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s --check-prefixes=LARGE-ELF,CHECK
# RUN: llc -mtriple aarch64-linux-elf -code-model=tiny -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=TINY,CHECK
+# RUN: llc -mtriple aarch64-linux-elf -code-model=tiny -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s --check-prefixes=TINY,CHECK
# RUN: llc -mtriple aarch64-windows-coff -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=WINDOWS,CHECK
+# RUN: llc -mtriple aarch64-windows-coff -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s --check-prefixes=WINDOWS,CHECK
# Each of these tests has a trivial pattern for folding a G_PTR_ADD into a
# G_GLOBAL_VALUE.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fold-global-offsets.mir b/llvm/test/CodeGen/AArch64/GlobalISel/fold-global-offsets.mir
index f0fbfecf219fd..c7b8cdc730ba4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/fold-global-offsets.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/fold-global-offsets.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64-apple-darwin -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64-apple-darwin -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
--- |
@g = external hidden global i32
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir
index 1c0fc3fb36a0d..854d90d43119c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-darwin"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
index b040ff2932ce8..4c46ede7b08de 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-darwin"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
index f24aeaed1d8bc..d9a5c631df225 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
index af01789fa75d4..601ca32bc8478 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
index 73930911e304f..6e9e0596cdcfc 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=aarch64-prelegalizer-combiner -O0 -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -O0 %s -o - | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-darwin"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/lifetime-marker-no-dce.mir b/llvm/test/CodeGen/AArch64/GlobalISel/lifetime-marker-no-dce.mir
index 2dd968561e5e8..9cf149c2cadd0 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/lifetime-marker-no-dce.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/lifetime-marker-no-dce.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -global-isel -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -global-isel %s -o - | FileCheck %s
# Check that we don't DCE the lifetime markers even though they don't have any users.
---
name: test_lifetime_no_dce
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/non-pow-2-extload-combine.mir b/llvm/test/CodeGen/AArch64/GlobalISel/non-pow-2-extload-combine.mir
index 5bc845fb35037..d0ff83f8ecb72 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/non-pow-2-extload-combine.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/non-pow-2-extload-combine.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=aarch64-prelegalizer-combiner %s -o - -verify-machineinstrs | FileCheck %s
+# RUN: llc -mtriple=aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/observer-change-crash.mir b/llvm/test/CodeGen/AArch64/GlobalISel/observer-change-crash.mir
index 5ea12871f6efe..70608d257d6cc 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/observer-change-crash.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/observer-change-crash.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-ios5.0.0"
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/opt-overlapping-and.mir b/llvm/test/CodeGen/AArch64/GlobalISel/opt-overlapping-and.mir
index 351d6b39d56e5..2052dc55c1e4c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/opt-overlapping-and.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/opt-overlapping-and.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -debugify-and-strip-all-safe -mtriple arm64-apple-ios -O0 -run-pass=aarch64-prelegalizer-combiner --aarch64prelegalizercombiner-only-enable-rule="overlapping_and" -global-isel -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -debugify-and-strip-all-safe -mtriple arm64-apple-ios -O0 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' --aarch64prelegalizercombiner-only-enable-rule="overlapping_and" -global-isel %s -o - | FileCheck %s
# REQUIRES: asserts
---
name: bitmask_overlap1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-addo-zero.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-addo-zero.mir
index 9483cbf06f405..2fdf598db9c4d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-addo-zero.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-addo-zero.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -debugify-and-strip-all-safe -run-pass=aarch64-prelegalizer-combiner --aarch64prelegalizercombiner-only-enable-rule="match_addos" -global-isel -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -debugify-and-strip-all-safe -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' --aarch64prelegalizercombiner-only-enable-rule="match_addos" -global-isel %s -o - | FileCheck %s
# REQUIRES: asserts
# (G_*ADDO x, 0) -> x + no carry
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-binop-reassoc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-binop-reassoc.mir
index f1676e48e5113..70ca88bbf3d0b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-binop-reassoc.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-binop-reassoc.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
# Combins: (Opc (Opc X, C1), C2) -> (Opc X, (Opc C1, C2))
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-conflict.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-conflict.mir
index a87ff305d1535..5a4816e6e534b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-conflict.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-conflict.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -global-isel -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -global-isel %s -o - | FileCheck %s
---
name: test
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-crash.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-crash.mir
index 767ece62b8731..41a2d186d1a1f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-crash.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-crash.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64-apple-ios -run-pass=aarch64-prelegalizer-combiner %s -o - -verify-machineinstrs | FileCheck %s
+# RUN: llc -mtriple aarch64-apple-ios -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
# Check that we insert the divrem at the place of the G_UDIV, not the G_UREM.
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir
index 199da9bee6aae..138a330c848b1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -debugify-and-strip-all-safe -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner --aarch64prelegalizercombiner-only-enable-rule="icmp_to_true_false_known_bits" -global-isel -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -debugify-and-strip-all-safe -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' --aarch64prelegalizercombiner-only-enable-rule="icmp_to_true_false_known_bits" -global-isel %s -o - | FileCheck %s
# REQUIRES: asserts
--- |
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-and-mask.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-and-mask.mir
index a7809f276c53f..c85a50cc93c27 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-and-mask.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-and-mask.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -aarch64prelegalizercombiner-only-enable-rule="load_and_mask" -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -aarch64prelegalizercombiner-only-enable-rule="load_and_mask" %s -o - | FileCheck %s
# REQUIRES: asserts
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-or-pattern-align.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-or-pattern-align.mir
index 3dd681c2d21fb..6375d44b36c2c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-or-pattern-align.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-or-pattern-align.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -debugify-and-strip-all-safe -mtriple aarch64 -O0 -run-pass=aarch64-prelegalizer-combiner --aarch64prelegalizercombiner-only-enable-rule="load_or_combine" -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=NOT_STRICT
+# RUN: llc -debugify-and-strip-all-safe -mtriple aarch64 -O0 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' --aarch64prelegalizercombiner-only-enable-rule="load_or_combine" -global-isel %s -o - | FileCheck %s --check-prefix=NOT_STRICT
# RUN: llc -debugify-and-strip-all-safe -mattr=+strict-align -mtriple aarch64 -O0 -run-pass=aarch64-prelegalizer-combiner --aarch64prelegalizercombiner-only-enable-rule="load_or_combine" -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=STRICT
+# RUN: llc -debugify-and-strip-all-safe -mattr=+strict-align -mtriple aarch64 -O0 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' --aarch64prelegalizercombiner-only-enable-rule="load_or_combine" -global-isel %s -o - | FileCheck %s --check-prefix=STRICT
# REQUIRES: asserts
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-or-pattern.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-or-pattern.mir
index 131dcbf9906b4..9fcd3bedf2edc 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-or-pattern.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-or-pattern.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -debugify-and-strip-all-safe -mtriple aarch64 -O0 -run-pass=aarch64-prelegalizer-combiner --aarch64prelegalizercombiner-only-enable-rule="load_or_combine" -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=LITTLE
+# RUN: llc -debugify-and-strip-all-safe -mtriple aarch64 -O0 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' --aarch64prelegalizercombiner-only-enable-rule="load_or_combine" -global-isel %s -o - | FileCheck %s --check-prefix=LITTLE
# RUN: llc -debugify-and-strip-all-safe -mtriple arm64eb -O0 -run-pass=aarch64-prelegalizer-combiner --aarch64prelegalizercombiner-only-enable-rule="load_or_combine" -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=BIG
+# RUN: llc -debugify-and-strip-all-safe -mtriple arm64eb -O0 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' --aarch64prelegalizercombiner-only-enable-rule="load_or_combine" -global-isel %s -o - | FileCheck %s --check-prefix=BIG
# REQUIRES: asserts
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-mulo-zero.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-mulo-zero.mir
index 34219c374f6ed..39cebb4d1e491 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-mulo-zero.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-mulo-zero.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -debugify-and-strip-all-safe -run-pass=aarch64-prelegalizer-combiner --aarch64prelegalizercombiner-only-enable-rule="mulo_by_0" -global-isel -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -debugify-and-strip-all-safe -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' --aarch64prelegalizercombiner-only-enable-rule="mulo_by_0" -global-isel %s -o - | FileCheck %s
# REQUIRES: asserts
# (G_*MULO x, 0) -> 0 + no carry out
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-narrow-binop-feeding-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-narrow-binop-feeding-add.mir
index 8f19649339823..23688861102e0 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-narrow-binop-feeding-add.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-narrow-binop-feeding-add.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-select-to-fminmax.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-select-to-fminmax.mir
index 03e507f5eaa7f..ed1cf482a29b0 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-select-to-fminmax.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-select-to-fminmax.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -mattr=+fullfp16 -run-pass=aarch64-prelegalizer-combiner -global-isel -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -mattr=+fullfp16 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -global-isel %s -o - | FileCheck %s
---
name: test_s16
body: |
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-use-vector-truncate.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-use-vector-truncate.mir
index 3d0d591bccc17..caaadc49e4148 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-use-vector-truncate.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-use-vector-truncate.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=aarch64-prelegalizer-combiner %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
---
name: test_foldable_s32
body: |
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-ashr-shl-to-sext-inreg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-ashr-shl-to-sext-inreg.mir
index 9e540390dd37f..a9e55590dc756 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-ashr-shl-to-sext-inreg.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-ashr-shl-to-sext-inreg.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
---
name: ashr_shl_to_sext_inreg
alignment: 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-binop-same-val.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-binop-same-val.mir
index a3d5294a99c5d..95138b1cda970 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-binop-same-val.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-binop-same-val.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
name: or_same
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-br.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-br.mir
index fd49f7ffc15eb..e66ee433c1bb2 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-br.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-br.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -debugify-and-strip-all-safe -O0 -run-pass=aarch64-prelegalizer-combiner --aarch64prelegalizercombiner-only-enable-rule="opt_brcond_by_inverting_cond" -global-isel -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -debugify-and-strip-all-safe -O0 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' --aarch64prelegalizercombiner-only-enable-rule="opt_brcond_by_inverting_cond" -global-isel %s -o - | FileCheck %s
# Need asserts for the only-enable-rule to work.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-bzero.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-bzero.mir
index a152b3fdf1119..034faf0a424f1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-bzero.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-bzero.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64-apple-ios -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=DARWIN
+# RUN: llc -mtriple aarch64-apple-ios -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s --check-prefix=DARWIN
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=UNKNOWN
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s --check-prefix=UNKNOWN
#
# Check that on Darwin we can combine to G_BZERO. Without Darwin, this should
# stay as memset.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-commute-shift.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-commute-shift.mir
index d4800748374e0..1b5ec6f0b4e02 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-commute-shift.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-commute-shift.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# RUN: llc -mtriple aarch64 -mattr=+fullfp16 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -mattr=+fullfp16 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
---
name: shl_add_k
alignment: 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-concat-vectors.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-concat-vectors.mir
index 30cb7b724059e..d3fc4c58da16c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-concat-vectors.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-concat-vectors.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64-apple-ios -run-pass=aarch64-prelegalizer-combiner %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64-apple-ios -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
# Check that we canonicalize concat_vectors(build_vector, build_vector)
# into build_vector.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-copy-prop-disabled.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-copy-prop-disabled.mir
index 35dce4da92aa7..7b05d011ee2fa 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-copy-prop-disabled.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-copy-prop-disabled.mir
@@ -1,16 +1,28 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -global-isel -verify-machineinstrs %s -o - \
# RUN: | FileCheck --check-prefix=ENABLED %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -global-isel %s -o - \
+# RUN: | FileCheck --check-prefix=ENABLED %s
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -global-isel -verify-machineinstrs %s -o - \
# RUN: --aarch64prelegalizercombiner-disable-rule=copy_prop | FileCheck --check-prefix=DISABLED %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -global-isel %s -o - \
+# RUN: --aarch64prelegalizercombiner-disable-rule=copy_prop | FileCheck --check-prefix=DISABLED %s
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -global-isel -verify-machineinstrs %s -o - \
# RUN: --aarch64prelegalizercombiner-disable-rule="*" | FileCheck --check-prefix=DISABLED %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -global-isel %s -o - \
+# RUN: --aarch64prelegalizercombiner-disable-rule="*" | FileCheck --check-prefix=DISABLED %s
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -global-isel -verify-machineinstrs %s -o - \
# RUN: --aarch64prelegalizercombiner-disable-rule="*,!copy_prop" \
# RUN: | FileCheck --check-prefix=ENABLED %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -global-isel %s -o - \
+# RUN: --aarch64prelegalizercombiner-disable-rule="*,!copy_prop" \
+# RUN: | FileCheck --check-prefix=ENABLED %s
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -global-isel -verify-machineinstrs %s -o - \
# RUN: --aarch64prelegalizercombiner-only-enable-rule="copy_prop" \
# RUN: | FileCheck --check-prefix=ENABLED %s
+# RUN: llc -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -global-isel %s -o - \
+# RUN: --aarch64prelegalizercombiner-only-enable-rule="copy_prop" \
+# RUN: | FileCheck --check-prefix=ENABLED %s
# REQUIRES: asserts
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
index 591b6a17928cb..d5c159dfc2283 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
@@ -1,7 +1,11 @@
# RUN: llc -O0 -run-pass=aarch64-prelegalizer-combiner -global-isel %s -o - | FileCheck %s
+# RUN: llc -O0 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -global-isel %s -o - | FileCheck %s
# RUN: llc -O0 -run-pass=aarch64-prelegalizer-combiner -global-isel %s -o - \
# RUN: -debug-only=aarch64-prelegalizer-combiner,gi-combiner 2>&1 >/dev/null \
# RUN: | FileCheck %s --check-prefix=CHECK-WORKLIST
+# RUN: llc -O0 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -global-isel %s -o - \
+# RUN: -debug-only=aarch64-prelegalizer-combiner,gi-combiner 2>&1 >/dev/null \
+# RUN: | FileCheck %s --check-prefix=CHECK-WORKLIST
# REQUIRES: asserts
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-s1.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-s1.mir
index 072bdc38330b7..1d79f6be751fa 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-s1.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-s1.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -O0 -run-pass=aarch64-prelegalizer-combiner -global-isel -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -O0 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -global-isel %s -o - | FileCheck %s
# Check we don't try to combine a load of < s8 as that will end up creating a illegal non-extending load.
--- |
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads.mir
index 28c7485bbf60c..24e67138c7510 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -O0 -run-pass=aarch64-prelegalizer-combiner -global-isel -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -O0 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -global-isel %s -o - | FileCheck %s
---
name: test_anyext
body: |
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-funnel-shifts-to-rotates.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-funnel-shifts-to-rotates.mir
index 0ccd3515d2b6e..8962471b97a42 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-funnel-shifts-to-rotates.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-funnel-shifts-to-rotates.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64-apple-ios -run-pass=aarch64-prelegalizer-combiner %s -o - -verify-machineinstrs | FileCheck %s
+# RUN: llc -mtriple aarch64-apple-ios -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
---
name: test_rotr
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-hoist-same-hands.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-hoist-same-hands.mir
index 1b85cec49226c..7ff65215e98b4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-hoist-same-hands.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-hoist-same-hands.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-PRE
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-PRE
# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-POST
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-icmp-redundant-trunc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-icmp-redundant-trunc.mir
index 6a944c667cc82..c0d1033830fc6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-icmp-redundant-trunc.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-icmp-redundant-trunc.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64-apple-ios -run-pass=aarch64-prelegalizer-combiner %s -o - -verify-machineinstrs | FileCheck %s
+# RUN: llc -mtriple aarch64-apple-ios -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
# This test checks the optimization to remove the G_TRUNC if we can determine it's redundant.
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-invert-cmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-invert-cmp.mir
index ca9afa7700fa8..8b8fe5e27ae6b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-invert-cmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-invert-cmp.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64-apple-ios -run-pass=aarch64-prelegalizer-combiner --aarch64prelegalizercombiner-only-enable-rule="not_cmp_fold" %s -o - -verify-machineinstrs | FileCheck %s
+# RUN: llc -mtriple aarch64-apple-ios -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' --aarch64prelegalizercombiner-only-enable-rule="not_cmp_fold" %s -o - | FileCheck %s
# Need asserts for the only-enable-rule to work.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-not-really-equiv-insts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-not-really-equiv-insts.mir
index b2d2f99777e4f..55643ad9a1322 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-not-really-equiv-insts.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-not-really-equiv-insts.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
--- |
@g = external hidden unnamed_addr global i32, align 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-prop-extends-phi.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-prop-extends-phi.mir
index 6b8410a83b11a..d05462438bdea 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-prop-extends-phi.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-prop-extends-phi.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64-apple-darwin -debugify-and-strip-all-safe -run-pass=aarch64-prelegalizer-combiner -global-isel -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64-apple-darwin -debugify-and-strip-all-safe -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -global-isel %s -o - | FileCheck %s
# Check that we propagate the G_SEXT to the sources of the phi operand.
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-ptradd-chain.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-ptradd-chain.mir
index a66fd4faec800..00e0d374f6caf 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-ptradd-chain.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-ptradd-chain.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64-apple-ios -run-pass=aarch64-prelegalizer-combiner %s -o - -verify-machineinstrs | FileCheck %s
+# RUN: llc -mtriple aarch64-apple-ios -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
# REQUIRES: asserts
# Check that we fold two adds of constant offsets with G_PTR_ADD into a single G_PTR_ADD.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-select.mir
index 94c93ba1f083e..ec25c39f73afa 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-select.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
--- |
declare void @foo()
define void @self() { ret void }
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-sextload-from-sextinreg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-sextload-from-sextinreg.mir
index e827341e909d9..ea54b75007c66 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-sextload-from-sextinreg.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-sextload-from-sextinreg.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
---
name: sextload_from_inreg
alignment: 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector-disjoint-mask.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector-disjoint-mask.mir
index 914dfa0c58d59..655ffc1ff933a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector-disjoint-mask.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector-disjoint-mask.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64-apple-ios -run-pass=aarch64-prelegalizer-combiner %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64-apple-ios -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
---
name: shuffle_vector_unused_lhs
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector-undef-rhs.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector-undef-rhs.mir
index 7a314ba9ab358..a65b4b4168e42 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector-undef-rhs.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector-undef-rhs.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
---
name: shuffle_vector_undef_rhs
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector.mir
index 901341003d495..864d9da886848 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64-apple-ios -run-pass=aarch64-prelegalizer-combiner %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64-apple-ios -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
# Check that we canonicalize shuffle_vector(Src1, Src2, mask(0,1,2,3))
# into concat_vector(Src1, Src2).
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-simplify-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-simplify-add.mir
index 83a4db1843a09..a346a77527633 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-simplify-add.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-simplify-add.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
name: pat1
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
index d36b382672e60..a15242e556a07 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
name: right_ident_sub
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-undef.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-undef.mir
index 3a10f47aa3068..01b5efe0c6dfe 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-undef.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-undef.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
name: uitofp_to_zero
alignment: 4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-xor-of-and-with-same-reg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-xor-of-and-with-same-reg.mir
index f0cd970602d55..f0adda95c4975 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-xor-of-and-with-same-reg.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-xor-of-and-with-same-reg.mir
@@ -1,6 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -debugify-and-strip-all-safe -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple aarch64 -debugify-and-strip-all-safe -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/uaddo-8-16-bits.mir b/llvm/test/CodeGen/AArch64/GlobalISel/uaddo-8-16-bits.mir
index b242c68e3b07f..b26e91b82548b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/uaddo-8-16-bits.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/uaddo-8-16-bits.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -verify-machineinstrs -mtriple arm64-apple-ios -global-isel -run-pass=aarch64-prelegalizer-combiner -o - %s | FileCheck %s
+# RUN: llc -mtriple arm64-apple-ios -global-isel -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' -o - %s | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/AArch64/extractvector-of-load.mir b/llvm/test/CodeGen/AArch64/extractvector-of-load.mir
index 43051232b436d..4f075a7653a22 100644
--- a/llvm/test/CodeGen/AArch64/extractvector-of-load.mir
+++ b/llvm/test/CodeGen/AArch64/extractvector-of-load.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=aarch64-linux-gnu -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-linux-gnu -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
---
name: f
diff --git a/llvm/test/CodeGen/AArch64/extractvector-oob-load.mir b/llvm/test/CodeGen/AArch64/extractvector-oob-load.mir
index e7e8c93991094..c24e33ca9d979 100644
--- a/llvm/test/CodeGen/AArch64/extractvector-oob-load.mir
+++ b/llvm/test/CodeGen/AArch64/extractvector-oob-load.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=aarch64-linux-gnu -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-linux-gnu -passes='require<libcall-lowering-info>,function(machine-function(aarch64-prelegalizer-combiner))' %s -o - | FileCheck %s
---
name: f
More information about the llvm-commits
mailing list