[llvm] [DAG] computeKnownFPClass - add ISD::SINT_TO_FP/UINT_TO_FP handling (PR #190539)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-selectiondag

@llvm/pr-subscribers-backend-risc-v

Author: Pau Sum (pau-sum)

<details>
<summary>Changes</summary>

Resolves #<!-- -->189479

- Adds computeKnownFPClass for ISD::SINT_TO_FP/UINT_TO_FP in SelectionDAG.cpp
- Adds tests for RISC-V in llvm/test/CodeGen/RISCV/combine-is_fpclass.ll

---
Full diff: https://github.com/llvm/llvm-project/pull/190539.diff


2 Files Affected:

- (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (+8) 
- (modified) llvm/test/CodeGen/RISCV/combine-is_fpclass.ll (+63) 


``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 137922aa62557..980ba98f38084 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -6082,6 +6082,14 @@ KnownFPClass SelectionDAG::computeKnownFPClass(SDValue Op,
     Known = computeKnownFPClass(Op.getOperand(0), InterestedClasses, Depth + 1);
     break;
   }
+  case ISD::SINT_TO_FP:
+  case ISD::UINT_TO_FP: {
+    Known.knownNot(fcNan);
+
+    if (Opcode == ISD::UINT_TO_FP)
+      Known.knownNot(fcNegative);
+    break;
+  }
   case ISD::BITCAST: {
     // FIXME: It should not be necessary to check for an elementwise bitcast.
     // If a bitcast is not elementwise between vector / scalar types,
diff --git a/llvm/test/CodeGen/RISCV/combine-is_fpclass.ll b/llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
index 5049775710628..fc6bb4aedfaee 100644
--- a/llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
+++ b/llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
@@ -22,6 +22,69 @@ define i8 @iszero_constant_v4f32() nounwind {
   ret i8 %r
 }
 
+define i1 @uitofp_isnan(i32 %x) {
+; CHECK-LABEL: uitofp_isnan:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    ret
+  %f = uitofp i32 %x to float
+  %res = call i1 @llvm.is.fpclass.f32(float %f, i32 3) ; 3 = sNaN|qNaN
+  ret i1 %res
+}
+
+define i1 @sitofp_isnan(i32 %x) {
+; CHECK-LABEL: sitofp_isnan:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    ret
+  %f = sitofp i32 %x to float
+  %res = call i1 @llvm.is.fpclass.f32(float %f, i32 3) ; 3 = sNaN|qNaN
+  ret i1 %res
+}
+
+define i1 @uitofp_isneg(i32 %x) {
+; CHECK-LABEL: uitofp_isneg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    ret
+  %f = uitofp i32 %x to float
+  %res = call i1 @llvm.is.fpclass.f32(float %f, i32 60) ; 60 = neg_inf|neg_normal|neg_subnormal|neg_zero
+  ret i1 %res
+}
+
+define <4 x i1> @uitofp_v4_isnan(<4 x i32> %x) nounwind {
+; CHECK-LABEL: uitofp_v4_isnan:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT:    vmclr.m v0
+; CHECK-NEXT:    ret
+  %f = uitofp <4 x i32> %x to <4 x float>
+  %res = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %f, i32 3) ; 3 = sNaN|qNaN
+  ret <4 x i1> %res
+}
+
+define <4 x i1> @sitofp_v4_isnan(<4 x i32> %x) {
+; CHECK-LABEL: sitofp_v4_isnan:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT:    vmclr.m v0
+; CHECK-NEXT:    ret
+  %f = sitofp <4 x i32> %x to <4 x float>
+  %res = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %f, i32 3) ; 3 = sNaN|qNaN
+  ret <4 x i1> %res
+}
+
+define <4 x i1> @uitofp_v4_is_negative(<4 x i32> %x) {
+; CHECK-LABEL: uitofp_v4_is_negative:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT:    vmclr.m v0
+; CHECK-NEXT:    ret
+  %f = uitofp <4 x i32> %x to <4 x float>
+  %res = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %f, i32 60) ; 60 = neg_inf|neg_normal|neg_subnormal|neg_zero
+  ret <4 x i1> %res
+}
+
 define <vscale x 4 x i1> @splat_constant_is_pos_normal() {
 ; CHECK-LABEL: splat_constant_is_pos_normal:
 ; CHECK:       # %bb.0:

``````````

</details>


https://github.com/llvm/llvm-project/pull/190539