[llvm] [SLP][NFC]Fix run line for the test, fix test name, NFC (PR #190537)
Alexey Bataev via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 5 09:20:03 PDT 2026
https://github.com/alexey-bataev created https://github.com/llvm/llvm-project/pull/190537
None
>From 222ef6304b7ef3bf503e0390dadc07331590fd0f Mon Sep 17 00:00:00 2001
From: Alexey Bataev <a.bataev at outlook.com>
Date: Sun, 5 Apr 2026 09:19:50 -0700
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
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Created using spr 1.3.7
---
...on.ll => multi-use-bitcasted-reduction.ll} | 40 ++++++++++---------
1 file changed, 22 insertions(+), 18 deletions(-)
rename llvm/test/Transforms/SLPVectorizer/X86/{multi-use-bicasted-reduction.ll => multi-use-bitcasted-reduction.ll} (77%)
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/multi-use-bicasted-reduction.ll b/llvm/test/Transforms/SLPVectorizer/X86/multi-use-bitcasted-reduction.ll
similarity index 77%
rename from llvm/test/Transforms/SLPVectorizer/X86/multi-use-bicasted-reduction.ll
rename to llvm/test/Transforms/SLPVectorizer/X86/multi-use-bitcasted-reduction.ll
index c5c978c9d22b1..b112953581297 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/multi-use-bicasted-reduction.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/multi-use-bitcasted-reduction.ll
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
-; RUN: opt -passes=slp-vectorizer -S -mattr=+sse4.2 < %s | FileCheck %s
+; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux -mattr=+sse4.2 -slp-threshold=-2 < %s | FileCheck %s
define i32 @test(i32 %arg, i32 %arg1, i1 %arg4, i1 %arg5) {
; CHECK-LABEL: define i32 @test(
-; CHECK-SAME: i32 [[ARG:%.*]], i32 [[ARG1:%.*]], i1 [[ARG4:%.*]], i1 [[ARG5:%.*]]) {
+; CHECK-SAME: i32 [[ARG:%.*]], i32 [[ARG1:%.*]], i1 [[ARG4:%.*]], i1 [[ARG5:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[BB:.*:]]
; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[ARG]], i32 0
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[ARG1]], i32 1
@@ -74,38 +74,42 @@ bb20:
define i32 @test_multi_cond_use(i32 %arg, i32 %arg1, i1 %arg4, i1 %arg5) {
; CHECK-LABEL: define i32 @test_multi_cond_use(
-; CHECK-SAME: i32 [[ARG:%.*]], i32 [[ARG1:%.*]], i1 [[ARG4:%.*]], i1 [[ARG5:%.*]]) {
+; CHECK-SAME: i32 [[ARG:%.*]], i32 [[ARG1:%.*]], i1 [[ARG4:%.*]], i1 [[ARG5:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[BB:.*:]]
; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[ARG]], i32 0
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[ARG1]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 0>
+; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
; CHECK-NEXT: [[TMP3:%.*]] = sdiv <4 x i32> [[TMP2]], splat (i32 64)
-; CHECK-NEXT: [[TMP4:%.*]] = shl <4 x i32> [[TMP3]], <i32 1, i32 0, i32 0, i32 0>
-; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
-; CHECK-NEXT: [[TMP6:%.*]] = icmp ne <4 x i32> [[TMP4]], [[TMP5]]
-; CHECK-NEXT: [[TMP14:%.*]] = icmp eq <4 x i32> [[TMP4]], [[TMP5]]
-; CHECK-NEXT: [[TMP15:%.*]] = shufflevector <4 x i1> [[TMP6]], <4 x i1> [[TMP14]], <4 x i32> <i32 0, i32 5, i32 6, i32 7>
-; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[TMP15]], <4 x i32> <i32 1, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 2, i32 4, i32 8>
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i1> [[TMP15]], i32 3
+; CHECK-NEXT: [[TMP4:%.*]] = shl <4 x i32> [[TMP3]], <i32 0, i32 0, i32 1, i32 0>
+; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 0, i32 0>
+; CHECK-NEXT: [[TMP6:%.*]] = icmp eq <4 x i32> [[TMP4]], [[TMP5]]
+; CHECK-NEXT: [[TMP7:%.*]] = icmp ne <4 x i32> [[TMP4]], [[TMP5]]
+; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <4 x i1> [[TMP6]], <4 x i1> [[TMP7]], <4 x i32> <i32 0, i32 1, i32 6, i32 3>
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i1> [[TMP10]], i32 2
; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP8]] to i32
+; CHECK-NEXT: [[ICMP7:%.*]] = extractelement <4 x i1> [[TMP10]], i32 3
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[ICMP7]], i32 0, i32 2
+; CHECK-NEXT: [[ICMP9:%.*]] = extractelement <4 x i1> [[TMP10]], i32 1
+; CHECK-NEXT: [[TMP12:%.*]] = select i1 [[ICMP9]], i32 0, i32 4
+; CHECK-NEXT: [[ICMP11:%.*]] = extractelement <4 x i1> [[TMP10]], i32 0
+; CHECK-NEXT: [[TMP13:%.*]] = select i1 [[ICMP11]], i32 0, i32 8
+; CHECK-NEXT: [[EXT1:%.*]] = zext i1 [[ICMP11]] to i32
; CHECK-NEXT: br i1 [[ARG4]], label %[[BB13:.*]], label %[[BB16:.*]]
; CHECK: [[COMMON_RET:.*]]:
-; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ [[EXT]], %[[BB20:.*]] ], [ [[OR19:%.*]], %[[BB17:.*]] ]
+; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ [[EXT1]], %[[BB20:.*]] ], [ [[OR19:%.*]], %[[BB17:.*]] ]
; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
; CHECK: [[BB13]]:
-; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP7]])
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[SELECT]], [[EXT]]
+; CHECK-NEXT: [[OR14:%.*]] = or i32 [[OR]], [[TMP12]]
+; CHECK-NEXT: [[TMP9:%.*]] = or i32 [[OR14]], [[TMP13]]
; CHECK-NEXT: ret i32 [[TMP9]]
; CHECK: [[BB16]]:
; CHECK-NEXT: br i1 [[ARG5]], label %[[BB17]], label %[[BB20]]
; CHECK: [[BB17]]:
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i32> [[TMP7]], i32 0
-; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x i32> [[TMP7]], i32 1
-; CHECK-NEXT: [[OR18:%.*]] = or i32 [[TMP11]], [[TMP10]]
-; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i32> [[TMP7]], i32 2
+; CHECK-NEXT: [[OR18:%.*]] = or i32 [[SELECT]], [[EXT]]
; CHECK-NEXT: [[OR19]] = or i32 [[OR18]], [[TMP12]]
; CHECK-NEXT: br label %[[COMMON_RET]]
; CHECK: [[BB20]]:
-; CHECK-NEXT: [[TMP13:%.*]] = extractelement <4 x i32> [[TMP7]], i32 3
; CHECK-NEXT: store volatile i32 [[TMP13]], ptr null, align 4294967296
; CHECK-NEXT: br label %[[COMMON_RET]]
;
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