[llvm] 7c60d08 - [DAG] computeKnownFPClass - add ISD::SPLAT_VECTOR handling (#189780)

[via llvm-commits]

Author: Kartik Ohlan
Date: 2026-04-04T14:54:12Z
New Revision: 7c60d08056e13ac9ab0282887e0d44b6928caff5

URL: https://github.com/llvm/llvm-project/commit/7c60d08056e13ac9ab0282887e0d44b6928caff5
DIFF: https://github.com/llvm/llvm-project/commit/7c60d08056e13ac9ab0282887e0d44b6928caff5.diff

LOG: [DAG] computeKnownFPClass - add ISD::SPLAT_VECTOR handling (#189780)

Fixes #189481

Implement ISD::SPLAT_VECTOR in SelectionDAG::computeKnownFPClass to
correctly propagate floating-point properties from scalar operands to
vectors.

Added AArch64 and RISC-V test coverage

Added: 
    llvm/test/CodeGen/AArch64/known-fpclass-splat-vector.ll

Modified: 
    llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/test/CodeGen/RISCV/combine-is_fpclass.ll

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index dba27af5786e9..137922aa62557 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -6078,6 +6078,10 @@ KnownFPClass SelectionDAG::computeKnownFPClass(SDValue Op,
     }
     break;
   }
+  case ISD::SPLAT_VECTOR: {
+    Known = computeKnownFPClass(Op.getOperand(0), InterestedClasses, Depth + 1);
+    break;
+  }
   case ISD::BITCAST: {
     // FIXME: It should not be necessary to check for an elementwise bitcast.
     // If a bitcast is not elementwise between vector / scalar types,

diff  --git a/llvm/test/CodeGen/AArch64/known-fpclass-splat-vector.ll b/llvm/test/CodeGen/AArch64/known-fpclass-splat-vector.ll
new file mode 100644
index 0000000000000..23f04a2d34fea
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/known-fpclass-splat-vector.ll
@@ -0,0 +1,24 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64 -mattr=+sve < %s | FileCheck %s
+
+define <vscale x 4 x i1> @test_splat_const_is_pos_normal() {
+; CHECK-LABEL: test_splat_const_is_pos_normal:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmov z0.s, #1.00000000
+; CHECK-NEXT:    mov z1.s, #0x7fffff
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    sub z0.s, z0.s, #1 // =0x1
+; CHECK-NEXT:    cmphi p0.s, p0/z, z1.s, z0.s
+; CHECK-NEXT:    ret
+  %res = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> splat (float 1.0), i32 128)
+  ret <vscale x 4 x i1> %res
+}
+
+define <vscale x 4 x i1> @test_splat_const_isnan() {
+; CHECK-LABEL: test_splat_const_isnan:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    pfalse p0.b
+; CHECK-NEXT:    ret
+  %res = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> splat (float 2.0), i32 3)
+  ret <vscale x 4 x i1> %res
+}

diff  --git a/llvm/test/CodeGen/RISCV/combine-is_fpclass.ll b/llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
index 0292df415a655..5049775710628 100644
--- a/llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
+++ b/llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
@@ -21,3 +21,34 @@ define i8 @iszero_constant_v4f32() nounwind {
   %r = bitcast <8 x i1> %f to i8
   ret i8 %r
 }
+
+define <vscale x 4 x i1> @splat_constant_is_pos_normal() {
+; CHECK-LABEL: splat_constant_is_pos_normal:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT:    vmclr.m v0
+; CHECK-NEXT:    ret
+  %res = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> splat (float 1.0), i32 128) ; 128 = pos_normal
+  ret <vscale x 4 x i1> %res
+}
+
+define <vscale x 4 x i1> @splat_constant_isnan_false() {
+; CHECK-LABEL: splat_constant_isnan_false:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT:    vmclr.m v0
+; CHECK-NEXT:    ret
+  %res = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> splat (float 1.0), i32 3) ; 3 = nan
+  ret <vscale x 4 x i1> %res
+}
+
+define <vscale x 2 x i1> @splat_constant_f64_isinf_false() {
+; CHECK-LABEL: splat_constant_f64_isinf_false:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT:    vmclr.m v0
+; CHECK-NEXT:    ret
+  %res = call <vscale x 2 x i1> @llvm.is.fpclass.nxv2f64(<vscale x 2 x double> splat (double 1.0), i32 516) ; 516 = inf
+  ret <vscale x 2 x i1> %res
+}
+