[llvm] [DAG] computeKnownFPClass - add ISD::SPLAT_VECTOR handling (PR #189780)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sat Apr 4 07:08:17 PDT 2026
https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/189780
>From 4acc6bdf0b571d06a03ade01b73cd9e54fdfe667 Mon Sep 17 00:00:00 2001
From: kartikohlan <kartik7ohlan at gmail.com>
Date: Wed, 1 Apr 2026 17:09:32 -0400
Subject: [PATCH 1/3] Updated to upstream and test commit
---
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 6 +++
.../AArch64/known-fpclass-splat-vector.ll | 33 ++++++++++++
llvm/test/CodeGen/RISCV/combine-is_fpclass.ll | 50 +++++++++++++++++++
3 files changed, 89 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/known-fpclass-splat-vector.ll
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index d269c54340538..d10203bc1c70f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -6113,6 +6113,12 @@ KnownFPClass SelectionDAG::computeKnownFPClass(SDValue Op,
}
break;
}
+
+ case ISD::SPLAT_VECTOR: {
+ Known = computeKnownFPClass(Op.getOperand(0), InterestedClasses, Depth + 1);
+ break;
+ }
+
default:
if (Opcode >= ISD::BUILTIN_OP_END || Opcode == ISD::INTRINSIC_WO_CHAIN ||
Opcode == ISD::INTRINSIC_W_CHAIN || Opcode == ISD::INTRINSIC_VOID) {
diff --git a/llvm/test/CodeGen/AArch64/known-fpclass-splat-vector.ll b/llvm/test/CodeGen/AArch64/known-fpclass-splat-vector.ll
new file mode 100644
index 0000000000000..644c9a1eeac68
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/known-fpclass-splat-vector.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64 -mattr=+sve < %s | FileCheck %s
+
+define <vscale x 4 x i1> @test_splat_const_is_pos_normal() {
+; CHECK-LABEL: test_splat_const_is_pos_normal:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov z0.s, #1.00000000
+; CHECK-NEXT: mov z1.s, #0x7fffff
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: sub z0.s, z0.s, #1 // =0x1
+; CHECK-NEXT: cmphi p0.s, p0/z, z1.s, z0.s
+; CHECK-NEXT: ret
+ %res = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> splat (float 1.0), i32 128)
+ ret <vscale x 4 x i1> %res
+}
+
+define <vscale x 4 x i1> @test_splat_const_isinf() {
+; CHECK-LABEL: test_splat_const_isinf:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ret
+ %res = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> splat (float 0x7FF0000000000000), i32 516)
+ ret <vscale x 4 x i1> %res
+}
+
+define <vscale x 4 x i1> @test_splat_const_isnan() {
+; CHECK-LABEL: test_splat_const_isnan:
+; CHECK: // %bb.0:
+; CHECK-NEXT: pfalse p0.b
+; CHECK-NEXT: ret
+ %res = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> splat (float 2.0), i32 3)
+ ret <vscale x 4 x i1> %res
+}
diff --git a/llvm/test/CodeGen/RISCV/combine-is_fpclass.ll b/llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
index 0292df415a655..08c1a616b316a 100644
--- a/llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
+++ b/llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
@@ -21,3 +21,53 @@ define i8 @iszero_constant_v4f32() nounwind {
%r = bitcast <8 x i1> %f to i8
ret i8 %r
}
+
+define <vscale x 4 x i1> @splat_constant_is_pos_normal() {
+; CHECK-LABEL: splat_constant_is_pos_normal:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmclr.m v0
+; CHECK-NEXT: ret
+ %res = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> splat (float 1.0), i32 128) ; 128 = pos_normal
+ ret <vscale x 4 x i1> %res
+}
+
+define <vscale x 4 x i1> @splat_constant_isnan_false() {
+; CHECK-LABEL: splat_constant_isnan_false:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmclr.m v0
+; CHECK-NEXT: ret
+ %res = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> splat (float 1.0), i32 3) ; 3 = nan
+ ret <vscale x 4 x i1> %res
+}
+
+define <vscale x 2 x i1> @splat_constant_f64_isinf_false() {
+; CHECK-LABEL: splat_constant_f64_isinf_false:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmclr.m v0
+; CHECK-NEXT: ret
+ %res = call <vscale x 2 x i1> @llvm.is.fpclass.nxv2f64(<vscale x 2 x double> splat (double 1.0), i32 516) ; 516 = inf
+ ret <vscale x 2 x i1> %res
+}
+
+define <vscale x 4 x i1> @test_splat_dynamic_is_not_nan(float %x) {
+; CHECK-LABEL: test_splat_dynamic_is_not_nan:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 260096
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fadd.s fa5, fa0, fa5
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-NEXT: vfmv.v.f v8, fa5
+; CHECK-NEXT: vfclass.v v8, v8
+; CHECK-NEXT: li a0, 255
+; CHECK-NEXT: vand.vx v8, v8, a0
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: ret
+ %val = fadd nnan float %x, 1.0
+ %ins = insertelement <vscale x 4 x float> poison, float %val, i64 0
+ %splat = shufflevector <vscale x 4 x float> %ins, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
+ %res = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> %splat, i32 1020)
+ ret <vscale x 4 x i1> %res
+}
>From 9fb81768f42f83d32ee64052b875b43bd27ad2b5 Mon Sep 17 00:00:00 2001
From: Kartik Ohlan <kartik7ohlan at gmail.com>
Date: Thu, 2 Apr 2026 15:06:23 -0400
Subject: [PATCH 2/3] Remove test_splat_const_isinf function
Removed test_splat_const_isinf function that checks for infinity.
---
llvm/test/CodeGen/AArch64/known-fpclass-splat-vector.ll | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/known-fpclass-splat-vector.ll b/llvm/test/CodeGen/AArch64/known-fpclass-splat-vector.ll
index 644c9a1eeac68..23f04a2d34fea 100644
--- a/llvm/test/CodeGen/AArch64/known-fpclass-splat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/known-fpclass-splat-vector.ll
@@ -14,15 +14,6 @@ define <vscale x 4 x i1> @test_splat_const_is_pos_normal() {
ret <vscale x 4 x i1> %res
}
-define <vscale x 4 x i1> @test_splat_const_isinf() {
-; CHECK-LABEL: test_splat_const_isinf:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: ret
- %res = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> splat (float 0x7FF0000000000000), i32 516)
- ret <vscale x 4 x i1> %res
-}
-
define <vscale x 4 x i1> @test_splat_const_isnan() {
; CHECK-LABEL: test_splat_const_isnan:
; CHECK: // %bb.0:
>From 1558d50205ed19ba1ec13e3a0921b8c959be3d0a Mon Sep 17 00:00:00 2001
From: Kartik Ohlan <kartik7ohlan at gmail.com>
Date: Thu, 2 Apr 2026 15:06:57 -0400
Subject: [PATCH 3/3] Remove test_splat_dynamic_is_not_nan function
Removed the test function for dynamic is_not_nan check.
---
llvm/test/CodeGen/RISCV/combine-is_fpclass.ll | 19 -------------------
1 file changed, 19 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/combine-is_fpclass.ll b/llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
index 08c1a616b316a..5049775710628 100644
--- a/llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
+++ b/llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
@@ -52,22 +52,3 @@ define <vscale x 2 x i1> @splat_constant_f64_isinf_false() {
ret <vscale x 2 x i1> %res
}
-define <vscale x 4 x i1> @test_splat_dynamic_is_not_nan(float %x) {
-; CHECK-LABEL: test_splat_dynamic_is_not_nan:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lui a0, 260096
-; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: fadd.s fa5, fa0, fa5
-; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-NEXT: vfmv.v.f v8, fa5
-; CHECK-NEXT: vfclass.v v8, v8
-; CHECK-NEXT: li a0, 255
-; CHECK-NEXT: vand.vx v8, v8, a0
-; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: ret
- %val = fadd nnan float %x, 1.0
- %ins = insertelement <vscale x 4 x float> poison, float %val, i64 0
- %splat = shufflevector <vscale x 4 x float> %ins, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
- %res = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> %splat, i32 1020)
- ret <vscale x 4 x i1> %res
-}
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