[llvm] [GlobalISel][AArch64] - Add G_UREM computeKnownBits (PR #189087)
Tejas Gaikwad via llvm-commits
llvm-commits at lists.llvm.org
Sat Apr 4 00:10:47 PDT 2026
https://github.com/tejasgaikwad04 updated https://github.com/llvm/llvm-project/pull/189087
>From 4d20a64c45fc617e706e571a409585125ab248bd Mon Sep 17 00:00:00 2001
From: Tejas Gaikwad <tgaikwad966 at gmail.com>
Date: Fri, 27 Mar 2026 18:47:17 +0000
Subject: [PATCH 1/3] [GlobalISel][AArch64] - Add G_UREM computeKnownBits
---
.../CodeGen/GlobalISel/GISelValueTracking.cpp | 30 ++++++++++++++++
.../AArch64/GlobalISel/knownbits-urem.mir | 35 +++++++++++++++++++
2 files changed, 65 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index 245ade77f736e..62c49bd8f581b 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -285,6 +285,36 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
}
break;
}
+ case TargetOpcode::G_UREM: {
+ KnownBits LHSKnown(Known.getBitWidth());
+ KnownBits RHSKnown(Known.getBitWidth());
+
+ computeKnownBitsImpl(MI.getOperand(1).getReg(), LHSKnown, DemandedElts,
+ Depth + 1);
+ computeKnownBitsImpl(MI.getOperand(2).getReg(), RHSKnown, DemandedElts,
+ Depth + 1);
+
+ APInt MaxRHS = RHSKnown.getMaxValue();
+
+ if (MaxRHS.isPowerOf2()) {
+ unsigned LowBits = MaxRHS.logBase2();
+ // Upper bits are zero
+ Known.Zero.setBitsFrom(LowBits);
+ // Mask for lower bits
+ APInt Mask = APInt::getLowBitsSet(Known.getBitWidth(), LowBits);
+ // Propagate known bits from LHS for lower bits
+ Known.One |= (LHSKnown.One & Mask);
+ Known.Zero |= (LHSKnown.Zero & Mask);
+ break;
+ }
+ if (!MaxRHS.isZero()) {
+ unsigned LeadingZeros = MaxRHS.countLeadingZeros();
+ Known.Zero.setHighBits(LeadingZeros);
+ }
+
+ break;
+ }
+
case TargetOpcode::G_CONSTANT: {
Known = KnownBits::makeConstant(MI.getOperand(1).getCImm()->getValue());
break;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
new file mode 100644
index 0000000000000..f164d32a11bd3
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
@@ -0,0 +1,35 @@
+# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple aarch64 -passes="print<gisel-value-tracking>" %s -filetype=null 2>&1 | FileCheck %s
+
+--- |
+ ; ModuleID = 'urem_aarch64_gisel_test.ll'
+ source_filename = "urem_aarch64_gisel_test.ll"
+ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
+ target triple = "aarch64"
+
+ define i32 @urem_pow2(i32 %x) {
+ %y = urem i32 %x, 8
+ ret i32 %y
+ }
+...
+---
+name: urem_pow2
+
+body: |
+ bb.1 (%ir-block.0):
+
+ ; CHECK-LABEL: name: @urem_pow2
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:00000000000000000000000000001000 SignBits:28
+ ; CHECK-NEXT: %2:_ KnownBits:00000000000000000000000000000??? SignBits:29
+
+ liveins: $w0
+
+ %0:_(s32) = COPY $w0
+ %1:_(s32) = G_CONSTANT i32 8
+ %2:_(s32) = G_UREM %0, %1
+ $w0 = COPY %2(s32)
+ RET_ReallyLR implicit $w0
+...
+## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+# CHECK: {{.*}}
>From 14937554485d960430b17c403b94738a679ba311 Mon Sep 17 00:00:00 2001
From: Tejas Gaikwad <tgaikwad966 at gmail.com>
Date: Sun, 29 Mar 2026 17:35:49 +0000
Subject: [PATCH 2/3] resolving comments
---
.../CodeGen/GlobalISel/GISelValueTracking.cpp | 8 ++++----
.../AArch64/GlobalISel/knownbits-urem.mir | 17 +----------------
2 files changed, 5 insertions(+), 20 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index 62c49bd8f581b..dbe7ae85f2877 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -301,10 +301,10 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
// Upper bits are zero
Known.Zero.setBitsFrom(LowBits);
// Mask for lower bits
- APInt Mask = APInt::getLowBitsSet(Known.getBitWidth(), LowBits);
- // Propagate known bits from LHS for lower bits
- Known.One |= (LHSKnown.One & Mask);
- Known.Zero |= (LHSKnown.Zero & Mask);
+ KnownBits TruncLHS = LHSKnown.trunc(LowBits).zext(Known.getBitWidth());
+
+ Known.One |= TruncLHS.One;
+ Known.Zero |= TruncLHS.Zero;
break;
}
if (!MaxRHS.isZero()) {
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
index f164d32a11bd3..b5c70f46a35cc 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-urem.mir
@@ -1,22 +1,10 @@
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple aarch64 -passes="print<gisel-value-tracking>" %s -filetype=null 2>&1 | FileCheck %s
---- |
- ; ModuleID = 'urem_aarch64_gisel_test.ll'
- source_filename = "urem_aarch64_gisel_test.ll"
- target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
- target triple = "aarch64"
-
- define i32 @urem_pow2(i32 %x) {
- %y = urem i32 %x, 8
- ret i32 %y
- }
-...
----
name: urem_pow2
body: |
- bb.1 (%ir-block.0):
+ bb.1:
; CHECK-LABEL: name: @urem_pow2
; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
@@ -30,6 +18,3 @@ body: |
%2:_(s32) = G_UREM %0, %1
$w0 = COPY %2(s32)
RET_ReallyLR implicit $w0
-...
-## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-# CHECK: {{.*}}
>From 32cf8ef99175fe406fc231d5fe6c49bc26e379e8 Mon Sep 17 00:00:00 2001
From: Tejas Gaikwad <tgaikwad966 at gmail.com>
Date: Sat, 4 Apr 2026 07:03:23 +0000
Subject: [PATCH 3/3] Dummy_comment_to_trigger_build_cmd
---
llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index 9bfd0ce62c858..9756db713ffdd 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -285,6 +285,7 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
}
break;
}
+ //support for G_UREM
case TargetOpcode::G_UREM: {
KnownBits LHSKnown(Known.getBitWidth());
KnownBits RHSKnown(Known.getBitWidth());
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