[llvm] [RISCV] Lower (select c, y, 0) -> (qc.muliadd c, y-1) (PR #190323)

Sudharsan Veeravalli via llvm-commits llvm-commits at lists.llvm.org
Fri Apr 3 19:48:26 PDT 2026


================
@@ -99,6 +105,8 @@ def uimm10 : RISCVUImmLeafOp<10>;
 
 def uimm11 : RISCVUImmLeafOp<11>;
 
+def timm12 : TImmLeaf<XLenVT, [{return isInt<12>(Imm);}]>;
----------------
svs-quic wrote:

Given that we are creating a `target constant` the selection DAG expects to find the same in the pattern. I had tried the normal `simm12_lo` and it failed to match. Pasting from the `MatcherTable` in `RISCVGenDAGISel.inc`:

```
20, TARGET_VAL(RISCVISD::QC_MULIADD),
  OPC_RecordChild0,
  OPC_RecordChild1,
  OPC_RecordChild2,
  OPC_MoveChild2,
  OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
  OPC_CheckPredicate, 28,
  OPC_CheckTypeI32,
  OPC_MoveParent,
  OPC_CheckTypeI32,
  OPC_CheckPatternPredicate, 119,
  OPC_MorphNodeTo1None, TARGET_VAL(RISCV::QC_MULIADD),
                  MVT::i32, 3, 39,
```

https://github.com/llvm/llvm-project/pull/190323


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