[llvm] [ARM] Add new test that will demonstrate the cmn node in the ARM backend (NFC) (PR #179282)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 3 10:15:04 PDT 2026
https://github.com/SiliconA-Z updated https://github.com/llvm/llvm-project/pull/179282
>From c3d4c871e5d0306ea57ec2dc5a4871b8bfaf2d63 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Mon, 13 Oct 2025 13:51:16 -0400
Subject: [PATCH] [ARM] Add new test that will demonstrate the cmn node in the
ARM backend (NFC)
No code changes yet, but this is going to change once the cmn node lands in the backend.
---
llvm/test/CodeGen/ARM/cmp-to-cmn.ll | 2200 +++++++++++++++++++++++++++
1 file changed, 2200 insertions(+)
create mode 100644 llvm/test/CodeGen/ARM/cmp-to-cmn.ll
diff --git a/llvm/test/CodeGen/ARM/cmp-to-cmn.ll b/llvm/test/CodeGen/ARM/cmp-to-cmn.ll
new file mode 100644
index 0000000000000..12659a55bfc4b
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/cmp-to-cmn.ll
@@ -0,0 +1,2200 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=armv7 %s -o - | FileCheck %s --check-prefixes=CHECK-ARM
+; RUN: llc -mtriple=thumb-eabi -mcpu=arm7tdmi %s -o - | FileCheck %s --check-prefix=CHECK-T1
+; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s --check-prefix=CHECK-T2
+
+define i1 @test_EQ_IllEbT(i64 %a, i64 %b) {
+; CHECK-ARM-LABEL: test_EQ_IllEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: rsbs r2, r2, #0
+; CHECK-ARM-NEXT: eor r0, r2, r0
+; CHECK-ARM-NEXT: rsc r2, r3, #0
+; CHECK-ARM-NEXT: eor r1, r2, r1
+; CHECK-ARM-NEXT: orr r0, r0, r1
+; CHECK-ARM-NEXT: clz r0, r0
+; CHECK-ARM-NEXT: lsr r0, r0, #5
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_EQ_IllEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: .save {r4, lr}
+; CHECK-T1-NEXT: push {r4, lr}
+; CHECK-T1-NEXT: movs r4, #0
+; CHECK-T1-NEXT: rsbs r2, r2, #0
+; CHECK-T1-NEXT: sbcs r4, r3
+; CHECK-T1-NEXT: eors r4, r1
+; CHECK-T1-NEXT: eors r0, r2
+; CHECK-T1-NEXT: orrs r0, r4
+; CHECK-T1-NEXT: rsbs r1, r0, #0
+; CHECK-T1-NEXT: adcs r0, r1
+; CHECK-T1-NEXT: pop {r4}
+; CHECK-T1-NEXT: pop {r1}
+; CHECK-T1-NEXT: bx r1
+;
+; CHECK-T2-LABEL: test_EQ_IllEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: rsbs r2, r2, #0
+; CHECK-T2-NEXT: mov.w r12, #0
+; CHECK-T2-NEXT: sbc.w r3, r12, r3
+; CHECK-T2-NEXT: eors r1, r3
+; CHECK-T2-NEXT: eors r0, r2
+; CHECK-T2-NEXT: orrs r0, r1
+; CHECK-T2-NEXT: clz r0, r0
+; CHECK-T2-NEXT: lsrs r0, r0, #5
+; CHECK-T2-NEXT: bx lr
+entry:
+ %add = sub i64 0, %b
+ %cmp = icmp eq i64 %add, %a
+ ret i1 %cmp
+}
+
+define i1 @test_EQ_IliEbT(i64 %a, i32 %b) {
+; CHECK-ARM-LABEL: test_EQ_IliEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: rsbs r0, r0, #0
+; CHECK-ARM-NEXT: rsc r1, r1, #0
+; CHECK-ARM-NEXT: eor r0, r2, r0
+; CHECK-ARM-NEXT: eor r1, r1, r2, asr #31
+; CHECK-ARM-NEXT: orr r0, r0, r1
+; CHECK-ARM-NEXT: clz r0, r0
+; CHECK-ARM-NEXT: lsr r0, r0, #5
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_EQ_IliEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: .save {r4, lr}
+; CHECK-T1-NEXT: push {r4, lr}
+; CHECK-T1-NEXT: movs r3, #0
+; CHECK-T1-NEXT: rsbs r4, r0, #0
+; CHECK-T1-NEXT: sbcs r3, r1
+; CHECK-T1-NEXT: asrs r0, r2, #31
+; CHECK-T1-NEXT: eors r0, r3
+; CHECK-T1-NEXT: eors r4, r2
+; CHECK-T1-NEXT: orrs r4, r0
+; CHECK-T1-NEXT: rsbs r0, r4, #0
+; CHECK-T1-NEXT: adcs r0, r4
+; CHECK-T1-NEXT: pop {r4}
+; CHECK-T1-NEXT: pop {r1}
+; CHECK-T1-NEXT: bx r1
+;
+; CHECK-T2-LABEL: test_EQ_IliEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: rsbs r0, r0, #0
+; CHECK-T2-NEXT: mov.w r3, #0
+; CHECK-T2-NEXT: sbc.w r1, r3, r1
+; CHECK-T2-NEXT: eor.w r1, r1, r2, asr #31
+; CHECK-T2-NEXT: eors r0, r2
+; CHECK-T2-NEXT: orrs r0, r1
+; CHECK-T2-NEXT: clz r0, r0
+; CHECK-T2-NEXT: lsrs r0, r0, #5
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = sext i32 %b to i64
+ %add = sub i64 0, %a
+ %cmp = icmp eq i64 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @test_EQ_IlsEbT(i64 %a, i16 %b) {
+; CHECK-ARM-LABEL: test_EQ_IlsEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: rsbs r0, r0, #0
+; CHECK-ARM-NEXT: sxth r2, r2
+; CHECK-ARM-NEXT: rsc r1, r1, #0
+; CHECK-ARM-NEXT: eor r0, r2, r0
+; CHECK-ARM-NEXT: eor r1, r1, r2, asr #31
+; CHECK-ARM-NEXT: orr r0, r0, r1
+; CHECK-ARM-NEXT: clz r0, r0
+; CHECK-ARM-NEXT: lsr r0, r0, #5
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_EQ_IlsEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: movs r3, #0
+; CHECK-T1-NEXT: rsbs r0, r0, #0
+; CHECK-T1-NEXT: sbcs r3, r1
+; CHECK-T1-NEXT: lsls r1, r2, #16
+; CHECK-T1-NEXT: asrs r2, r1, #31
+; CHECK-T1-NEXT: eors r2, r3
+; CHECK-T1-NEXT: asrs r1, r1, #16
+; CHECK-T1-NEXT: eors r1, r0
+; CHECK-T1-NEXT: orrs r1, r2
+; CHECK-T1-NEXT: rsbs r0, r1, #0
+; CHECK-T1-NEXT: adcs r0, r1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: test_EQ_IlsEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: movs r3, #0
+; CHECK-T2-NEXT: rsbs r0, r0, #0
+; CHECK-T2-NEXT: sxth r2, r2
+; CHECK-T2-NEXT: sbc.w r1, r3, r1
+; CHECK-T2-NEXT: eor.w r1, r1, r2, asr #31
+; CHECK-T2-NEXT: eors r0, r2
+; CHECK-T2-NEXT: orrs r0, r1
+; CHECK-T2-NEXT: clz r0, r0
+; CHECK-T2-NEXT: lsrs r0, r0, #5
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = sext i16 %b to i64
+ %add = sub i64 0, %a
+ %cmp = icmp eq i64 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @test_EQ_IlcEbT(i64 %a, i8 %b) {
+; CHECK-ARM-LABEL: test_EQ_IlcEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: rsbs r0, r0, #0
+; CHECK-ARM-NEXT: uxtb r2, r2
+; CHECK-ARM-NEXT: rsc r1, r1, #0
+; CHECK-ARM-NEXT: eor r0, r2, r0
+; CHECK-ARM-NEXT: orr r0, r0, r1
+; CHECK-ARM-NEXT: clz r0, r0
+; CHECK-ARM-NEXT: lsr r0, r0, #5
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_EQ_IlcEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: movs r3, #0
+; CHECK-T1-NEXT: rsbs r0, r0, #0
+; CHECK-T1-NEXT: sbcs r3, r1
+; CHECK-T1-NEXT: movs r1, #255
+; CHECK-T1-NEXT: ands r1, r2
+; CHECK-T1-NEXT: eors r1, r0
+; CHECK-T1-NEXT: orrs r1, r3
+; CHECK-T1-NEXT: rsbs r0, r1, #0
+; CHECK-T1-NEXT: adcs r0, r1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: test_EQ_IlcEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: movs r3, #0
+; CHECK-T2-NEXT: rsbs r0, r0, #0
+; CHECK-T2-NEXT: uxtb r2, r2
+; CHECK-T2-NEXT: sbc.w r1, r3, r1
+; CHECK-T2-NEXT: eors r0, r2
+; CHECK-T2-NEXT: orrs r0, r1
+; CHECK-T2-NEXT: clz r0, r0
+; CHECK-T2-NEXT: lsrs r0, r0, #5
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = zext i8 %b to i64
+ %add = sub i64 0, %a
+ %cmp = icmp eq i64 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @test_EQ_IilEbT(i32 %a, i64 %b) {
+; CHECK-ARM-LABEL: test_EQ_IilEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: rsbs r1, r2, #0
+; CHECK-ARM-NEXT: rsc r2, r3, #0
+; CHECK-ARM-NEXT: eor r1, r0, r1
+; CHECK-ARM-NEXT: eor r0, r2, r0, asr #31
+; CHECK-ARM-NEXT: orr r0, r1, r0
+; CHECK-ARM-NEXT: clz r0, r0
+; CHECK-ARM-NEXT: lsr r0, r0, #5
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_EQ_IilEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: movs r1, #0
+; CHECK-T1-NEXT: rsbs r2, r2, #0
+; CHECK-T1-NEXT: sbcs r1, r3
+; CHECK-T1-NEXT: asrs r3, r0, #31
+; CHECK-T1-NEXT: eors r3, r1
+; CHECK-T1-NEXT: eors r0, r2
+; CHECK-T1-NEXT: orrs r0, r3
+; CHECK-T1-NEXT: rsbs r1, r0, #0
+; CHECK-T1-NEXT: adcs r0, r1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: test_EQ_IilEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: movs r1, #0
+; CHECK-T2-NEXT: rsbs r2, r2, #0
+; CHECK-T2-NEXT: sbcs r1, r3
+; CHECK-T2-NEXT: eor.w r1, r1, r0, asr #31
+; CHECK-T2-NEXT: eors r0, r2
+; CHECK-T2-NEXT: orrs r0, r1
+; CHECK-T2-NEXT: clz r0, r0
+; CHECK-T2-NEXT: lsrs r0, r0, #5
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = sext i32 %a to i64
+ %add = sub i64 0, %b
+ %cmp = icmp eq i64 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @test_EQ_IiiEbT(i32 %a, i32 %b) {
+; CHECK-ARM-LABEL: test_EQ_IiiEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: add r0, r1, r0
+; CHECK-ARM-NEXT: rsb r0, r0, #0
+; CHECK-ARM-NEXT: clz r0, r0
+; CHECK-ARM-NEXT: lsr r0, r0, #5
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_EQ_IiiEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: adds r0, r1, r0
+; CHECK-T1-NEXT: rsbs r1, r0, #0
+; CHECK-T1-NEXT: rsbs r0, r1, #0
+; CHECK-T1-NEXT: adcs r0, r1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: test_EQ_IiiEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: add r0, r1
+; CHECK-T2-NEXT: rsbs r0, r0, #0
+; CHECK-T2-NEXT: clz r0, r0
+; CHECK-T2-NEXT: lsrs r0, r0, #5
+; CHECK-T2-NEXT: bx lr
+entry:
+ %add = sub i32 0, %b
+ %cmp = icmp eq i32 %add, %a
+ ret i1 %cmp
+}
+
+define i1 @test_EQ_IisEbT(i32 %a, i16 %b) {
+; CHECK-ARM-LABEL: test_EQ_IisEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: sxtah r0, r0, r1
+; CHECK-ARM-NEXT: clz r0, r0
+; CHECK-ARM-NEXT: lsr r0, r0, #5
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_EQ_IisEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: lsls r1, r1, #16
+; CHECK-T1-NEXT: asrs r1, r1, #16
+; CHECK-T1-NEXT: adds r0, r0, r1
+; CHECK-T1-NEXT: rsbs r1, r0, #0
+; CHECK-T1-NEXT: rsbs r0, r1, #0
+; CHECK-T1-NEXT: adcs r0, r1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: test_EQ_IisEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: sxtah r0, r0, r1
+; CHECK-T2-NEXT: clz r0, r0
+; CHECK-T2-NEXT: lsrs r0, r0, #5
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = sext i16 %b to i32
+ %add = sub i32 0, %a
+ %cmp = icmp eq i32 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @test_EQ_IicEbT(i32 %a, i8 %b) {
+; CHECK-ARM-LABEL: test_EQ_IicEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: uxtab r0, r0, r1
+; CHECK-ARM-NEXT: clz r0, r0
+; CHECK-ARM-NEXT: lsr r0, r0, #5
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_EQ_IicEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: movs r2, #255
+; CHECK-T1-NEXT: ands r2, r1
+; CHECK-T1-NEXT: adds r1, r2, r0
+; CHECK-T1-NEXT: rsbs r0, r1, #0
+; CHECK-T1-NEXT: adcs r0, r1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: test_EQ_IicEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: uxtab r0, r0, r1
+; CHECK-T2-NEXT: clz r0, r0
+; CHECK-T2-NEXT: lsrs r0, r0, #5
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = zext i8 %b to i32
+ %add = sub i32 0, %a
+ %cmp = icmp eq i32 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @test_EQ_IslEbT(i16 %a, i64 %b) {
+; CHECK-ARM-LABEL: test_EQ_IslEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: rsbs r1, r2, #0
+; CHECK-ARM-NEXT: sxth r0, r0
+; CHECK-ARM-NEXT: rsc r2, r3, #0
+; CHECK-ARM-NEXT: eor r1, r0, r1
+; CHECK-ARM-NEXT: eor r0, r2, r0, asr #31
+; CHECK-ARM-NEXT: orr r0, r1, r0
+; CHECK-ARM-NEXT: clz r0, r0
+; CHECK-ARM-NEXT: lsr r0, r0, #5
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_EQ_IslEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: movs r1, #0
+; CHECK-T1-NEXT: rsbs r2, r2, #0
+; CHECK-T1-NEXT: sbcs r1, r3
+; CHECK-T1-NEXT: lsls r0, r0, #16
+; CHECK-T1-NEXT: asrs r3, r0, #31
+; CHECK-T1-NEXT: eors r3, r1
+; CHECK-T1-NEXT: asrs r1, r0, #16
+; CHECK-T1-NEXT: eors r1, r2
+; CHECK-T1-NEXT: orrs r1, r3
+; CHECK-T1-NEXT: rsbs r0, r1, #0
+; CHECK-T1-NEXT: adcs r0, r1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: test_EQ_IslEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: movs r1, #0
+; CHECK-T2-NEXT: rsbs r2, r2, #0
+; CHECK-T2-NEXT: sbcs r1, r3
+; CHECK-T2-NEXT: sxth r0, r0
+; CHECK-T2-NEXT: eor.w r1, r1, r0, asr #31
+; CHECK-T2-NEXT: eors r0, r2
+; CHECK-T2-NEXT: orrs r0, r1
+; CHECK-T2-NEXT: clz r0, r0
+; CHECK-T2-NEXT: lsrs r0, r0, #5
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = sext i16 %a to i64
+ %add = sub i64 0, %b
+ %cmp = icmp eq i64 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @test_EQ_IsiEbT(i16 %a, i32 %b) {
+; CHECK-ARM-LABEL: test_EQ_IsiEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: sxtah r0, r1, r0
+; CHECK-ARM-NEXT: clz r0, r0
+; CHECK-ARM-NEXT: lsr r0, r0, #5
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_EQ_IsiEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: lsls r0, r0, #16
+; CHECK-T1-NEXT: asrs r0, r0, #16
+; CHECK-T1-NEXT: adds r0, r1, r0
+; CHECK-T1-NEXT: rsbs r1, r0, #0
+; CHECK-T1-NEXT: rsbs r0, r1, #0
+; CHECK-T1-NEXT: adcs r0, r1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: test_EQ_IsiEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: sxtah r0, r1, r0
+; CHECK-T2-NEXT: clz r0, r0
+; CHECK-T2-NEXT: lsrs r0, r0, #5
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = sext i16 %a to i32
+ %add = sub i32 0, %b
+ %cmp = icmp eq i32 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @test_EQ_IssEbT(i16 %a, i16 %b) {
+; CHECK-ARM-LABEL: test_EQ_IssEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: sxth r0, r0
+; CHECK-ARM-NEXT: sxtah r0, r0, r1
+; CHECK-ARM-NEXT: clz r0, r0
+; CHECK-ARM-NEXT: lsr r0, r0, #5
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_EQ_IssEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: lsls r0, r0, #16
+; CHECK-T1-NEXT: asrs r0, r0, #16
+; CHECK-T1-NEXT: lsls r1, r1, #16
+; CHECK-T1-NEXT: asrs r1, r1, #16
+; CHECK-T1-NEXT: adds r0, r1, r0
+; CHECK-T1-NEXT: rsbs r1, r0, #0
+; CHECK-T1-NEXT: rsbs r0, r1, #0
+; CHECK-T1-NEXT: adcs r0, r1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: test_EQ_IssEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: sxth r0, r0
+; CHECK-T2-NEXT: sxtah r0, r0, r1
+; CHECK-T2-NEXT: clz r0, r0
+; CHECK-T2-NEXT: lsrs r0, r0, #5
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = sext i16 %a to i32
+ %conv1 = sext i16 %b to i32
+ %add = sub nsw i32 0, %conv1
+ %cmp = icmp eq i32 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @test_EQ_IscEbT(i16 %a, i8 %b) {
+; CHECK-ARM-LABEL: test_EQ_IscEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: sxth r0, r0
+; CHECK-ARM-NEXT: uxtab r0, r0, r1
+; CHECK-ARM-NEXT: clz r0, r0
+; CHECK-ARM-NEXT: lsr r0, r0, #5
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_EQ_IscEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: movs r2, #255
+; CHECK-T1-NEXT: ands r2, r1
+; CHECK-T1-NEXT: lsls r0, r0, #16
+; CHECK-T1-NEXT: asrs r0, r0, #16
+; CHECK-T1-NEXT: adds r0, r2, r0
+; CHECK-T1-NEXT: rsbs r1, r0, #0
+; CHECK-T1-NEXT: rsbs r0, r1, #0
+; CHECK-T1-NEXT: adcs r0, r1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: test_EQ_IscEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: sxth r0, r0
+; CHECK-T2-NEXT: uxtab r0, r0, r1
+; CHECK-T2-NEXT: clz r0, r0
+; CHECK-T2-NEXT: lsrs r0, r0, #5
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = sext i16 %a to i32
+ %conv1 = zext i8 %b to i32
+ %add = sub nsw i32 0, %conv1
+ %cmp = icmp eq i32 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @test_EQ_IclEbT(i8 %a, i64 %b) {
+; CHECK-ARM-LABEL: test_EQ_IclEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: rsbs r1, r2, #0
+; CHECK-ARM-NEXT: uxtb r0, r0
+; CHECK-ARM-NEXT: rsc r2, r3, #0
+; CHECK-ARM-NEXT: eor r0, r0, r1
+; CHECK-ARM-NEXT: orr r0, r0, r2
+; CHECK-ARM-NEXT: clz r0, r0
+; CHECK-ARM-NEXT: lsr r0, r0, #5
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_EQ_IclEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: movs r1, #0
+; CHECK-T1-NEXT: rsbs r2, r2, #0
+; CHECK-T1-NEXT: sbcs r1, r3
+; CHECK-T1-NEXT: movs r3, #255
+; CHECK-T1-NEXT: ands r0, r3
+; CHECK-T1-NEXT: eors r0, r2
+; CHECK-T1-NEXT: orrs r0, r1
+; CHECK-T1-NEXT: rsbs r1, r0, #0
+; CHECK-T1-NEXT: adcs r0, r1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: test_EQ_IclEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: movs r1, #0
+; CHECK-T2-NEXT: rsbs r2, r2, #0
+; CHECK-T2-NEXT: uxtb r0, r0
+; CHECK-T2-NEXT: sbcs r1, r3
+; CHECK-T2-NEXT: eors r0, r2
+; CHECK-T2-NEXT: orrs r0, r1
+; CHECK-T2-NEXT: clz r0, r0
+; CHECK-T2-NEXT: lsrs r0, r0, #5
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = zext i8 %a to i64
+ %add = sub i64 0, %b
+ %cmp = icmp eq i64 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @test_EQ_IciEbT(i8 %a, i32 %b) {
+; CHECK-ARM-LABEL: test_EQ_IciEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: uxtab r0, r1, r0
+; CHECK-ARM-NEXT: clz r0, r0
+; CHECK-ARM-NEXT: lsr r0, r0, #5
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_EQ_IciEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: movs r2, #255
+; CHECK-T1-NEXT: ands r2, r0
+; CHECK-T1-NEXT: adds r1, r2, r1
+; CHECK-T1-NEXT: rsbs r0, r1, #0
+; CHECK-T1-NEXT: adcs r0, r1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: test_EQ_IciEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: uxtab r0, r1, r0
+; CHECK-T2-NEXT: clz r0, r0
+; CHECK-T2-NEXT: lsrs r0, r0, #5
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = zext i8 %a to i32
+ %add = sub i32 0, %b
+ %cmp = icmp eq i32 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @test_EQ_IcsEbT(i8 %a, i16 %b) {
+; CHECK-ARM-LABEL: test_EQ_IcsEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: sxth r1, r1
+; CHECK-ARM-NEXT: uxtab r0, r1, r0
+; CHECK-ARM-NEXT: clz r0, r0
+; CHECK-ARM-NEXT: lsr r0, r0, #5
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_EQ_IcsEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: movs r2, #255
+; CHECK-T1-NEXT: ands r2, r0
+; CHECK-T1-NEXT: lsls r0, r1, #16
+; CHECK-T1-NEXT: asrs r0, r0, #16
+; CHECK-T1-NEXT: adds r1, r2, r0
+; CHECK-T1-NEXT: rsbs r0, r1, #0
+; CHECK-T1-NEXT: adcs r0, r1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: test_EQ_IcsEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: sxth r1, r1
+; CHECK-T2-NEXT: uxtab r0, r1, r0
+; CHECK-T2-NEXT: clz r0, r0
+; CHECK-T2-NEXT: lsrs r0, r0, #5
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = zext i8 %a to i32
+ %conv1 = sext i16 %b to i32
+ %add = sub nsw i32 0, %conv1
+ %cmp = icmp eq i32 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @test_EQ_IccEbT(i8 %a, i8 %b) {
+; CHECK-ARM-LABEL: test_EQ_IccEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: uxtb r0, r0
+; CHECK-ARM-NEXT: uxtab r0, r0, r1
+; CHECK-ARM-NEXT: clz r0, r0
+; CHECK-ARM-NEXT: lsr r0, r0, #5
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_EQ_IccEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: movs r2, #255
+; CHECK-T1-NEXT: ands r1, r2
+; CHECK-T1-NEXT: ands r0, r2
+; CHECK-T1-NEXT: adds r1, r0, r1
+; CHECK-T1-NEXT: rsbs r0, r1, #0
+; CHECK-T1-NEXT: adcs r0, r1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: test_EQ_IccEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: uxtb r0, r0
+; CHECK-T2-NEXT: uxtab r0, r0, r1
+; CHECK-T2-NEXT: clz r0, r0
+; CHECK-T2-NEXT: lsrs r0, r0, #5
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = zext i8 %a to i32
+ %conv1 = zext i8 %b to i32
+ %add = sub nsw i32 0, %conv1
+ %cmp = icmp eq i32 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @test_NE_IllEbT(i64 %a, i64 %b) {
+; CHECK-ARM-LABEL: test_NE_IllEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: rsbs r2, r2, #0
+; CHECK-ARM-NEXT: eor r0, r2, r0
+; CHECK-ARM-NEXT: rsc r2, r3, #0
+; CHECK-ARM-NEXT: eor r1, r2, r1
+; CHECK-ARM-NEXT: orrs r0, r0, r1
+; CHECK-ARM-NEXT: movwne r0, #1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_NE_IllEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: .save {r4, lr}
+; CHECK-T1-NEXT: push {r4, lr}
+; CHECK-T1-NEXT: movs r4, #0
+; CHECK-T1-NEXT: rsbs r2, r2, #0
+; CHECK-T1-NEXT: sbcs r4, r3
+; CHECK-T1-NEXT: eors r4, r1
+; CHECK-T1-NEXT: eors r0, r2
+; CHECK-T1-NEXT: orrs r0, r4
+; CHECK-T1-NEXT: subs r1, r0, #1
+; CHECK-T1-NEXT: sbcs r0, r1
+; CHECK-T1-NEXT: pop {r4}
+; CHECK-T1-NEXT: pop {r1}
+; CHECK-T1-NEXT: bx r1
+;
+; CHECK-T2-LABEL: test_NE_IllEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: rsbs r2, r2, #0
+; CHECK-T2-NEXT: mov.w r12, #0
+; CHECK-T2-NEXT: sbc.w r3, r12, r3
+; CHECK-T2-NEXT: eors r1, r3
+; CHECK-T2-NEXT: eors r0, r2
+; CHECK-T2-NEXT: orrs r0, r1
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: movne r0, #1
+; CHECK-T2-NEXT: bx lr
+entry:
+ %add = sub i64 0, %b
+ %cmp = icmp ne i64 %add, %a
+ ret i1 %cmp
+}
+
+define i1 @test_NE_IliEbT(i64 %a, i32 %b) {
+; CHECK-ARM-LABEL: test_NE_IliEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: rsbs r0, r0, #0
+; CHECK-ARM-NEXT: rsc r1, r1, #0
+; CHECK-ARM-NEXT: eor r0, r2, r0
+; CHECK-ARM-NEXT: eor r1, r1, r2, asr #31
+; CHECK-ARM-NEXT: orrs r0, r0, r1
+; CHECK-ARM-NEXT: movwne r0, #1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_NE_IliEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: movs r3, #0
+; CHECK-T1-NEXT: rsbs r0, r0, #0
+; CHECK-T1-NEXT: sbcs r3, r1
+; CHECK-T1-NEXT: asrs r1, r2, #31
+; CHECK-T1-NEXT: eors r1, r3
+; CHECK-T1-NEXT: eors r0, r2
+; CHECK-T1-NEXT: orrs r0, r1
+; CHECK-T1-NEXT: subs r1, r0, #1
+; CHECK-T1-NEXT: sbcs r0, r1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: test_NE_IliEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: rsbs r0, r0, #0
+; CHECK-T2-NEXT: mov.w r3, #0
+; CHECK-T2-NEXT: sbc.w r1, r3, r1
+; CHECK-T2-NEXT: eor.w r1, r1, r2, asr #31
+; CHECK-T2-NEXT: eors r0, r2
+; CHECK-T2-NEXT: orrs r0, r1
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: movne r0, #1
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = sext i32 %b to i64
+ %add = sub i64 0, %a
+ %cmp = icmp ne i64 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @test_NE_IlsEbT(i64 %a, i16 %b) {
+; CHECK-ARM-LABEL: test_NE_IlsEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: rsbs r0, r0, #0
+; CHECK-ARM-NEXT: sxth r2, r2
+; CHECK-ARM-NEXT: rsc r1, r1, #0
+; CHECK-ARM-NEXT: eor r0, r2, r0
+; CHECK-ARM-NEXT: eor r1, r1, r2, asr #31
+; CHECK-ARM-NEXT: orrs r0, r0, r1
+; CHECK-ARM-NEXT: movwne r0, #1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_NE_IlsEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: .save {r4, lr}
+; CHECK-T1-NEXT: push {r4, lr}
+; CHECK-T1-NEXT: movs r3, #0
+; CHECK-T1-NEXT: rsbs r4, r0, #0
+; CHECK-T1-NEXT: sbcs r3, r1
+; CHECK-T1-NEXT: lsls r0, r2, #16
+; CHECK-T1-NEXT: asrs r1, r0, #31
+; CHECK-T1-NEXT: eors r1, r3
+; CHECK-T1-NEXT: asrs r0, r0, #16
+; CHECK-T1-NEXT: eors r0, r4
+; CHECK-T1-NEXT: orrs r0, r1
+; CHECK-T1-NEXT: subs r1, r0, #1
+; CHECK-T1-NEXT: sbcs r0, r1
+; CHECK-T1-NEXT: pop {r4}
+; CHECK-T1-NEXT: pop {r1}
+; CHECK-T1-NEXT: bx r1
+;
+; CHECK-T2-LABEL: test_NE_IlsEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: movs r3, #0
+; CHECK-T2-NEXT: rsbs r0, r0, #0
+; CHECK-T2-NEXT: sxth r2, r2
+; CHECK-T2-NEXT: sbc.w r1, r3, r1
+; CHECK-T2-NEXT: eor.w r1, r1, r2, asr #31
+; CHECK-T2-NEXT: eors r0, r2
+; CHECK-T2-NEXT: orrs r0, r1
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: movne r0, #1
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = sext i16 %b to i64
+ %add = sub i64 0, %a
+ %cmp = icmp ne i64 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @test_NE_IlcEbT(i64 %a, i8 %b) {
+; CHECK-ARM-LABEL: test_NE_IlcEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: rsbs r0, r0, #0
+; CHECK-ARM-NEXT: uxtb r2, r2
+; CHECK-ARM-NEXT: rsc r1, r1, #0
+; CHECK-ARM-NEXT: eor r0, r2, r0
+; CHECK-ARM-NEXT: orrs r0, r0, r1
+; CHECK-ARM-NEXT: movwne r0, #1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_NE_IlcEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: .save {r4, lr}
+; CHECK-T1-NEXT: push {r4, lr}
+; CHECK-T1-NEXT: movs r3, #0
+; CHECK-T1-NEXT: rsbs r4, r0, #0
+; CHECK-T1-NEXT: sbcs r3, r1
+; CHECK-T1-NEXT: movs r0, #255
+; CHECK-T1-NEXT: ands r0, r2
+; CHECK-T1-NEXT: eors r0, r4
+; CHECK-T1-NEXT: orrs r0, r3
+; CHECK-T1-NEXT: subs r1, r0, #1
+; CHECK-T1-NEXT: sbcs r0, r1
+; CHECK-T1-NEXT: pop {r4}
+; CHECK-T1-NEXT: pop {r1}
+; CHECK-T1-NEXT: bx r1
+;
+; CHECK-T2-LABEL: test_NE_IlcEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: movs r3, #0
+; CHECK-T2-NEXT: rsbs r0, r0, #0
+; CHECK-T2-NEXT: uxtb r2, r2
+; CHECK-T2-NEXT: sbc.w r1, r3, r1
+; CHECK-T2-NEXT: eors r0, r2
+; CHECK-T2-NEXT: orrs r0, r1
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: movne r0, #1
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = zext i8 %b to i64
+ %add = sub i64 0, %a
+ %cmp = icmp ne i64 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @test_NE_IilEbT(i32 %a, i64 %b) {
+; CHECK-ARM-LABEL: test_NE_IilEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: rsbs r1, r2, #0
+; CHECK-ARM-NEXT: rsc r2, r3, #0
+; CHECK-ARM-NEXT: eor r1, r0, r1
+; CHECK-ARM-NEXT: eor r0, r2, r0, asr #31
+; CHECK-ARM-NEXT: orrs r0, r1, r0
+; CHECK-ARM-NEXT: movwne r0, #1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_NE_IilEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: movs r1, #0
+; CHECK-T1-NEXT: rsbs r2, r2, #0
+; CHECK-T1-NEXT: sbcs r1, r3
+; CHECK-T1-NEXT: asrs r3, r0, #31
+; CHECK-T1-NEXT: eors r3, r1
+; CHECK-T1-NEXT: eors r0, r2
+; CHECK-T1-NEXT: orrs r0, r3
+; CHECK-T1-NEXT: subs r1, r0, #1
+; CHECK-T1-NEXT: sbcs r0, r1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: test_NE_IilEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: movs r1, #0
+; CHECK-T2-NEXT: rsbs r2, r2, #0
+; CHECK-T2-NEXT: sbcs r1, r3
+; CHECK-T2-NEXT: eor.w r1, r1, r0, asr #31
+; CHECK-T2-NEXT: eors r0, r2
+; CHECK-T2-NEXT: orrs r0, r1
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: movne r0, #1
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = sext i32 %a to i64
+ %add = sub i64 0, %b
+ %cmp = icmp ne i64 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @test_NE_IiiEbT(i32 %a, i32 %b) {
+; CHECK-ARM-LABEL: test_NE_IiiEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: rsb r1, r1, #0
+; CHECK-ARM-NEXT: subs r0, r1, r0
+; CHECK-ARM-NEXT: movwne r0, #1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_NE_IiiEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: rsbs r1, r1, #0
+; CHECK-T1-NEXT: subs r0, r1, r0
+; CHECK-T1-NEXT: subs r1, r0, #1
+; CHECK-T1-NEXT: sbcs r0, r1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: test_NE_IiiEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: rsbs r1, r1, #0
+; CHECK-T2-NEXT: subs r0, r1, r0
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: movne r0, #1
+; CHECK-T2-NEXT: bx lr
+entry:
+ %add = sub i32 0, %b
+ %cmp = icmp ne i32 %add, %a
+ ret i1 %cmp
+}
+
+define i1 @test_NE_IisEbT(i32 %a, i16 %b) {
+; CHECK-ARM-LABEL: test_NE_IisEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: rsb r0, r0, #0
+; CHECK-ARM-NEXT: sxth r1, r1
+; CHECK-ARM-NEXT: subs r0, r1, r0
+; CHECK-ARM-NEXT: movwne r0, #1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_NE_IisEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: rsbs r0, r0, #0
+; CHECK-T1-NEXT: lsls r1, r1, #16
+; CHECK-T1-NEXT: asrs r1, r1, #16
+; CHECK-T1-NEXT: subs r0, r0, r1
+; CHECK-T1-NEXT: subs r1, r0, #1
+; CHECK-T1-NEXT: sbcs r0, r1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: test_NE_IisEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: rsbs r0, r0, #0
+; CHECK-T2-NEXT: sxth r1, r1
+; CHECK-T2-NEXT: subs r0, r1, r0
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: movne r0, #1
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = sext i16 %b to i32
+ %add = sub i32 0, %a
+ %cmp = icmp ne i32 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @test_NE_IicEbT(i32 %a, i8 %b) {
+; CHECK-ARM-LABEL: test_NE_IicEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: rsb r0, r0, #0
+; CHECK-ARM-NEXT: uxtb r1, r1
+; CHECK-ARM-NEXT: subs r0, r1, r0
+; CHECK-ARM-NEXT: movwne r0, #1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_NE_IicEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: movs r2, #255
+; CHECK-T1-NEXT: ands r2, r1
+; CHECK-T1-NEXT: rsbs r0, r0, #0
+; CHECK-T1-NEXT: subs r0, r2, r0
+; CHECK-T1-NEXT: subs r1, r0, #1
+; CHECK-T1-NEXT: sbcs r0, r1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: test_NE_IicEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: rsbs r0, r0, #0
+; CHECK-T2-NEXT: uxtb r1, r1
+; CHECK-T2-NEXT: subs r0, r1, r0
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: movne r0, #1
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = zext i8 %b to i32
+ %add = sub i32 0, %a
+ %cmp = icmp ne i32 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @test_NE_IslEbT(i16 %a, i64 %b) {
+; CHECK-ARM-LABEL: test_NE_IslEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: rsbs r1, r2, #0
+; CHECK-ARM-NEXT: sxth r0, r0
+; CHECK-ARM-NEXT: rsc r2, r3, #0
+; CHECK-ARM-NEXT: eor r1, r0, r1
+; CHECK-ARM-NEXT: eor r0, r2, r0, asr #31
+; CHECK-ARM-NEXT: orrs r0, r1, r0
+; CHECK-ARM-NEXT: movwne r0, #1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_NE_IslEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: movs r1, #0
+; CHECK-T1-NEXT: rsbs r2, r2, #0
+; CHECK-T1-NEXT: sbcs r1, r3
+; CHECK-T1-NEXT: lsls r0, r0, #16
+; CHECK-T1-NEXT: asrs r3, r0, #31
+; CHECK-T1-NEXT: eors r3, r1
+; CHECK-T1-NEXT: asrs r0, r0, #16
+; CHECK-T1-NEXT: eors r0, r2
+; CHECK-T1-NEXT: orrs r0, r3
+; CHECK-T1-NEXT: subs r1, r0, #1
+; CHECK-T1-NEXT: sbcs r0, r1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: test_NE_IslEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: movs r1, #0
+; CHECK-T2-NEXT: rsbs r2, r2, #0
+; CHECK-T2-NEXT: sbcs r1, r3
+; CHECK-T2-NEXT: sxth r0, r0
+; CHECK-T2-NEXT: eor.w r1, r1, r0, asr #31
+; CHECK-T2-NEXT: eors r0, r2
+; CHECK-T2-NEXT: orrs r0, r1
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: movne r0, #1
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = sext i16 %a to i64
+ %add = sub i64 0, %b
+ %cmp = icmp ne i64 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @test_NE_IsiEbT(i16 %a, i32 %b) {
+; CHECK-ARM-LABEL: test_NE_IsiEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: rsb r1, r1, #0
+; CHECK-ARM-NEXT: sxth r0, r0
+; CHECK-ARM-NEXT: subs r0, r0, r1
+; CHECK-ARM-NEXT: movwne r0, #1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_NE_IsiEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: rsbs r1, r1, #0
+; CHECK-T1-NEXT: lsls r0, r0, #16
+; CHECK-T1-NEXT: asrs r0, r0, #16
+; CHECK-T1-NEXT: subs r0, r1, r0
+; CHECK-T1-NEXT: subs r1, r0, #1
+; CHECK-T1-NEXT: sbcs r0, r1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: test_NE_IsiEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: rsbs r1, r1, #0
+; CHECK-T2-NEXT: sxth r0, r0
+; CHECK-T2-NEXT: subs r0, r0, r1
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: movne r0, #1
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = sext i16 %a to i32
+ %add = sub i32 0, %b
+ %cmp = icmp ne i32 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @test_NE_IssEbT(i16 %a, i16 %b) {
+; CHECK-ARM-LABEL: test_NE_IssEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: sxth r1, r1
+; CHECK-ARM-NEXT: sxth r0, r0
+; CHECK-ARM-NEXT: rsb r1, r1, #0
+; CHECK-ARM-NEXT: subs r0, r0, r1
+; CHECK-ARM-NEXT: movwne r0, #1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_NE_IssEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: lsls r0, r0, #16
+; CHECK-T1-NEXT: asrs r0, r0, #16
+; CHECK-T1-NEXT: lsls r1, r1, #16
+; CHECK-T1-NEXT: asrs r1, r1, #16
+; CHECK-T1-NEXT: rsbs r1, r1, #0
+; CHECK-T1-NEXT: subs r0, r1, r0
+; CHECK-T1-NEXT: subs r1, r0, #1
+; CHECK-T1-NEXT: sbcs r0, r1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: test_NE_IssEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: sxth r1, r1
+; CHECK-T2-NEXT: sxth r0, r0
+; CHECK-T2-NEXT: rsbs r1, r1, #0
+; CHECK-T2-NEXT: subs r0, r0, r1
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: movne r0, #1
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = sext i16 %a to i32
+ %conv1 = sext i16 %b to i32
+ %add = sub nsw i32 0, %conv1
+ %cmp = icmp ne i32 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @test_NE_IscEbT(i16 %a, i8 %b) {
+; CHECK-ARM-LABEL: test_NE_IscEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: uxtb r1, r1
+; CHECK-ARM-NEXT: sxth r0, r0
+; CHECK-ARM-NEXT: rsb r1, r1, #0
+; CHECK-ARM-NEXT: subs r0, r0, r1
+; CHECK-ARM-NEXT: movwne r0, #1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_NE_IscEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: movs r2, #255
+; CHECK-T1-NEXT: ands r2, r1
+; CHECK-T1-NEXT: rsbs r1, r2, #0
+; CHECK-T1-NEXT: lsls r0, r0, #16
+; CHECK-T1-NEXT: asrs r0, r0, #16
+; CHECK-T1-NEXT: subs r0, r1, r0
+; CHECK-T1-NEXT: subs r1, r0, #1
+; CHECK-T1-NEXT: sbcs r0, r1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: test_NE_IscEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: uxtb r1, r1
+; CHECK-T2-NEXT: sxth r0, r0
+; CHECK-T2-NEXT: rsbs r1, r1, #0
+; CHECK-T2-NEXT: subs r0, r0, r1
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: movne r0, #1
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = sext i16 %a to i32
+ %conv1 = zext i8 %b to i32
+ %add = sub nsw i32 0, %conv1
+ %cmp = icmp ne i32 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @test_NE_IclEbT(i8 %a, i64 %b) {
+; CHECK-ARM-LABEL: test_NE_IclEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: rsbs r1, r2, #0
+; CHECK-ARM-NEXT: uxtb r0, r0
+; CHECK-ARM-NEXT: rsc r2, r3, #0
+; CHECK-ARM-NEXT: eor r0, r0, r1
+; CHECK-ARM-NEXT: orrs r0, r0, r2
+; CHECK-ARM-NEXT: movwne r0, #1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_NE_IclEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: movs r1, #0
+; CHECK-T1-NEXT: rsbs r2, r2, #0
+; CHECK-T1-NEXT: sbcs r1, r3
+; CHECK-T1-NEXT: movs r3, #255
+; CHECK-T1-NEXT: ands r0, r3
+; CHECK-T1-NEXT: eors r0, r2
+; CHECK-T1-NEXT: orrs r0, r1
+; CHECK-T1-NEXT: subs r1, r0, #1
+; CHECK-T1-NEXT: sbcs r0, r1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: test_NE_IclEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: movs r1, #0
+; CHECK-T2-NEXT: rsbs r2, r2, #0
+; CHECK-T2-NEXT: uxtb r0, r0
+; CHECK-T2-NEXT: sbcs r1, r3
+; CHECK-T2-NEXT: eors r0, r2
+; CHECK-T2-NEXT: orrs r0, r1
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: movne r0, #1
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = zext i8 %a to i64
+ %add = sub i64 0, %b
+ %cmp = icmp ne i64 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @test_NE_IciEbT(i8 %a, i32 %b) {
+; CHECK-ARM-LABEL: test_NE_IciEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: rsb r1, r1, #0
+; CHECK-ARM-NEXT: uxtb r0, r0
+; CHECK-ARM-NEXT: subs r0, r0, r1
+; CHECK-ARM-NEXT: movwne r0, #1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_NE_IciEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: movs r2, #255
+; CHECK-T1-NEXT: ands r2, r0
+; CHECK-T1-NEXT: rsbs r0, r1, #0
+; CHECK-T1-NEXT: subs r0, r2, r0
+; CHECK-T1-NEXT: subs r1, r0, #1
+; CHECK-T1-NEXT: sbcs r0, r1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: test_NE_IciEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: rsbs r1, r1, #0
+; CHECK-T2-NEXT: uxtb r0, r0
+; CHECK-T2-NEXT: subs r0, r0, r1
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: movne r0, #1
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = zext i8 %a to i32
+ %add = sub i32 0, %b
+ %cmp = icmp ne i32 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @test_NE_IcsEbT(i8 %a, i16 %b) {
+; CHECK-ARM-LABEL: test_NE_IcsEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: sxth r1, r1
+; CHECK-ARM-NEXT: uxtb r0, r0
+; CHECK-ARM-NEXT: rsb r1, r1, #0
+; CHECK-ARM-NEXT: subs r0, r0, r1
+; CHECK-ARM-NEXT: movwne r0, #1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_NE_IcsEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: movs r2, #255
+; CHECK-T1-NEXT: ands r2, r0
+; CHECK-T1-NEXT: lsls r0, r1, #16
+; CHECK-T1-NEXT: asrs r0, r0, #16
+; CHECK-T1-NEXT: rsbs r0, r0, #0
+; CHECK-T1-NEXT: subs r0, r2, r0
+; CHECK-T1-NEXT: subs r1, r0, #1
+; CHECK-T1-NEXT: sbcs r0, r1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: test_NE_IcsEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: sxth r1, r1
+; CHECK-T2-NEXT: uxtb r0, r0
+; CHECK-T2-NEXT: rsbs r1, r1, #0
+; CHECK-T2-NEXT: subs r0, r0, r1
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: movne r0, #1
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = zext i8 %a to i32
+ %conv1 = sext i16 %b to i32
+ %add = sub nsw i32 0, %conv1
+ %cmp = icmp ne i32 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @test_NE_IccEbT(i8 %a, i8 %b) {
+; CHECK-ARM-LABEL: test_NE_IccEbT:
+; CHECK-ARM: @ %bb.0: @ %entry
+; CHECK-ARM-NEXT: uxtb r1, r1
+; CHECK-ARM-NEXT: uxtb r0, r0
+; CHECK-ARM-NEXT: rsb r1, r1, #0
+; CHECK-ARM-NEXT: subs r0, r0, r1
+; CHECK-ARM-NEXT: movwne r0, #1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: test_NE_IccEbT:
+; CHECK-T1: @ %bb.0: @ %entry
+; CHECK-T1-NEXT: movs r2, #255
+; CHECK-T1-NEXT: ands r0, r2
+; CHECK-T1-NEXT: ands r1, r2
+; CHECK-T1-NEXT: rsbs r1, r1, #0
+; CHECK-T1-NEXT: subs r0, r0, r1
+; CHECK-T1-NEXT: subs r1, r0, #1
+; CHECK-T1-NEXT: sbcs r0, r1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: test_NE_IccEbT:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: uxtb r1, r1
+; CHECK-T2-NEXT: uxtb r0, r0
+; CHECK-T2-NEXT: rsbs r1, r1, #0
+; CHECK-T2-NEXT: subs r0, r0, r1
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: movne r0, #1
+; CHECK-T2-NEXT: bx lr
+entry:
+ %conv = zext i8 %a to i32
+ %conv1 = zext i8 %b to i32
+ %add = sub nsw i32 0, %conv1
+ %cmp = icmp ne i32 %conv, %add
+ ret i1 %cmp
+}
+
+define i1 @cmn_large_imm(i32 %a) {
+; CHECK-ARM-LABEL: cmn_large_imm:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r2, #64765
+; CHECK-ARM-NEXT: mov r1, #0
+; CHECK-ARM-NEXT: movt r2, #64764
+; CHECK-ARM-NEXT: cmp r0, r2
+; CHECK-ARM-NEXT: movwgt r1, #1
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: cmn_large_imm:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: ldr r1, .LCPI32_0
+; CHECK-T1-NEXT: cmp r0, r1
+; CHECK-T1-NEXT: bgt .LBB32_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .LBB32_2:
+; CHECK-T1-NEXT: movs r0, #1
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.3:
+; CHECK-T1-NEXT: .LCPI32_0:
+; CHECK-T1-NEXT: .long 4244438269 @ 0xfcfcfcfd
+;
+; CHECK-T2-LABEL: cmn_large_imm:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: movs r1, #0
+; CHECK-T2-NEXT: cmn.w r0, #50529027
+; CHECK-T2-NEXT: it gt
+; CHECK-T2-NEXT: movgt r1, #1
+; CHECK-T2-NEXT: mov r0, r1
+; CHECK-T2-NEXT: bx lr
+ %cmp = icmp sgt i32 %a, -50529027
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_slt(i32 %x) {
+; CHECK-ARM-LABEL: almost_immediate_neg_slt:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r2, #4097
+; CHECK-ARM-NEXT: mov r1, #0
+; CHECK-ARM-NEXT: movt r2, #65281
+; CHECK-ARM-NEXT: cmp r0, r2
+; CHECK-ARM-NEXT: movwlt r1, #1
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: almost_immediate_neg_slt:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: ldr r1, .LCPI33_0
+; CHECK-T1-NEXT: cmp r0, r1
+; CHECK-T1-NEXT: blt .LBB33_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .LBB33_2:
+; CHECK-T1-NEXT: movs r0, #1
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.3:
+; CHECK-T1-NEXT: .LCPI33_0:
+; CHECK-T1-NEXT: .long 4278259713 @ 0xff011001
+;
+; CHECK-T2-LABEL: almost_immediate_neg_slt:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: movw r2, #4097
+; CHECK-T2-NEXT: movt r2, #65281
+; CHECK-T2-NEXT: movs r1, #0
+; CHECK-T2-NEXT: cmp r0, r2
+; CHECK-T2-NEXT: it lt
+; CHECK-T2-NEXT: movlt r1, #1
+; CHECK-T2-NEXT: mov r0, r1
+; CHECK-T2-NEXT: bx lr
+ %cmp = icmp slt i32 %x, -16707583
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_slt_64(i64 %x) {
+; CHECK-ARM-LABEL: almost_immediate_neg_slt_64:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r3, #4097
+; CHECK-ARM-NEXT: mov r2, #0
+; CHECK-ARM-NEXT: movt r3, #65281
+; CHECK-ARM-NEXT: subs r0, r0, r3
+; CHECK-ARM-NEXT: mvn r12, #0
+; CHECK-ARM-NEXT: sbcs r0, r1, r12
+; CHECK-ARM-NEXT: movwlt r2, #1
+; CHECK-ARM-NEXT: mov r0, r2
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: almost_immediate_neg_slt_64:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: movs r2, r0
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: ldr r3, .LCPI34_0
+; CHECK-T1-NEXT: adds r2, r2, r3
+; CHECK-T1-NEXT: adcs r1, r0
+; CHECK-T1-NEXT: bge .LBB34_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #1
+; CHECK-T1-NEXT: .LBB34_2:
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.3:
+; CHECK-T1-NEXT: .LCPI34_0:
+; CHECK-T1-NEXT: .long 16707583 @ 0xfeefff
+;
+; CHECK-T2-LABEL: almost_immediate_neg_slt_64:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: movw r3, #4097
+; CHECK-T2-NEXT: movt r3, #65281
+; CHECK-T2-NEXT: subs r0, r0, r3
+; CHECK-T2-NEXT: mov.w r2, #0
+; CHECK-T2-NEXT: sbcs r0, r1, #-1
+; CHECK-T2-NEXT: it lt
+; CHECK-T2-NEXT: movlt r2, #1
+; CHECK-T2-NEXT: mov r0, r2
+; CHECK-T2-NEXT: bx lr
+ %cmp = icmp slt i64 %x, -16707583
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_sge(i32 %x) {
+; CHECK-ARM-LABEL: almost_immediate_neg_sge:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r2, #4096
+; CHECK-ARM-NEXT: mov r1, #0
+; CHECK-ARM-NEXT: movt r2, #65281
+; CHECK-ARM-NEXT: cmp r0, r2
+; CHECK-ARM-NEXT: movwgt r1, #1
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: almost_immediate_neg_sge:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: ldr r1, .LCPI35_0
+; CHECK-T1-NEXT: cmp r0, r1
+; CHECK-T1-NEXT: bgt .LBB35_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .LBB35_2:
+; CHECK-T1-NEXT: movs r0, #1
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.3:
+; CHECK-T1-NEXT: .LCPI35_0:
+; CHECK-T1-NEXT: .long 4278259712 @ 0xff011000
+;
+; CHECK-T2-LABEL: almost_immediate_neg_sge:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: movw r2, #4096
+; CHECK-T2-NEXT: movt r2, #65281
+; CHECK-T2-NEXT: movs r1, #0
+; CHECK-T2-NEXT: cmp r0, r2
+; CHECK-T2-NEXT: it gt
+; CHECK-T2-NEXT: movgt r1, #1
+; CHECK-T2-NEXT: mov r0, r1
+; CHECK-T2-NEXT: bx lr
+ %cmp = icmp sge i32 %x, -16707583
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_sge_64(i64 %x) {
+; CHECK-ARM-LABEL: almost_immediate_neg_sge_64:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r3, #4096
+; CHECK-ARM-NEXT: mov r2, #0
+; CHECK-ARM-NEXT: movt r3, #65281
+; CHECK-ARM-NEXT: subs r0, r3, r0
+; CHECK-ARM-NEXT: mvn r12, #0
+; CHECK-ARM-NEXT: sbcs r0, r12, r1
+; CHECK-ARM-NEXT: movwlt r2, #1
+; CHECK-ARM-NEXT: mov r0, r2
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: almost_immediate_neg_sge_64:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: .save {r4, lr}
+; CHECK-T1-NEXT: push {r4, lr}
+; CHECK-T1-NEXT: movs r2, r0
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: mvns r3, r0
+; CHECK-T1-NEXT: ldr r4, .LCPI36_0
+; CHECK-T1-NEXT: subs r2, r4, r2
+; CHECK-T1-NEXT: sbcs r3, r1
+; CHECK-T1-NEXT: bge .LBB36_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #1
+; CHECK-T1-NEXT: .LBB36_2:
+; CHECK-T1-NEXT: pop {r4}
+; CHECK-T1-NEXT: pop {r1}
+; CHECK-T1-NEXT: bx r1
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.3:
+; CHECK-T1-NEXT: .LCPI36_0:
+; CHECK-T1-NEXT: .long 4278259712 @ 0xff011000
+;
+; CHECK-T2-LABEL: almost_immediate_neg_sge_64:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: movw r3, #4096
+; CHECK-T2-NEXT: movt r3, #65281
+; CHECK-T2-NEXT: mov.w r12, #-1
+; CHECK-T2-NEXT: subs r0, r3, r0
+; CHECK-T2-NEXT: mov.w r2, #0
+; CHECK-T2-NEXT: sbcs.w r0, r12, r1
+; CHECK-T2-NEXT: it lt
+; CHECK-T2-NEXT: movlt r2, #1
+; CHECK-T2-NEXT: mov r0, r2
+; CHECK-T2-NEXT: bx lr
+ %cmp = icmp sge i64 %x, -16707583
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_uge(i32 %x) {
+; CHECK-ARM-LABEL: almost_immediate_neg_uge:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r2, #4096
+; CHECK-ARM-NEXT: mov r1, #0
+; CHECK-ARM-NEXT: movt r2, #65281
+; CHECK-ARM-NEXT: cmp r0, r2
+; CHECK-ARM-NEXT: movwhi r1, #1
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: almost_immediate_neg_uge:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: ldr r1, .LCPI37_0
+; CHECK-T1-NEXT: cmp r0, r1
+; CHECK-T1-NEXT: bhi .LBB37_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .LBB37_2:
+; CHECK-T1-NEXT: movs r0, #1
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.3:
+; CHECK-T1-NEXT: .LCPI37_0:
+; CHECK-T1-NEXT: .long 4278259712 @ 0xff011000
+;
+; CHECK-T2-LABEL: almost_immediate_neg_uge:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: movw r2, #4096
+; CHECK-T2-NEXT: movt r2, #65281
+; CHECK-T2-NEXT: movs r1, #0
+; CHECK-T2-NEXT: cmp r0, r2
+; CHECK-T2-NEXT: it hi
+; CHECK-T2-NEXT: movhi r1, #1
+; CHECK-T2-NEXT: mov r0, r1
+; CHECK-T2-NEXT: bx lr
+ %cmp = icmp uge i32 %x, -16707583
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_uge_64(i64 %x) {
+; CHECK-ARM-LABEL: almost_immediate_neg_uge_64:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r3, #4096
+; CHECK-ARM-NEXT: mov r2, #0
+; CHECK-ARM-NEXT: movt r3, #65281
+; CHECK-ARM-NEXT: subs r0, r3, r0
+; CHECK-ARM-NEXT: mvn r12, #0
+; CHECK-ARM-NEXT: sbcs r0, r12, r1
+; CHECK-ARM-NEXT: movwlo r2, #1
+; CHECK-ARM-NEXT: mov r0, r2
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: almost_immediate_neg_uge_64:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: .save {r4, lr}
+; CHECK-T1-NEXT: push {r4, lr}
+; CHECK-T1-NEXT: movs r2, r0
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: mvns r3, r0
+; CHECK-T1-NEXT: ldr r4, .LCPI38_0
+; CHECK-T1-NEXT: subs r2, r4, r2
+; CHECK-T1-NEXT: sbcs r3, r1
+; CHECK-T1-NEXT: bhs .LBB38_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #1
+; CHECK-T1-NEXT: .LBB38_2:
+; CHECK-T1-NEXT: pop {r4}
+; CHECK-T1-NEXT: pop {r1}
+; CHECK-T1-NEXT: bx r1
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.3:
+; CHECK-T1-NEXT: .LCPI38_0:
+; CHECK-T1-NEXT: .long 4278259712 @ 0xff011000
+;
+; CHECK-T2-LABEL: almost_immediate_neg_uge_64:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: movw r3, #4096
+; CHECK-T2-NEXT: movt r3, #65281
+; CHECK-T2-NEXT: mov.w r12, #-1
+; CHECK-T2-NEXT: subs r0, r3, r0
+; CHECK-T2-NEXT: mov.w r2, #0
+; CHECK-T2-NEXT: sbcs.w r0, r12, r1
+; CHECK-T2-NEXT: it lo
+; CHECK-T2-NEXT: movlo r2, #1
+; CHECK-T2-NEXT: mov r0, r2
+; CHECK-T2-NEXT: bx lr
+ %cmp = icmp uge i64 %x, -16707583
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_ult(i32 %x) {
+; CHECK-ARM-LABEL: almost_immediate_neg_ult:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r2, #4097
+; CHECK-ARM-NEXT: mov r1, #0
+; CHECK-ARM-NEXT: movt r2, #65281
+; CHECK-ARM-NEXT: cmp r0, r2
+; CHECK-ARM-NEXT: movwlo r1, #1
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: almost_immediate_neg_ult:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: ldr r1, .LCPI39_0
+; CHECK-T1-NEXT: cmp r0, r1
+; CHECK-T1-NEXT: blo .LBB39_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .LBB39_2:
+; CHECK-T1-NEXT: movs r0, #1
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.3:
+; CHECK-T1-NEXT: .LCPI39_0:
+; CHECK-T1-NEXT: .long 4278259713 @ 0xff011001
+;
+; CHECK-T2-LABEL: almost_immediate_neg_ult:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: movw r2, #4097
+; CHECK-T2-NEXT: movt r2, #65281
+; CHECK-T2-NEXT: movs r1, #0
+; CHECK-T2-NEXT: cmp r0, r2
+; CHECK-T2-NEXT: it lo
+; CHECK-T2-NEXT: movlo r1, #1
+; CHECK-T2-NEXT: mov r0, r1
+; CHECK-T2-NEXT: bx lr
+ %cmp = icmp ult i32 %x, -16707583
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_ult_64(i64 %x) {
+; CHECK-ARM-LABEL: almost_immediate_neg_ult_64:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r3, #4097
+; CHECK-ARM-NEXT: mov r2, #0
+; CHECK-ARM-NEXT: movt r3, #65281
+; CHECK-ARM-NEXT: subs r0, r0, r3
+; CHECK-ARM-NEXT: mvn r12, #0
+; CHECK-ARM-NEXT: sbcs r0, r1, r12
+; CHECK-ARM-NEXT: movwlo r2, #1
+; CHECK-ARM-NEXT: mov r0, r2
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: almost_immediate_neg_ult_64:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: movs r2, r0
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: ldr r3, .LCPI40_0
+; CHECK-T1-NEXT: adds r2, r2, r3
+; CHECK-T1-NEXT: adcs r1, r0
+; CHECK-T1-NEXT: bhs .LBB40_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #1
+; CHECK-T1-NEXT: .LBB40_2:
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.3:
+; CHECK-T1-NEXT: .LCPI40_0:
+; CHECK-T1-NEXT: .long 16707583 @ 0xfeefff
+;
+; CHECK-T2-LABEL: almost_immediate_neg_ult_64:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: movw r3, #4097
+; CHECK-T2-NEXT: movt r3, #65281
+; CHECK-T2-NEXT: subs r0, r0, r3
+; CHECK-T2-NEXT: mov.w r2, #0
+; CHECK-T2-NEXT: sbcs r0, r1, #-1
+; CHECK-T2-NEXT: it lo
+; CHECK-T2-NEXT: movlo r2, #1
+; CHECK-T2-NEXT: mov r0, r2
+; CHECK-T2-NEXT: bx lr
+ %cmp = icmp ult i64 %x, -16707583
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_sle(i32 %x) {
+; CHECK-ARM-LABEL: almost_immediate_neg_sle:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r2, #4096
+; CHECK-ARM-NEXT: mov r1, #0
+; CHECK-ARM-NEXT: movt r2, #65280
+; CHECK-ARM-NEXT: cmp r0, r2
+; CHECK-ARM-NEXT: movwlt r1, #1
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: almost_immediate_neg_sle:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: ldr r1, .LCPI41_0
+; CHECK-T1-NEXT: cmp r0, r1
+; CHECK-T1-NEXT: blt .LBB41_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .LBB41_2:
+; CHECK-T1-NEXT: movs r0, #1
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.3:
+; CHECK-T1-NEXT: .LCPI41_0:
+; CHECK-T1-NEXT: .long 4278194176 @ 0xff001000
+;
+; CHECK-T2-LABEL: almost_immediate_neg_sle:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: movw r2, #4096
+; CHECK-T2-NEXT: movt r2, #65280
+; CHECK-T2-NEXT: movs r1, #0
+; CHECK-T2-NEXT: cmp r0, r2
+; CHECK-T2-NEXT: it lt
+; CHECK-T2-NEXT: movlt r1, #1
+; CHECK-T2-NEXT: mov r0, r1
+; CHECK-T2-NEXT: bx lr
+ %cmp = icmp sle i32 %x, -16773121
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_sle_64(i64 %x) {
+; CHECK-ARM-LABEL: almost_immediate_neg_sle_64:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r3, #4096
+; CHECK-ARM-NEXT: mov r2, #0
+; CHECK-ARM-NEXT: movt r3, #65280
+; CHECK-ARM-NEXT: subs r0, r0, r3
+; CHECK-ARM-NEXT: mvn r12, #0
+; CHECK-ARM-NEXT: sbcs r0, r1, r12
+; CHECK-ARM-NEXT: movwlt r2, #1
+; CHECK-ARM-NEXT: mov r0, r2
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: almost_immediate_neg_sle_64:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: movs r2, r0
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: ldr r3, .LCPI42_0
+; CHECK-T1-NEXT: adds r2, r2, r3
+; CHECK-T1-NEXT: adcs r1, r0
+; CHECK-T1-NEXT: bge .LBB42_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #1
+; CHECK-T1-NEXT: .LBB42_2:
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.3:
+; CHECK-T1-NEXT: .LCPI42_0:
+; CHECK-T1-NEXT: .long 16773120 @ 0xfff000
+;
+; CHECK-T2-LABEL: almost_immediate_neg_sle_64:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: movw r3, #4096
+; CHECK-T2-NEXT: movt r3, #65280
+; CHECK-T2-NEXT: subs r0, r0, r3
+; CHECK-T2-NEXT: mov.w r2, #0
+; CHECK-T2-NEXT: sbcs r0, r1, #-1
+; CHECK-T2-NEXT: it lt
+; CHECK-T2-NEXT: movlt r2, #1
+; CHECK-T2-NEXT: mov r0, r2
+; CHECK-T2-NEXT: bx lr
+ %cmp = icmp sle i64 %x, -16773121
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_sgt(i32 %x) {
+; CHECK-ARM-LABEL: almost_immediate_neg_sgt:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r2, #4095
+; CHECK-ARM-NEXT: mov r1, #0
+; CHECK-ARM-NEXT: movt r2, #65280
+; CHECK-ARM-NEXT: cmp r0, r2
+; CHECK-ARM-NEXT: movwgt r1, #1
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: almost_immediate_neg_sgt:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: ldr r1, .LCPI43_0
+; CHECK-T1-NEXT: cmp r0, r1
+; CHECK-T1-NEXT: bgt .LBB43_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .LBB43_2:
+; CHECK-T1-NEXT: movs r0, #1
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.3:
+; CHECK-T1-NEXT: .LCPI43_0:
+; CHECK-T1-NEXT: .long 4278194175 @ 0xff000fff
+;
+; CHECK-T2-LABEL: almost_immediate_neg_sgt:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: movw r2, #4095
+; CHECK-T2-NEXT: movt r2, #65280
+; CHECK-T2-NEXT: movs r1, #0
+; CHECK-T2-NEXT: cmp r0, r2
+; CHECK-T2-NEXT: it gt
+; CHECK-T2-NEXT: movgt r1, #1
+; CHECK-T2-NEXT: mov r0, r1
+; CHECK-T2-NEXT: bx lr
+ %cmp = icmp sgt i32 %x, -16773121
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_sgt_64(i64 %x) {
+; CHECK-ARM-LABEL: almost_immediate_neg_sgt_64:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r3, #4095
+; CHECK-ARM-NEXT: mov r2, #0
+; CHECK-ARM-NEXT: movt r3, #65280
+; CHECK-ARM-NEXT: subs r0, r3, r0
+; CHECK-ARM-NEXT: mvn r12, #0
+; CHECK-ARM-NEXT: sbcs r0, r12, r1
+; CHECK-ARM-NEXT: movwlt r2, #1
+; CHECK-ARM-NEXT: mov r0, r2
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: almost_immediate_neg_sgt_64:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: .save {r4, lr}
+; CHECK-T1-NEXT: push {r4, lr}
+; CHECK-T1-NEXT: movs r2, r0
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: mvns r3, r0
+; CHECK-T1-NEXT: ldr r4, .LCPI44_0
+; CHECK-T1-NEXT: subs r2, r4, r2
+; CHECK-T1-NEXT: sbcs r3, r1
+; CHECK-T1-NEXT: bge .LBB44_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #1
+; CHECK-T1-NEXT: .LBB44_2:
+; CHECK-T1-NEXT: pop {r4}
+; CHECK-T1-NEXT: pop {r1}
+; CHECK-T1-NEXT: bx r1
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.3:
+; CHECK-T1-NEXT: .LCPI44_0:
+; CHECK-T1-NEXT: .long 4278194175 @ 0xff000fff
+;
+; CHECK-T2-LABEL: almost_immediate_neg_sgt_64:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: movw r3, #4095
+; CHECK-T2-NEXT: movt r3, #65280
+; CHECK-T2-NEXT: mov.w r12, #-1
+; CHECK-T2-NEXT: subs r0, r3, r0
+; CHECK-T2-NEXT: mov.w r2, #0
+; CHECK-T2-NEXT: sbcs.w r0, r12, r1
+; CHECK-T2-NEXT: it lt
+; CHECK-T2-NEXT: movlt r2, #1
+; CHECK-T2-NEXT: mov r0, r2
+; CHECK-T2-NEXT: bx lr
+ %cmp = icmp sgt i64 %x, -16773121
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_ule(i32 %x) {
+; CHECK-ARM-LABEL: almost_immediate_neg_ule:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r2, #4096
+; CHECK-ARM-NEXT: mov r1, #0
+; CHECK-ARM-NEXT: movt r2, #65280
+; CHECK-ARM-NEXT: cmp r0, r2
+; CHECK-ARM-NEXT: movwlo r1, #1
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: almost_immediate_neg_ule:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: ldr r1, .LCPI45_0
+; CHECK-T1-NEXT: cmp r0, r1
+; CHECK-T1-NEXT: blo .LBB45_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .LBB45_2:
+; CHECK-T1-NEXT: movs r0, #1
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.3:
+; CHECK-T1-NEXT: .LCPI45_0:
+; CHECK-T1-NEXT: .long 4278194176 @ 0xff001000
+;
+; CHECK-T2-LABEL: almost_immediate_neg_ule:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: movw r2, #4096
+; CHECK-T2-NEXT: movt r2, #65280
+; CHECK-T2-NEXT: movs r1, #0
+; CHECK-T2-NEXT: cmp r0, r2
+; CHECK-T2-NEXT: it lo
+; CHECK-T2-NEXT: movlo r1, #1
+; CHECK-T2-NEXT: mov r0, r1
+; CHECK-T2-NEXT: bx lr
+ %cmp = icmp ule i32 %x, -16773121
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_ule_64(i64 %x) {
+; CHECK-ARM-LABEL: almost_immediate_neg_ule_64:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r3, #4096
+; CHECK-ARM-NEXT: mov r2, #0
+; CHECK-ARM-NEXT: movt r3, #65280
+; CHECK-ARM-NEXT: subs r0, r0, r3
+; CHECK-ARM-NEXT: mvn r12, #0
+; CHECK-ARM-NEXT: sbcs r0, r1, r12
+; CHECK-ARM-NEXT: movwlo r2, #1
+; CHECK-ARM-NEXT: mov r0, r2
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: almost_immediate_neg_ule_64:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: movs r2, r0
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: ldr r3, .LCPI46_0
+; CHECK-T1-NEXT: adds r2, r2, r3
+; CHECK-T1-NEXT: adcs r1, r0
+; CHECK-T1-NEXT: bhs .LBB46_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #1
+; CHECK-T1-NEXT: .LBB46_2:
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.3:
+; CHECK-T1-NEXT: .LCPI46_0:
+; CHECK-T1-NEXT: .long 16773120 @ 0xfff000
+;
+; CHECK-T2-LABEL: almost_immediate_neg_ule_64:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: movw r3, #4096
+; CHECK-T2-NEXT: movt r3, #65280
+; CHECK-T2-NEXT: subs r0, r0, r3
+; CHECK-T2-NEXT: mov.w r2, #0
+; CHECK-T2-NEXT: sbcs r0, r1, #-1
+; CHECK-T2-NEXT: it lo
+; CHECK-T2-NEXT: movlo r2, #1
+; CHECK-T2-NEXT: mov r0, r2
+; CHECK-T2-NEXT: bx lr
+ %cmp = icmp ule i64 %x, -16773121
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_ugt(i32 %x) {
+; CHECK-ARM-LABEL: almost_immediate_neg_ugt:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r2, #4095
+; CHECK-ARM-NEXT: mov r1, #0
+; CHECK-ARM-NEXT: movt r2, #65280
+; CHECK-ARM-NEXT: cmp r0, r2
+; CHECK-ARM-NEXT: movwhi r1, #1
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: almost_immediate_neg_ugt:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: ldr r1, .LCPI47_0
+; CHECK-T1-NEXT: cmp r0, r1
+; CHECK-T1-NEXT: bhi .LBB47_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .LBB47_2:
+; CHECK-T1-NEXT: movs r0, #1
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.3:
+; CHECK-T1-NEXT: .LCPI47_0:
+; CHECK-T1-NEXT: .long 4278194175 @ 0xff000fff
+;
+; CHECK-T2-LABEL: almost_immediate_neg_ugt:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: movw r2, #4095
+; CHECK-T2-NEXT: movt r2, #65280
+; CHECK-T2-NEXT: movs r1, #0
+; CHECK-T2-NEXT: cmp r0, r2
+; CHECK-T2-NEXT: it hi
+; CHECK-T2-NEXT: movhi r1, #1
+; CHECK-T2-NEXT: mov r0, r1
+; CHECK-T2-NEXT: bx lr
+ %cmp = icmp ugt i32 %x, -16773121
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_ugt_64(i64 %x) {
+; CHECK-ARM-LABEL: almost_immediate_neg_ugt_64:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r3, #4095
+; CHECK-ARM-NEXT: mov r2, #0
+; CHECK-ARM-NEXT: movt r3, #65280
+; CHECK-ARM-NEXT: subs r0, r3, r0
+; CHECK-ARM-NEXT: mvn r12, #0
+; CHECK-ARM-NEXT: sbcs r0, r12, r1
+; CHECK-ARM-NEXT: movwlo r2, #1
+; CHECK-ARM-NEXT: mov r0, r2
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: almost_immediate_neg_ugt_64:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: .save {r4, lr}
+; CHECK-T1-NEXT: push {r4, lr}
+; CHECK-T1-NEXT: movs r2, r0
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: mvns r3, r0
+; CHECK-T1-NEXT: ldr r4, .LCPI48_0
+; CHECK-T1-NEXT: subs r2, r4, r2
+; CHECK-T1-NEXT: sbcs r3, r1
+; CHECK-T1-NEXT: bhs .LBB48_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #1
+; CHECK-T1-NEXT: .LBB48_2:
+; CHECK-T1-NEXT: pop {r4}
+; CHECK-T1-NEXT: pop {r1}
+; CHECK-T1-NEXT: bx r1
+; CHECK-T1-NEXT: .p2align 2
+; CHECK-T1-NEXT: @ %bb.3:
+; CHECK-T1-NEXT: .LCPI48_0:
+; CHECK-T1-NEXT: .long 4278194175 @ 0xff000fff
+;
+; CHECK-T2-LABEL: almost_immediate_neg_ugt_64:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: movw r3, #4095
+; CHECK-T2-NEXT: movt r3, #65280
+; CHECK-T2-NEXT: mov.w r12, #-1
+; CHECK-T2-NEXT: subs r0, r3, r0
+; CHECK-T2-NEXT: mov.w r2, #0
+; CHECK-T2-NEXT: sbcs.w r0, r12, r1
+; CHECK-T2-NEXT: it lo
+; CHECK-T2-NEXT: movlo r2, #1
+; CHECK-T2-NEXT: mov r0, r2
+; CHECK-T2-NEXT: bx lr
+ %cmp = icmp ugt i64 %x, -16773121
+ ret i1 %cmp
+}
+
+define i1 @cmn_nsw(i32 %a, i32 %b) {
+; CHECK-ARM-LABEL: cmn_nsw:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: rsb r2, r1, #0
+; CHECK-ARM-NEXT: mov r1, #0
+; CHECK-ARM-NEXT: cmp r0, r2
+; CHECK-ARM-NEXT: movwgt r1, #1
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: cmn_nsw:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: rsbs r1, r1, #0
+; CHECK-T1-NEXT: cmp r0, r1
+; CHECK-T1-NEXT: bgt .LBB49_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .LBB49_2:
+; CHECK-T1-NEXT: movs r0, #1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: cmn_nsw:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: rsbs r2, r1, #0
+; CHECK-T2-NEXT: movs r1, #0
+; CHECK-T2-NEXT: cmp r0, r2
+; CHECK-T2-NEXT: it gt
+; CHECK-T2-NEXT: movgt r1, #1
+; CHECK-T2-NEXT: mov r0, r1
+; CHECK-T2-NEXT: bx lr
+ %sub = sub nsw i32 0, %b
+ %cmp = icmp sgt i32 %a, %sub
+ ret i1 %cmp
+}
+
+define i1 @cmn_nsw_64(i64 %a, i64 %b) {
+; CHECK-ARM-LABEL: cmn_nsw_64:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: rsbs r12, r2, #0
+; CHECK-ARM-NEXT: mov r2, #0
+; CHECK-ARM-NEXT: rsc r3, r3, #0
+; CHECK-ARM-NEXT: subs r0, r12, r0
+; CHECK-ARM-NEXT: sbcs r0, r3, r1
+; CHECK-ARM-NEXT: movwlt r2, #1
+; CHECK-ARM-NEXT: mov r0, r2
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: cmn_nsw_64:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: .save {r4, r5, r7, lr}
+; CHECK-T1-NEXT: push {r4, r5, r7, lr}
+; CHECK-T1-NEXT: movs r4, r0
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: rsbs r2, r2, #0
+; CHECK-T1-NEXT: mov r12, r0
+; CHECK-T1-NEXT: mov r5, r12
+; CHECK-T1-NEXT: sbcs r5, r3
+; CHECK-T1-NEXT: subs r2, r2, r4
+; CHECK-T1-NEXT: sbcs r5, r1
+; CHECK-T1-NEXT: bge .LBB50_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #1
+; CHECK-T1-NEXT: .LBB50_2:
+; CHECK-T1-NEXT: pop {r4, r5, r7}
+; CHECK-T1-NEXT: pop {r1}
+; CHECK-T1-NEXT: bx r1
+;
+; CHECK-T2-LABEL: cmn_nsw_64:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: mov.w r12, #0
+; CHECK-T2-NEXT: rsbs r2, r2, #0
+; CHECK-T2-NEXT: sbc.w r3, r12, r3
+; CHECK-T2-NEXT: subs r0, r2, r0
+; CHECK-T2-NEXT: sbcs.w r0, r3, r1
+; CHECK-T2-NEXT: it lt
+; CHECK-T2-NEXT: movlt.w r12, #1
+; CHECK-T2-NEXT: mov r0, r12
+; CHECK-T2-NEXT: bx lr
+ %sub = sub nsw i64 0, %b
+ %cmp = icmp sgt i64 %a, %sub
+ ret i1 %cmp
+}
+
+define i1 @cmn_nsw_neg(i32 %a, i32 %b) {
+; CHECK-ARM-LABEL: cmn_nsw_neg:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: rsb r2, r1, #0
+; CHECK-ARM-NEXT: mov r1, #0
+; CHECK-ARM-NEXT: cmp r0, r2
+; CHECK-ARM-NEXT: movwgt r1, #1
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: cmn_nsw_neg:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: rsbs r1, r1, #0
+; CHECK-T1-NEXT: cmp r0, r1
+; CHECK-T1-NEXT: bgt .LBB51_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .LBB51_2:
+; CHECK-T1-NEXT: movs r0, #1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: cmn_nsw_neg:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: rsbs r2, r1, #0
+; CHECK-T2-NEXT: movs r1, #0
+; CHECK-T2-NEXT: cmp r0, r2
+; CHECK-T2-NEXT: it gt
+; CHECK-T2-NEXT: movgt r1, #1
+; CHECK-T2-NEXT: mov r0, r1
+; CHECK-T2-NEXT: bx lr
+ %sub = sub i32 0, %b
+ %cmp = icmp sgt i32 %a, %sub
+ ret i1 %cmp
+}
+
+define i1 @cmn_swap(i32 %a, i32 %b) {
+; CHECK-ARM-LABEL: cmn_swap:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: rsb r2, r1, #0
+; CHECK-ARM-NEXT: mov r1, #0
+; CHECK-ARM-NEXT: cmp r2, r0
+; CHECK-ARM-NEXT: movwgt r1, #1
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: cmn_swap:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: rsbs r1, r1, #0
+; CHECK-T1-NEXT: cmp r1, r0
+; CHECK-T1-NEXT: bgt .LBB52_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: bx lr
+; CHECK-T1-NEXT: .LBB52_2:
+; CHECK-T1-NEXT: movs r0, #1
+; CHECK-T1-NEXT: bx lr
+;
+; CHECK-T2-LABEL: cmn_swap:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: rsbs r2, r1, #0
+; CHECK-T2-NEXT: movs r1, #0
+; CHECK-T2-NEXT: cmp r2, r0
+; CHECK-T2-NEXT: it gt
+; CHECK-T2-NEXT: movgt r1, #1
+; CHECK-T2-NEXT: mov r0, r1
+; CHECK-T2-NEXT: bx lr
+ %sub = sub nsw i32 0, %b
+ %cmp = icmp sgt i32 %sub, %a
+ ret i1 %cmp
+}
+
+
+define i1 @cmn_nsw_neg_64(i64 %a, i64 %b) {
+; CHECK-ARM-LABEL: cmn_nsw_neg_64:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: rsbs r12, r2, #0
+; CHECK-ARM-NEXT: mov r2, #0
+; CHECK-ARM-NEXT: rsc r3, r3, #0
+; CHECK-ARM-NEXT: subs r0, r12, r0
+; CHECK-ARM-NEXT: sbcs r0, r3, r1
+; CHECK-ARM-NEXT: movwlt r2, #1
+; CHECK-ARM-NEXT: mov r0, r2
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-T1-LABEL: cmn_nsw_neg_64:
+; CHECK-T1: @ %bb.0:
+; CHECK-T1-NEXT: .save {r4, r5, r7, lr}
+; CHECK-T1-NEXT: push {r4, r5, r7, lr}
+; CHECK-T1-NEXT: movs r4, r0
+; CHECK-T1-NEXT: movs r0, #0
+; CHECK-T1-NEXT: rsbs r2, r2, #0
+; CHECK-T1-NEXT: mov r12, r0
+; CHECK-T1-NEXT: mov r5, r12
+; CHECK-T1-NEXT: sbcs r5, r3
+; CHECK-T1-NEXT: subs r2, r2, r4
+; CHECK-T1-NEXT: sbcs r5, r1
+; CHECK-T1-NEXT: bge .LBB53_2
+; CHECK-T1-NEXT: @ %bb.1:
+; CHECK-T1-NEXT: movs r0, #1
+; CHECK-T1-NEXT: .LBB53_2:
+; CHECK-T1-NEXT: pop {r4, r5, r7}
+; CHECK-T1-NEXT: pop {r1}
+; CHECK-T1-NEXT: bx r1
+;
+; CHECK-T2-LABEL: cmn_nsw_neg_64:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: mov.w r12, #0
+; CHECK-T2-NEXT: rsbs r2, r2, #0
+; CHECK-T2-NEXT: sbc.w r3, r12, r3
+; CHECK-T2-NEXT: subs r0, r2, r0
+; CHECK-T2-NEXT: sbcs.w r0, r3, r1
+; CHECK-T2-NEXT: it lt
+; CHECK-T2-NEXT: movlt.w r12, #1
+; CHECK-T2-NEXT: mov r0, r12
+; CHECK-T2-NEXT: bx lr
+ %sub = sub i64 0, %b
+ %cmp = icmp sgt i64 %a, %sub
+ ret i1 %cmp
+}
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