[llvm] [WebAssembly] Fix operand order in performBitcastCombine for wide <N … (PR #190361)

[Zile Xiong via llvm-commits]

https://github.com/xiongzile created https://github.com/llvm/llvm-project/pull/190361

Fix operand order in performBitcastCombine for wide <N x i1> -> iN bitmask reconstruction.

In performBitcastCombine, when reconstructing i32/i64 bitmask from multiple v16i1 SetCC results (for N=32 and N=64 cases), the code incorrectly built SHL nodes with reversed operands:

SHL(16, ReturningInteger)  // wrong

SelectionDAG::getNode(ISD::SHL, ...) expects operand 0 to be the value to shift and operand 1 to be the shift amount.

This produced incorrect DAGs like shl Constant<16>, xxx, leading to wrong codegen for vector bitmask patterns.

Fixed by swapping the operands:

SHL(ReturningInteger, 16)

Fixes https://github.com/llvm/llvm-project/issues/190358

>From aff0beb84c8a74b46d70a0223758ae4583aef60b Mon Sep 17 00:00:00 2001
From: Zile Xiong <xiongzile99 at gmail.com>
Date: Sat, 4 Apr 2026 00:36:51 +0800
Subject: [PATCH] [WebAssembly] Fix operand order in performBitcastCombine for
 wide <N x i1> -> iN bitmask reconstruction

In performBitcastCombine, when reconstructing i32/i64 bitmask from
multiple v16i1 SetCC results (for N=32 and N=64 cases), the code was
building SHL nodes with reversed operands:

    SHL(16, ReturningInteger)   // wrong

SelectionDAG::getNode(ISD::SHL, ...) expects:
- operand 0: value to be shifted
- operand 1: shift amount

This produced incorrect DAGs such as `shl Constant<16>, xxx`, leading
to wrong codegen for vector bitmask patterns.

Fixed by swapping the operands to the correct order:
    SHL(ReturningInteger, 16)

Fixes: https://github.com/llvm/llvm-project/issues/190358
---
 llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index 47de46a6f7070..9e2ebe9a47761 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -3360,7 +3360,7 @@ static SDValue performBitcastCombine(SDNode *N,
     for (SDValue V : VectorsToShuffle) {
       ReturningInteger = DAG.getNode(
           ISD::SHL, DL, ReturnType,
-          {DAG.getShiftAmountConstant(16, ReturnType, DL), ReturningInteger});
+          {ReturningInteger, DAG.getShiftAmountConstant(16, ReturnType, DL)});
 
       SDValue ExtendedV = DAG.getZExtOrTrunc(V, DL, ReturnType);
       ReturningInteger =