[llvm] 62bbe3f - Fix buildbot failure by explicitly disabling partial reductions in TTI. (#190165)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 3 08:33:45 PDT 2026
Author: Sander de Smalen
Date: 2026-04-03T16:33:39+01:00
New Revision: 62bbe3fffc16d77a07cfbbb9333ef19fd01b135b
URL: https://github.com/llvm/llvm-project/commit/62bbe3fffc16d77a07cfbbb9333ef19fd01b135b
DIFF: https://github.com/llvm/llvm-project/commit/62bbe3fffc16d77a07cfbbb9333ef19fd01b135b.diff
LOG: Fix buildbot failure by explicitly disabling partial reductions in TTI. (#190165)
Partial reductions were previously disabled by default, but by
implementing a generic cost-model in BasicTTIImpl (#189905) this now
accidentally enables the use of those when vectorising loops for targets
that may not support this yet.
Added:
Modified:
llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h
llvm/lib/Target/DirectX/DirectXTargetTransformInfo.h
llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h
llvm/lib/Target/Mips/MipsTargetTransformInfo.h
llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
llvm/lib/Target/SPIRV/SPIRVTargetTransformInfo.h
llvm/lib/Target/Sparc/SparcTargetTransformInfo.h
llvm/lib/Target/VE/VETargetTransformInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h b/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h
index 9f8046391ebaf..f51c0963512c9 100644
--- a/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h
+++ b/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h
@@ -66,6 +66,15 @@ class R600TTIImpl final : public BasicTTIImplBase<R600TTIImpl> {
unsigned Index, const Value *Op0, const Value *Op1,
TTI::VectorInstrContext VIC =
TTI::VectorInstrContext::None) const override;
+
+ InstructionCost getPartialReductionCost(
+ unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
+ ElementCount VF, TTI::PartialReductionExtendKind OpAExtend,
+ TTI::PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
+ TTI::TargetCostKind CostKind,
+ std::optional<FastMathFlags> FMF) const override {
+ return InstructionCost::getInvalid();
+ }
};
} // end namespace llvm
diff --git a/llvm/lib/Target/DirectX/DirectXTargetTransformInfo.h b/llvm/lib/Target/DirectX/DirectXTargetTransformInfo.h
index e2dd4354a8167..4f914f53e2ed7 100644
--- a/llvm/lib/Target/DirectX/DirectXTargetTransformInfo.h
+++ b/llvm/lib/Target/DirectX/DirectXTargetTransformInfo.h
@@ -39,6 +39,15 @@ class DirectXTTIImpl final : public BasicTTIImplBase<DirectXTTIImpl> {
unsigned ScalarOpdIdx) const override;
bool isTargetIntrinsicWithOverloadTypeAtArg(Intrinsic::ID ID,
int OpdIdx) const override;
+
+ InstructionCost getPartialReductionCost(
+ unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
+ ElementCount VF, TTI::PartialReductionExtendKind OpAExtend,
+ TTI::PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
+ TTI::TargetCostKind CostKind,
+ std::optional<FastMathFlags> FMF) const override {
+ return InstructionCost::getInvalid();
+ }
};
} // namespace llvm
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
index 25e1b5b5f6455..86b3195222bdb 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
+++ b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
@@ -169,6 +169,15 @@ class HexagonTTIImpl final : public BasicTTIImplBase<HexagonTTIImpl> {
bool forceScalarizeMaskedScatter(VectorType *VTy,
Align Alignment) const override;
+ InstructionCost getPartialReductionCost(
+ unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
+ ElementCount VF, TTI::PartialReductionExtendKind OpAExtend,
+ TTI::PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
+ TTI::TargetCostKind CostKind,
+ std::optional<FastMathFlags> FMF) const override {
+ return InstructionCost::getInvalid();
+ }
+
/// @}
InstructionCost
diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h b/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h
index 9b479f9dc0dc5..88ecd8bc618f0 100644
--- a/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h
+++ b/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h
@@ -57,6 +57,15 @@ class LoongArchTTIImpl : public BasicTTIImplBase<LoongArchTTIImpl> {
TTI::MemCmpExpansionOptions
enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const override;
+
+ InstructionCost getPartialReductionCost(
+ unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
+ ElementCount VF, TTI::PartialReductionExtendKind OpAExtend,
+ TTI::PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
+ TTI::TargetCostKind CostKind,
+ std::optional<FastMathFlags> FMF) const override {
+ return InstructionCost::getInvalid();
+ }
};
} // end namespace llvm
diff --git a/llvm/lib/Target/Mips/MipsTargetTransformInfo.h b/llvm/lib/Target/Mips/MipsTargetTransformInfo.h
index 8f8173915b2fb..585589eb4f705 100644
--- a/llvm/lib/Target/Mips/MipsTargetTransformInfo.h
+++ b/llvm/lib/Target/Mips/MipsTargetTransformInfo.h
@@ -36,6 +36,15 @@ class MipsTTIImpl final : public BasicTTIImplBase<MipsTTIImpl> {
bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
const TargetTransformInfo::LSRCost &C2) const override;
+
+ InstructionCost getPartialReductionCost(
+ unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
+ ElementCount VF, TTI::PartialReductionExtendKind OpAExtend,
+ TTI::PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
+ TTI::TargetCostKind CostKind,
+ std::optional<FastMathFlags> FMF) const override {
+ return InstructionCost::getInvalid();
+ }
};
} // end namespace llvm
diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
index b39c3fc733372..8bdafd6b905f1 100644
--- a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
+++ b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
@@ -222,6 +222,15 @@ class NVPTXTTIImpl final : public BasicTTIImplBase<NVPTXTTIImpl> {
return false;
}
+ InstructionCost getPartialReductionCost(
+ unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
+ ElementCount VF, TTI::PartialReductionExtendKind OpAExtend,
+ TTI::PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
+ TTI::TargetCostKind CostKind,
+ std::optional<FastMathFlags> FMF) const override {
+ return InstructionCost::getInvalid();
+ }
+
ValueUniformity getValueUniformity(const Value *V) const override;
};
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
index 0432a388c4b88..67ac457063d66 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
@@ -169,6 +169,15 @@ class PPCTTIImpl final : public BasicTTIImplBase<PPCTTIImpl> {
getMemIntrinsicInstrCost(const MemIntrinsicCostAttributes &MICA,
TTI::TargetCostKind CostKind) const override;
+ InstructionCost getPartialReductionCost(
+ unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
+ ElementCount VF, TTI::PartialReductionExtendKind OpAExtend,
+ TTI::PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
+ TTI::TargetCostKind CostKind,
+ std::optional<FastMathFlags> FMF) const override {
+ return InstructionCost::getInvalid();
+ }
+
private:
// The following constant is used for estimating costs on power9.
static const InstructionCost::CostType P9PipelineFlushEstimate = 80;
diff --git a/llvm/lib/Target/SPIRV/SPIRVTargetTransformInfo.h b/llvm/lib/Target/SPIRV/SPIRVTargetTransformInfo.h
index 35a1aa1922eed..5d9db79e6f8de 100644
--- a/llvm/lib/Target/SPIRV/SPIRVTargetTransformInfo.h
+++ b/llvm/lib/Target/SPIRV/SPIRVTargetTransformInfo.h
@@ -64,6 +64,15 @@ class SPIRVTTIImpl final : public BasicTTIImplBase<SPIRVTTIImpl> {
bool isLegalMaskedGather(Type *DataType, Align Alignment) const override;
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const override;
+
+ InstructionCost getPartialReductionCost(
+ unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
+ ElementCount VF, TTI::PartialReductionExtendKind OpAExtend,
+ TTI::PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
+ TTI::TargetCostKind CostKind,
+ std::optional<FastMathFlags> FMF) const override {
+ return InstructionCost::getInvalid();
+ }
};
} // namespace llvm
diff --git a/llvm/lib/Target/Sparc/SparcTargetTransformInfo.h b/llvm/lib/Target/Sparc/SparcTargetTransformInfo.h
index 2d4b94c9995fe..7b2b7e4565cd8 100644
--- a/llvm/lib/Target/Sparc/SparcTargetTransformInfo.h
+++ b/llvm/lib/Target/Sparc/SparcTargetTransformInfo.h
@@ -51,6 +51,15 @@ class SparcTTIImpl final : public BasicTTIImplBase<SparcTTIImpl> {
Type *Ty = nullptr) const override;
TypeSize
getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const override;
+
+ InstructionCost getPartialReductionCost(
+ unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
+ ElementCount VF, TTI::PartialReductionExtendKind OpAExtend,
+ TTI::PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
+ TTI::TargetCostKind CostKind,
+ std::optional<FastMathFlags> FMF) const override {
+ return InstructionCost::getInvalid();
+ }
/// @}
};
diff --git a/llvm/lib/Target/VE/VETargetTransformInfo.h b/llvm/lib/Target/VE/VETargetTransformInfo.h
index eed3832c9f1fb..74f0b3dfea9bf 100644
--- a/llvm/lib/Target/VE/VETargetTransformInfo.h
+++ b/llvm/lib/Target/VE/VETargetTransformInfo.h
@@ -157,6 +157,17 @@ class VETTIImpl final : public BasicTTIImplBase<VETTIImpl> {
return true;
return !isSupportedReduction(II->getIntrinsicID());
}
+
+ InstructionCost getPartialReductionCost(
+ unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
+ ElementCount VF,
+ TargetTransformInfo::PartialReductionExtendKind OpAExtend,
+ TargetTransformInfo::PartialReductionExtendKind OpBExtend,
+ std::optional<unsigned> BinOp,
+ TargetTransformInfo::TargetCostKind CostKind,
+ std::optional<FastMathFlags> FMF) const override {
+ return InstructionCost::getInvalid();
+ }
};
} // namespace llvm
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