[llvm] [DAG] computeKnownFPClass - add ISD::FNEG handling + test coverage (PR #190325)

[via llvm-commits]

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@@ -0,0 +1,40 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+f,+d | FileCheck %s
+
+declare i1 @llvm.is.fpclass.f32(float, i32)
+
+define i1 @fneg_const_not_inf() nounwind {
+; CHECK-LABEL: fneg_const_not_inf:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    ret
+  %n = fneg float 1.0
+  %r = call i1 @llvm.is.fpclass.f32(float %n, i32 512) ; +inf
+  ret i1 %r
+}
+
+define i1 @fneg_mask_not_nan(i32 %a) nounwind {
+; CHECK-LABEL: fneg_mask_not_nan:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    ret
+  %m = and i32 %a, u0x007fffff
+  %x = bitcast i32 %m to float
+  %n = fneg float %x
+  %r = call i1 @llvm.is.fpclass.f32(float %n, i32 3) ; nan
+  ret i1 %r
+}
+
+define i1 @fneg_shift_not_inf(i32 %x) nounwind {
+; CHECK-LABEL: fneg_shift_not_inf:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    ret
+  %shl = shl i32 %x, 2
+  %shr = lshr i32 %shl, 2
+  %y = bitcast i32 %shr to float
+
+  %n = fneg float %y
+  %r = call i1 @llvm.is.fpclass.f32(float %n, i32 512) ; +inf
+  ret i1 %r
+}
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s-mv wrote:

I've added one in the latest commit, let me know if it's adequate

https://github.com/llvm/llvm-project/pull/190325