[llvm] [AMDGPU] Use ASan callback functions instead of inline checks in SW Lower LDS pass (PR #190332)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 3 04:42:23 PDT 2026
https://github.com/skc7 updated https://github.com/llvm/llvm-project/pull/190332
>From c71789057c25c749bf2013685c9da4bef2ba1aae Mon Sep 17 00:00:00 2001
From: skc7 <Krishna.Sankisa at amd.com>
Date: Fri, 3 Apr 2026 16:33:24 +0530
Subject: [PATCH] [AMDGPU] Use ASan callback functions instead of inline checks
in SW lower LDS pass
---
.../AMDGPU/AMDGPUAsanInstrumentation.cpp | 41 ++++
llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp | 4 +-
...-lower-lds-dynamic-indirect-access-asan.ll | 123 +-----------
...dgpu-sw-lower-lds-dynamic-lds-test-asan.ll | 26 +--
...lti-static-dynamic-indirect-access-asan.ll | 188 +++---------------
...lds-static-dynamic-indirect-access-asan.ll | 127 +-----------
...-lower-lds-static-dynamic-lds-test-asan.ll | 93 +--------
...w-lower-lds-static-indirect-access-asan.ll | 105 +---------
...tic-indirect-access-function-param-asan.ll | 57 +-----
...gpu-sw-lower-lds-static-lds-no-heap-ptr.ll | 73 +------
...mdgpu-sw-lower-lds-static-lds-test-asan.ll | 73 +------
...lds-static-lds-test-atomic-cmpxchg-asan.ll | 51 +----
...ower-lds-static-lds-test-atomicrmw-asan.ll | 121 +----------
13 files changed, 113 insertions(+), 969 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsanInstrumentation.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsanInstrumentation.cpp
index 9af3b05ff01fa..21761821b21fe 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsanInstrumentation.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsanInstrumentation.cpp
@@ -158,6 +158,32 @@ static void instrumentAddressImpl(Module &M, IRBuilder<> &IRB,
Type *IntptrTy = M.getDataLayout().getIntPtrType(
M.getContext(), AddrTy->getPointerAddressSpace());
IRB.SetInsertPoint(InsertBefore);
+
+ if (UseCalls) {
+ size_t AccessSizeIndex = TypeStoreSizeToSizeIndex(TypeStoreSize);
+ SmallString<64> CallbackName{"__asan_"};
+ CallbackName += IsWrite ? "store" : "load";
+ Value *AddrLong = IRB.CreatePtrToInt(Addr, IntptrTy);
+ if (SizeArgument) {
+ CallbackName += "N";
+ if (Recover)
+ CallbackName += "_noabort";
+ FunctionCallee Callback = M.getOrInsertFunction(
+ CallbackName,
+ FunctionType::get(IRB.getVoidTy(), {IntptrTy, IntptrTy}, false));
+ IRB.CreateCall(Callback, {AddrLong, SizeArgument});
+ } else {
+ raw_svector_ostream OS(CallbackName);
+ OS << (1ULL << AccessSizeIndex);
+ if (Recover)
+ CallbackName += "_noabort";
+ FunctionCallee Callback = M.getOrInsertFunction(
+ CallbackName, FunctionType::get(IRB.getVoidTy(), {IntptrTy}, false));
+ IRB.CreateCall(Callback, AddrLong);
+ }
+ return;
+ }
+
size_t AccessSizeIndex = TypeStoreSizeToSizeIndex(TypeStoreSize);
Type *ShadowTy = IntegerType::get(M.getContext(),
std::max(8U, TypeStoreSize >> AsanScale));
@@ -207,6 +233,21 @@ void instrumentAddress(Module &M, IRBuilder<> &IRB, Instruction *OrigIns,
Type *IntptrTy = M.getDataLayout().getIntPtrType(AddrTy);
Value *NumBits = IRB.CreateTypeSize(IntptrTy, TypeStoreSize);
Value *Size = IRB.CreateLShr(NumBits, ConstantInt::get(IntptrTy, 3));
+
+ if (UseCalls) {
+ Value *AddrLong = IRB.CreatePtrToInt(Addr, IntptrTy);
+ SmallString<64> CallbackName{"__asan_"};
+ CallbackName += IsWrite ? "store" : "load";
+ CallbackName += "N";
+ if (Recover)
+ CallbackName += "_noabort";
+ FunctionCallee Callback = M.getOrInsertFunction(
+ CallbackName,
+ FunctionType::get(IRB.getVoidTy(), {IntptrTy, IntptrTy}, false));
+ IRB.CreateCall(Callback, {AddrLong, Size});
+ return;
+ }
+
Value *AddrLong = IRB.CreatePtrToInt(Addr, IntptrTy);
Value *SizeMinusOne =
IRB.CreateAdd(Size, ConstantInt::getAllOnesValue(IntptrTy));
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
index b012b9e5f9935..75e9c8bb33bbb 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
@@ -1283,8 +1283,8 @@ bool AMDGPUSwLowerLDS::run() {
Value *Addr = Operand.getPtr();
instrumentAddress(M, IRB, Operand.getInsn(), Operand.getInsn(), Addr,
Operand.Alignment.valueOrOne(), Operand.TypeStoreSize,
- Operand.IsWrite, nullptr, false, false, AsanInfo.Scale,
- AsanInfo.Offset);
+ Operand.IsWrite, nullptr, /*UseCalls=*/true,
+ /*Recover=*/false, AsanInfo.Scale, AsanInfo.Offset);
Changed = true;
}
}
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-indirect-access-asan.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-indirect-access-asan.ll
index e3a28b6379077..90e706bfafd00 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-indirect-access-asan.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-indirect-access-asan.ll
@@ -13,8 +13,6 @@
; CHECK: @llvm.amdgcn.sw.lds.k0 = internal addrspace(3) global ptr poison, no_sanitize_address, align 8, !absolute_symbol [[META0:![0-9]+]]
; CHECK: @llvm.amdgcn.k0.dynlds = external addrspace(3) global [0 x i8], no_sanitize_address, align 8, !absolute_symbol [[META1:![0-9]+]]
; CHECK: @llvm.amdgcn.sw.lds.k0.md = internal addrspace(1) global %llvm.amdgcn.sw.lds.k0.md.type { %llvm.amdgcn.sw.lds.k0.md.item { i32 0, i32 8, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 32, i32 1, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 64, i32 4, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 96, i32 0, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 128, i32 0, i32 32 } }, no_sanitize_address
-; CHECK: @llvm.amdgcn.sw.lds.base.table = internal addrspace(1) constant [1 x ptr addrspace(3)] [ptr addrspace(3) @llvm.amdgcn.sw.lds.k0], no_sanitize_address
-; CHECK: @llvm.amdgcn.sw.lds.offset.table = internal addrspace(1) constant [1 x [2 x ptr addrspace(1)]] {{\[}}[2 x ptr addrspace(1)] [ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0), ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 0)]], no_sanitize_address
;.
define void @use_variables() sanitize_address {
; CHECK-LABEL: define void @use_variables(
@@ -34,52 +32,12 @@ define void @use_variables() sanitize_address {
; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr addrspace(3) [[TMP9]] to i32
; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP7]], i32 [[TMP13]]
; CHECK-NEXT: [[TMP47:%.*]] = ptrtoint ptr addrspace(1) [[TMP14]] to i64
-; CHECK-NEXT: [[TMP16:%.*]] = lshr i64 [[TMP47]], 3
-; CHECK-NEXT: [[TMP17:%.*]] = add i64 [[TMP16]], 2147450880
-; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr
-; CHECK-NEXT: [[TMP19:%.*]] = load i8, ptr [[TMP18]], align 1
-; CHECK-NEXT: [[TMP20:%.*]] = icmp ne i8 [[TMP19]], 0
-; CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP47]], 7
-; CHECK-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i8
-; CHECK-NEXT: [[TMP23:%.*]] = icmp sge i8 [[TMP22]], [[TMP19]]
-; CHECK-NEXT: [[TMP24:%.*]] = and i1 [[TMP20]], [[TMP23]]
-; CHECK-NEXT: [[TMP25:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP24]])
-; CHECK-NEXT: [[TMP26:%.*]] = icmp ne i64 [[TMP25]], 0
-; CHECK-NEXT: br i1 [[TMP26]], label [[ASAN_REPORT:%.*]], label [[TMP29:%.*]], !prof [[PROF3:![0-9]+]]
-; CHECK: asan.report:
-; CHECK-NEXT: br i1 [[TMP24]], label [[TMP27:%.*]], label [[TMP28:%.*]]
-; CHECK: 27:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP47]]) #[[ATTR7:[0-9]+]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP28]]
-; CHECK: 28:
-; CHECK-NEXT: br label [[TMP29]]
-; CHECK: 29:
+; CHECK-NEXT: call void @__asan_store1(i64 [[TMP47]])
; CHECK-NEXT: store i8 3, ptr addrspace(1) [[TMP14]], align 4
; CHECK-NEXT: [[TMP30:%.*]] = ptrtoint ptr addrspace(3) [[TMP15]] to i32
; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP7]], i32 [[TMP30]]
; CHECK-NEXT: [[TMP32:%.*]] = ptrtoint ptr addrspace(1) [[TMP31]] to i64
-; CHECK-NEXT: [[TMP33:%.*]] = lshr i64 [[TMP32]], 3
-; CHECK-NEXT: [[TMP34:%.*]] = add i64 [[TMP33]], 2147450880
-; CHECK-NEXT: [[TMP35:%.*]] = inttoptr i64 [[TMP34]] to ptr
-; CHECK-NEXT: [[TMP36:%.*]] = load i8, ptr [[TMP35]], align 1
-; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i8 [[TMP36]], 0
-; CHECK-NEXT: [[TMP38:%.*]] = and i64 [[TMP32]], 7
-; CHECK-NEXT: [[TMP39:%.*]] = trunc i64 [[TMP38]] to i8
-; CHECK-NEXT: [[TMP40:%.*]] = icmp sge i8 [[TMP39]], [[TMP36]]
-; CHECK-NEXT: [[TMP41:%.*]] = and i1 [[TMP37]], [[TMP40]]
-; CHECK-NEXT: [[TMP42:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP41]])
-; CHECK-NEXT: [[TMP43:%.*]] = icmp ne i64 [[TMP42]], 0
-; CHECK-NEXT: br i1 [[TMP43]], label [[ASAN_REPORT1:%.*]], label [[TMP46:%.*]], !prof [[PROF3]]
-; CHECK: asan.report1:
-; CHECK-NEXT: br i1 [[TMP41]], label [[TMP44:%.*]], label [[TMP45:%.*]]
-; CHECK: 44:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP32]]) #[[ATTR7]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP45]]
-; CHECK: 45:
-; CHECK-NEXT: br label [[TMP46]]
-; CHECK: 46:
+; CHECK-NEXT: call void @__asan_store1(i64 [[TMP32]])
; CHECK-NEXT: store i8 3, ptr addrspace(1) [[TMP31]], align 8
; CHECK-NEXT: ret void
;
@@ -90,7 +48,7 @@ define void @use_variables() sanitize_address {
define amdgpu_kernel void @k0() sanitize_address {
; CHECK-LABEL: define amdgpu_kernel void @k0(
-; CHECK-SAME: ) #[[ATTR1:[0-9]+]] !llvm.amdgcn.lds.kernel.id [[META4:![0-9]+]] {
+; CHECK-SAME: ) #[[ATTR1:[0-9]+]] !llvm.amdgcn.lds.kernel.id [[META3:![0-9]+]] {
; CHECK-NEXT: WId:
; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()
@@ -150,77 +108,12 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP38:%.*]] = ptrtoint ptr addrspace(3) [[TMP25]] to i32
; CHECK-NEXT: [[TMP39:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP31]], i32 [[TMP38]]
; CHECK-NEXT: [[TMP40:%.*]] = ptrtoint ptr addrspace(1) [[TMP39]] to i64
-; CHECK-NEXT: [[TMP41:%.*]] = lshr i64 [[TMP40]], 3
-; CHECK-NEXT: [[TMP42:%.*]] = add i64 [[TMP41]], 2147450880
-; CHECK-NEXT: [[TMP43:%.*]] = inttoptr i64 [[TMP42]] to ptr
-; CHECK-NEXT: [[TMP44:%.*]] = load i8, ptr [[TMP43]], align 1
-; CHECK-NEXT: [[TMP45:%.*]] = icmp ne i8 [[TMP44]], 0
-; CHECK-NEXT: [[TMP46:%.*]] = and i64 [[TMP40]], 7
-; CHECK-NEXT: [[TMP47:%.*]] = trunc i64 [[TMP46]] to i8
-; CHECK-NEXT: [[TMP48:%.*]] = icmp sge i8 [[TMP47]], [[TMP44]]
-; CHECK-NEXT: [[TMP49:%.*]] = and i1 [[TMP45]], [[TMP48]]
-; CHECK-NEXT: [[TMP50:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP49]])
-; CHECK-NEXT: [[TMP51:%.*]] = icmp ne i64 [[TMP50]], 0
-; CHECK-NEXT: br i1 [[TMP51]], label [[ASAN_REPORT:%.*]], label [[TMP54:%.*]], !prof [[PROF3]]
-; CHECK: asan.report:
-; CHECK-NEXT: br i1 [[TMP49]], label [[TMP52:%.*]], label [[CONDFREE:%.*]]
-; CHECK: 52:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP40]]) #[[ATTR7]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[CONDFREE]]
-; CHECK: 53:
-; CHECK-NEXT: br label [[TMP54]]
-; CHECK: 54:
+; CHECK-NEXT: call void @__asan_store1(i64 [[TMP40]])
; CHECK-NEXT: store i8 7, ptr addrspace(1) [[TMP39]], align 1
; CHECK-NEXT: [[TMP55:%.*]] = ptrtoint ptr addrspace(3) [[TMP30]] to i32
; CHECK-NEXT: [[TMP56:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP31]], i32 [[TMP55]]
-; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr addrspace(1) [[TMP56]] to i64
-; CHECK-NEXT: [[TMP63:%.*]] = add i64 [[TMP57]], 3
-; CHECK-NEXT: [[TMP90:%.*]] = inttoptr i64 [[TMP63]] to ptr addrspace(1)
; CHECK-NEXT: [[TMP91:%.*]] = ptrtoint ptr addrspace(1) [[TMP56]] to i64
-; CHECK-NEXT: [[TMP58:%.*]] = lshr i64 [[TMP91]], 3
-; CHECK-NEXT: [[TMP59:%.*]] = add i64 [[TMP58]], 2147450880
-; CHECK-NEXT: [[TMP60:%.*]] = inttoptr i64 [[TMP59]] to ptr
-; CHECK-NEXT: [[TMP61:%.*]] = load i8, ptr [[TMP60]], align 1
-; CHECK-NEXT: [[TMP62:%.*]] = icmp ne i8 [[TMP61]], 0
-; CHECK-NEXT: [[TMP64:%.*]] = and i64 [[TMP91]], 7
-; CHECK-NEXT: [[TMP65:%.*]] = trunc i64 [[TMP64]] to i8
-; CHECK-NEXT: [[TMP66:%.*]] = icmp sge i8 [[TMP65]], [[TMP61]]
-; CHECK-NEXT: [[TMP67:%.*]] = and i1 [[TMP62]], [[TMP66]]
-; CHECK-NEXT: [[TMP68:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP67]])
-; CHECK-NEXT: [[TMP69:%.*]] = icmp ne i64 [[TMP68]], 0
-; CHECK-NEXT: br i1 [[TMP69]], label [[ASAN_REPORT1:%.*]], label [[TMP72:%.*]], !prof [[PROF3]]
-; CHECK: asan.report1:
-; CHECK-NEXT: br i1 [[TMP67]], label [[TMP70:%.*]], label [[TMP71:%.*]]
-; CHECK: 72:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP91]]) #[[ATTR7]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP71]]
-; CHECK: 73:
-; CHECK-NEXT: br label [[TMP72]]
-; CHECK: 74:
-; CHECK-NEXT: [[TMP92:%.*]] = ptrtoint ptr addrspace(1) [[TMP90]] to i64
-; CHECK-NEXT: [[TMP76:%.*]] = lshr i64 [[TMP92]], 3
-; CHECK-NEXT: [[TMP77:%.*]] = add i64 [[TMP76]], 2147450880
-; CHECK-NEXT: [[TMP78:%.*]] = inttoptr i64 [[TMP77]] to ptr
-; CHECK-NEXT: [[TMP79:%.*]] = load i8, ptr [[TMP78]], align 1
-; CHECK-NEXT: [[TMP80:%.*]] = icmp ne i8 [[TMP79]], 0
-; CHECK-NEXT: [[TMP81:%.*]] = and i64 [[TMP92]], 7
-; CHECK-NEXT: [[TMP82:%.*]] = trunc i64 [[TMP81]] to i8
-; CHECK-NEXT: [[TMP83:%.*]] = icmp sge i8 [[TMP82]], [[TMP79]]
-; CHECK-NEXT: [[TMP84:%.*]] = and i1 [[TMP80]], [[TMP83]]
-; CHECK-NEXT: [[TMP85:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP84]])
-; CHECK-NEXT: [[TMP86:%.*]] = icmp ne i64 [[TMP85]], 0
-; CHECK-NEXT: br i1 [[TMP86]], label [[ASAN_REPORT2:%.*]], label [[TMP89:%.*]], !prof [[PROF3]]
-; CHECK: asan.report2:
-; CHECK-NEXT: br i1 [[TMP84]], label [[TMP87:%.*]], label [[TMP88:%.*]]
-; CHECK: 87:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP92]]) #[[ATTR7]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP88]]
-; CHECK: 88:
-; CHECK-NEXT: br label [[TMP89]]
-; CHECK: 89:
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP91]], i64 4)
; CHECK-NEXT: store i32 8, ptr addrspace(1) [[TMP56]], align 2
; CHECK-NEXT: br label [[CONDFREE1:%.*]]
; CHECK: CondFree:
@@ -250,13 +143,9 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(none) }
; CHECK: attributes #[[ATTR3:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
; CHECK: attributes #[[ATTR4:[0-9]+]] = { convergent nocallback nofree nounwind willreturn }
-; CHECK: attributes #[[ATTR5:[0-9]+]] = { convergent nocallback nocreateundeforpoison nofree nounwind willreturn memory(none) }
-; CHECK: attributes #[[ATTR6:[0-9]+]] = { convergent nocallback nofree nounwind }
-; CHECK: attributes #[[ATTR7]] = { nomerge }
;.
; CHECK: [[META0]] = !{i32 0, i32 1}
; CHECK: [[META1]] = !{i32 8, i32 9}
; CHECK: [[META2:![0-9]+]] = !{i32 4, !"nosanitize_address", i32 1}
-; CHECK: [[PROF3]] = !{!"branch_weights", i32 1, i32 1048575}
-; CHECK: [[META4]] = !{i32 0}
+; CHECK: [[META3]] = !{i32 0}
;.
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-lds-test-asan.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-lds-test-asan.ll
index 12dcc92f49dc6..00013d4f95c39 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-lds-test-asan.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-lds-test-asan.ll
@@ -55,27 +55,7 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr addrspace(3) [[TMP11]] to i32
; CHECK-NEXT: [[TMP46:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP28]], i32 [[TMP45]]
; CHECK-NEXT: [[TMP29:%.*]] = ptrtoint ptr addrspace(1) [[TMP46]] to i64
-; CHECK-NEXT: [[TMP30:%.*]] = lshr i64 [[TMP29]], 3
-; CHECK-NEXT: [[TMP31:%.*]] = add i64 [[TMP30]], 2147450880
-; CHECK-NEXT: [[TMP32:%.*]] = inttoptr i64 [[TMP31]] to ptr
-; CHECK-NEXT: [[TMP33:%.*]] = load i8, ptr [[TMP32]], align 1
-; CHECK-NEXT: [[TMP34:%.*]] = icmp ne i8 [[TMP33]], 0
-; CHECK-NEXT: [[TMP35:%.*]] = and i64 [[TMP29]], 7
-; CHECK-NEXT: [[TMP36:%.*]] = trunc i64 [[TMP35]] to i8
-; CHECK-NEXT: [[TMP37:%.*]] = icmp sge i8 [[TMP36]], [[TMP33]]
-; CHECK-NEXT: [[TMP38:%.*]] = and i1 [[TMP34]], [[TMP37]]
-; CHECK-NEXT: [[TMP39:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP38]])
-; CHECK-NEXT: [[TMP40:%.*]] = icmp ne i64 [[TMP39]], 0
-; CHECK-NEXT: br i1 [[TMP40]], label [[ASAN_REPORT:%.*]], label [[TMP43:%.*]], !prof [[PROF3:![0-9]+]]
-; CHECK: asan.report:
-; CHECK-NEXT: br i1 [[TMP38]], label [[TMP41:%.*]], label [[CONDFREE:%.*]]
-; CHECK: 41:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP29]]) #[[ATTR6:[0-9]+]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[CONDFREE]]
-; CHECK: 42:
-; CHECK-NEXT: br label [[TMP43]]
-; CHECK: 43:
+; CHECK-NEXT: call void @__asan_store1(i64 [[TMP29]])
; CHECK-NEXT: store i8 7, ptr addrspace(1) [[TMP46]], align 4
; CHECK-NEXT: br label [[CONDFREE1:%.*]]
; CHECK: CondFree:
@@ -103,12 +83,8 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(none) }
; CHECK: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
; CHECK: attributes #[[ATTR3:[0-9]+]] = { convergent nocallback nofree nounwind willreturn }
-; CHECK: attributes #[[ATTR4:[0-9]+]] = { convergent nocallback nocreateundeforpoison nofree nounwind willreturn memory(none) }
-; CHECK: attributes #[[ATTR5:[0-9]+]] = { convergent nocallback nofree nounwind }
-; CHECK: attributes #[[ATTR6]] = { nomerge }
;.
; CHECK: [[META0]] = !{i32 0, i32 1}
; CHECK: [[META1]] = !{i32 8, i32 9}
; CHECK: [[META2:![0-9]+]] = !{i32 4, !"nosanitize_address", i32 1}
-; CHECK: [[PROF3]] = !{!"branch_weights", i32 1, i32 1048575}
;.
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multi-static-dynamic-indirect-access-asan.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multi-static-dynamic-indirect-access-asan.ll
index ca41da7ec42e9..320c7150c952f 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multi-static-dynamic-indirect-access-asan.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multi-static-dynamic-indirect-access-asan.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --version 4
; RUN: opt < %s -passes=amdgpu-sw-lower-lds -S -mtriple=amdgcn-amd-amdhsa | FileCheck %s
; Test to check when multiple kernels access the same non-kernel, LDS accesses are lowere correctly.
@@ -7,6 +7,17 @@
@lds_3 = external addrspace(3) global [0 x i8], align 4
@lds_4 = external addrspace(3) global [0 x i8], align 8
+;.
+; CHECK-DAG: @llvm.amdgcn.sw.lds.k0 = internal addrspace(3) global ptr poison, no_sanitize_address, align 8, !absolute_symbol [[META0:![0-9]+]]
+; CHECK-DAG: @llvm.amdgcn.k0.dynlds = external addrspace(3) global [0 x i8], no_sanitize_address, align 8, !absolute_symbol [[META1:![0-9]+]]
+; CHECK-DAG: @llvm.amdgcn.sw.lds.k0.md = internal addrspace(1) global %llvm.amdgcn.sw.lds.k0.md.type { %llvm.amdgcn.sw.lds.k0.md.item { i32 0, i32 8, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 32, i32 1, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 64, i32 0, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 96, i32 0, i32 32 } }, no_sanitize_address
+; CHECK-DAG: @llvm.amdgcn.sw.lds.k1 = internal addrspace(3) global ptr poison, no_sanitize_address, align 8, !absolute_symbol [[META0]]
+; CHECK-DAG: @llvm.amdgcn.k1.dynlds = external addrspace(3) global [0 x i8], no_sanitize_address, align 8, !absolute_symbol [[META1]]
+; CHECK-DAG: @llvm.amdgcn.sw.lds.k1.md = internal addrspace(1) global %llvm.amdgcn.sw.lds.k1.md.type { %llvm.amdgcn.sw.lds.k1.md.item { i32 0, i32 8, i32 32 }, %llvm.amdgcn.sw.lds.k1.md.item { i32 32, i32 1, i32 32 }, %llvm.amdgcn.sw.lds.k1.md.item { i32 64, i32 4, i32 32 }, %llvm.amdgcn.sw.lds.k1.md.item { i32 96, i32 0, i32 32 }, %llvm.amdgcn.sw.lds.k1.md.item { i32 128, i32 0, i32 32 } }, no_sanitize_address
+; @llvm.amdgcn.sw.lds.base.table = internal addrspace(1) constant [2 x ptr addrspace(3)] [ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, ptr addrspace(3) @llvm.amdgcn.sw.lds.k1], no_sanitize_address
+; @llvm.amdgcn.sw.lds.offset.table = internal addrspace(1) constant [2 x [4 x ptr addrspace(1)]] [[4 x ptr addrspace(1)] [ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), ptr addrspace(1) poison, ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0)], [4 x ptr addrspace(1)] [ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k1.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 1, i32 0), ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k1.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 2, i32 0), ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k1.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 3, i32 0), ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k1.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 4, i32 0)]], no_sanitize_address
+;.
+
define void @use_variables_1() sanitize_address {
; CHECK-LABEL: define void @use_variables_1(
; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
@@ -25,52 +36,12 @@ define void @use_variables_1() sanitize_address {
; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr addrspace(3) [[TMP9]] to i32
; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP7]], i32 [[TMP13]]
; CHECK-NEXT: [[TMP47:%.*]] = ptrtoint ptr addrspace(1) [[TMP14]] to i64
-; CHECK-NEXT: [[TMP16:%.*]] = lshr i64 [[TMP47]], 3
-; CHECK-NEXT: [[TMP17:%.*]] = add i64 [[TMP16]], 2147450880
-; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr
-; CHECK-NEXT: [[TMP19:%.*]] = load i8, ptr [[TMP18]], align 1
-; CHECK-NEXT: [[TMP20:%.*]] = icmp ne i8 [[TMP19]], 0
-; CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP47]], 7
-; CHECK-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i8
-; CHECK-NEXT: [[TMP23:%.*]] = icmp sge i8 [[TMP22]], [[TMP19]]
-; CHECK-NEXT: [[TMP24:%.*]] = and i1 [[TMP20]], [[TMP23]]
-; CHECK-NEXT: [[TMP25:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP24]])
-; CHECK-NEXT: [[TMP26:%.*]] = icmp ne i64 [[TMP25]], 0
-; CHECK-NEXT: br i1 [[TMP26]], label [[ASAN_REPORT:%.*]], label [[TMP29:%.*]], !prof [[PROF3:![0-9]+]]
-; CHECK: asan.report:
-; CHECK-NEXT: br i1 [[TMP24]], label [[TMP27:%.*]], label [[TMP28:%.*]]
-; CHECK: 27:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP47]]) #[[ATTR7:[0-9]+]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP28]]
-; CHECK: 28:
-; CHECK-NEXT: br label [[TMP29]]
-; CHECK: 29:
+; CHECK-NEXT: call void @__asan_store1(i64 [[TMP47]])
; CHECK-NEXT: store i8 3, ptr addrspace(1) [[TMP14]], align 4
; CHECK-NEXT: [[TMP30:%.*]] = ptrtoint ptr addrspace(3) [[TMP15]] to i32
; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP7]], i32 [[TMP30]]
; CHECK-NEXT: [[TMP32:%.*]] = ptrtoint ptr addrspace(1) [[TMP31]] to i64
-; CHECK-NEXT: [[TMP33:%.*]] = lshr i64 [[TMP32]], 3
-; CHECK-NEXT: [[TMP34:%.*]] = add i64 [[TMP33]], 2147450880
-; CHECK-NEXT: [[TMP35:%.*]] = inttoptr i64 [[TMP34]] to ptr
-; CHECK-NEXT: [[TMP36:%.*]] = load i8, ptr [[TMP35]], align 1
-; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i8 [[TMP36]], 0
-; CHECK-NEXT: [[TMP38:%.*]] = and i64 [[TMP32]], 7
-; CHECK-NEXT: [[TMP39:%.*]] = trunc i64 [[TMP38]] to i8
-; CHECK-NEXT: [[TMP40:%.*]] = icmp sge i8 [[TMP39]], [[TMP36]]
-; CHECK-NEXT: [[TMP41:%.*]] = and i1 [[TMP37]], [[TMP40]]
-; CHECK-NEXT: [[TMP42:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP41]])
-; CHECK-NEXT: [[TMP43:%.*]] = icmp ne i64 [[TMP42]], 0
-; CHECK-NEXT: br i1 [[TMP43]], label [[ASAN_REPORT1:%.*]], label [[TMP46:%.*]], !prof [[PROF3]]
-; CHECK: asan.report1:
-; CHECK-NEXT: br i1 [[TMP41]], label [[TMP44:%.*]], label [[TMP45:%.*]]
-; CHECK: 44:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP32]]) #[[ATTR7]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP45]]
-; CHECK: 45:
-; CHECK-NEXT: br label [[TMP46]]
-; CHECK: 46:
+; CHECK-NEXT: call void @__asan_store1(i64 [[TMP32]])
; CHECK-NEXT: store i8 3, ptr addrspace(1) [[TMP31]], align 8
; CHECK-NEXT: ret void
;
@@ -97,77 +68,12 @@ define void @use_variables_2() sanitize_address {
; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr addrspace(3) [[TMP9]] to i32
; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP7]], i32 [[TMP13]]
; CHECK-NEXT: [[TMP48:%.*]] = ptrtoint ptr addrspace(1) [[TMP14]] to i64
-; CHECK-NEXT: [[TMP16:%.*]] = lshr i64 [[TMP48]], 3
-; CHECK-NEXT: [[TMP17:%.*]] = add i64 [[TMP16]], 2147450880
-; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr
-; CHECK-NEXT: [[TMP19:%.*]] = load i8, ptr [[TMP18]], align 1
-; CHECK-NEXT: [[TMP20:%.*]] = icmp ne i8 [[TMP19]], 0
-; CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP48]], 7
-; CHECK-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i8
-; CHECK-NEXT: [[TMP23:%.*]] = icmp sge i8 [[TMP22]], [[TMP19]]
-; CHECK-NEXT: [[TMP24:%.*]] = and i1 [[TMP20]], [[TMP23]]
-; CHECK-NEXT: [[TMP25:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP24]])
-; CHECK-NEXT: [[TMP26:%.*]] = icmp ne i64 [[TMP25]], 0
-; CHECK-NEXT: br i1 [[TMP26]], label [[ASAN_REPORT:%.*]], label [[TMP29:%.*]], !prof [[PROF3]]
-; CHECK: asan.report:
-; CHECK-NEXT: br i1 [[TMP24]], label [[TMP27:%.*]], label [[TMP28:%.*]]
-; CHECK: 27:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP48]]) #[[ATTR7]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP28]]
-; CHECK: 28:
-; CHECK-NEXT: br label [[TMP29]]
-; CHECK: 29:
+; CHECK-NEXT: call void @__asan_store1(i64 [[TMP48]])
; CHECK-NEXT: store i8 7, ptr addrspace(1) [[TMP14]], align 1
; CHECK-NEXT: [[TMP30:%.*]] = ptrtoint ptr addrspace(3) [[TMP15]] to i32
; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP7]], i32 [[TMP30]]
-; CHECK-NEXT: [[TMP32:%.*]] = ptrtoint ptr addrspace(1) [[TMP31]] to i64
-; CHECK-NEXT: [[TMP38:%.*]] = add i64 [[TMP32]], 3
-; CHECK-NEXT: [[TMP49:%.*]] = inttoptr i64 [[TMP38]] to ptr addrspace(1)
; CHECK-NEXT: [[TMP65:%.*]] = ptrtoint ptr addrspace(1) [[TMP31]] to i64
-; CHECK-NEXT: [[TMP33:%.*]] = lshr i64 [[TMP65]], 3
-; CHECK-NEXT: [[TMP34:%.*]] = add i64 [[TMP33]], 2147450880
-; CHECK-NEXT: [[TMP35:%.*]] = inttoptr i64 [[TMP34]] to ptr
-; CHECK-NEXT: [[TMP36:%.*]] = load i8, ptr [[TMP35]], align 1
-; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i8 [[TMP36]], 0
-; CHECK-NEXT: [[TMP39:%.*]] = and i64 [[TMP65]], 7
-; CHECK-NEXT: [[TMP40:%.*]] = trunc i64 [[TMP39]] to i8
-; CHECK-NEXT: [[TMP41:%.*]] = icmp sge i8 [[TMP40]], [[TMP36]]
-; CHECK-NEXT: [[TMP42:%.*]] = and i1 [[TMP37]], [[TMP41]]
-; CHECK-NEXT: [[TMP43:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP42]])
-; CHECK-NEXT: [[TMP44:%.*]] = icmp ne i64 [[TMP43]], 0
-; CHECK-NEXT: br i1 [[TMP44]], label [[ASAN_REPORT1:%.*]], label [[TMP47:%.*]], !prof [[PROF3]]
-; CHECK: asan.report1:
-; CHECK-NEXT: br i1 [[TMP42]], label [[TMP45:%.*]], label [[TMP46:%.*]]
-; CHECK: 47:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP65]]) #[[ATTR7]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP46]]
-; CHECK: 48:
-; CHECK-NEXT: br label [[TMP47]]
-; CHECK: 49:
-; CHECK-NEXT: [[TMP50:%.*]] = ptrtoint ptr addrspace(1) [[TMP49]] to i64
-; CHECK-NEXT: [[TMP51:%.*]] = lshr i64 [[TMP50]], 3
-; CHECK-NEXT: [[TMP52:%.*]] = add i64 [[TMP51]], 2147450880
-; CHECK-NEXT: [[TMP53:%.*]] = inttoptr i64 [[TMP52]] to ptr
-; CHECK-NEXT: [[TMP54:%.*]] = load i8, ptr [[TMP53]], align 1
-; CHECK-NEXT: [[TMP55:%.*]] = icmp ne i8 [[TMP54]], 0
-; CHECK-NEXT: [[TMP56:%.*]] = and i64 [[TMP50]], 7
-; CHECK-NEXT: [[TMP57:%.*]] = trunc i64 [[TMP56]] to i8
-; CHECK-NEXT: [[TMP58:%.*]] = icmp sge i8 [[TMP57]], [[TMP54]]
-; CHECK-NEXT: [[TMP59:%.*]] = and i1 [[TMP55]], [[TMP58]]
-; CHECK-NEXT: [[TMP60:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP59]])
-; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i64 [[TMP60]], 0
-; CHECK-NEXT: br i1 [[TMP61]], label [[ASAN_REPORT2:%.*]], label [[TMP64:%.*]], !prof [[PROF3]]
-; CHECK: asan.report2:
-; CHECK-NEXT: br i1 [[TMP59]], label [[TMP62:%.*]], label [[TMP63:%.*]]
-; CHECK: 62:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP50]]) #[[ATTR7]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP63]]
-; CHECK: 63:
-; CHECK-NEXT: br label [[TMP64]]
-; CHECK: 64:
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP65]], i64 4)
; CHECK-NEXT: store i32 8, ptr addrspace(1) [[TMP31]], align 2
; CHECK-NEXT: ret void
;
@@ -178,7 +84,7 @@ define void @use_variables_2() sanitize_address {
define amdgpu_kernel void @k0() sanitize_address {
; CHECK-LABEL: define amdgpu_kernel void @k0(
-; CHECK-SAME: ) #[[ATTR1:[0-9]+]] !llvm.amdgcn.lds.kernel.id [[META4:![0-9]+]] {
+; CHECK-SAME: ) #[[ATTR1:[0-9]+]] !llvm.amdgcn.lds.kernel.id [[META3:![0-9]+]] {
; CHECK-NEXT: WId:
; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()
@@ -233,27 +139,7 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP34:%.*]] = ptrtoint ptr addrspace(3) [[TMP23]] to i32
; CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP29]], i32 [[TMP34]]
; CHECK-NEXT: [[TMP36:%.*]] = ptrtoint ptr addrspace(1) [[TMP35]] to i64
-; CHECK-NEXT: [[TMP37:%.*]] = lshr i64 [[TMP36]], 3
-; CHECK-NEXT: [[TMP38:%.*]] = add i64 [[TMP37]], 2147450880
-; CHECK-NEXT: [[TMP39:%.*]] = inttoptr i64 [[TMP38]] to ptr
-; CHECK-NEXT: [[TMP40:%.*]] = load i8, ptr [[TMP39]], align 1
-; CHECK-NEXT: [[TMP41:%.*]] = icmp ne i8 [[TMP40]], 0
-; CHECK-NEXT: [[TMP42:%.*]] = and i64 [[TMP36]], 7
-; CHECK-NEXT: [[TMP43:%.*]] = trunc i64 [[TMP42]] to i8
-; CHECK-NEXT: [[TMP44:%.*]] = icmp sge i8 [[TMP43]], [[TMP40]]
-; CHECK-NEXT: [[TMP45:%.*]] = and i1 [[TMP41]], [[TMP44]]
-; CHECK-NEXT: [[TMP46:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP45]])
-; CHECK-NEXT: [[TMP47:%.*]] = icmp ne i64 [[TMP46]], 0
-; CHECK-NEXT: br i1 [[TMP47]], label [[ASAN_REPORT:%.*]], label [[TMP50:%.*]], !prof [[PROF3]]
-; CHECK: asan.report:
-; CHECK-NEXT: br i1 [[TMP45]], label [[TMP48:%.*]], label [[CONDFREE:%.*]]
-; CHECK: 48:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP36]]) #[[ATTR7]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[CONDFREE]]
-; CHECK: 49:
-; CHECK-NEXT: br label [[TMP50]]
-; CHECK: 50:
+; CHECK-NEXT: call void @__asan_store1(i64 [[TMP36]])
; CHECK-NEXT: store i8 7, ptr addrspace(1) [[TMP35]], align 1
; CHECK-NEXT: br label [[CONDFREE1:%.*]]
; CHECK: CondFree:
@@ -275,7 +161,7 @@ define amdgpu_kernel void @k0() sanitize_address {
define amdgpu_kernel void @k1() sanitize_address {
; CHECK-LABEL: define amdgpu_kernel void @k1(
-; CHECK-SAME: ) #[[ATTR1]] !llvm.amdgcn.lds.kernel.id [[META5:![0-9]+]] {
+; CHECK-SAME: ) #[[ATTR1]] !llvm.amdgcn.lds.kernel.id [[META4:![0-9]+]] {
; CHECK-NEXT: WId:
; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()
@@ -334,27 +220,7 @@ define amdgpu_kernel void @k1() sanitize_address {
; CHECK-NEXT: [[TMP58:%.*]] = ptrtoint ptr addrspace(3) [[TMP32]] to i32
; CHECK-NEXT: [[TMP59:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP29]], i32 [[TMP58]]
; CHECK-NEXT: [[TMP38:%.*]] = ptrtoint ptr addrspace(1) [[TMP59]] to i64
-; CHECK-NEXT: [[TMP39:%.*]] = lshr i64 [[TMP38]], 3
-; CHECK-NEXT: [[TMP40:%.*]] = add i64 [[TMP39]], 2147450880
-; CHECK-NEXT: [[TMP41:%.*]] = inttoptr i64 [[TMP40]] to ptr
-; CHECK-NEXT: [[TMP42:%.*]] = load i8, ptr [[TMP41]], align 1
-; CHECK-NEXT: [[TMP43:%.*]] = icmp ne i8 [[TMP42]], 0
-; CHECK-NEXT: [[TMP44:%.*]] = and i64 [[TMP38]], 7
-; CHECK-NEXT: [[TMP45:%.*]] = trunc i64 [[TMP44]] to i8
-; CHECK-NEXT: [[TMP46:%.*]] = icmp sge i8 [[TMP45]], [[TMP42]]
-; CHECK-NEXT: [[TMP47:%.*]] = and i1 [[TMP43]], [[TMP46]]
-; CHECK-NEXT: [[TMP48:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP47]])
-; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i64 [[TMP48]], 0
-; CHECK-NEXT: br i1 [[TMP49]], label [[ASAN_REPORT:%.*]], label [[TMP52:%.*]], !prof [[PROF3]]
-; CHECK: asan.report:
-; CHECK-NEXT: br i1 [[TMP47]], label [[TMP50:%.*]], label [[CONDFREE:%.*]]
-; CHECK: 50:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP38]]) #[[ATTR7]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[CONDFREE]]
-; CHECK: 51:
-; CHECK-NEXT: br label [[TMP52]]
-; CHECK: 52:
+; CHECK-NEXT: call void @__asan_store1(i64 [[TMP38]])
; CHECK-NEXT: store i8 3, ptr addrspace(1) [[TMP59]], align 4
; CHECK-NEXT: br label [[CONDFREE1:%.*]]
; CHECK: CondFree:
@@ -379,7 +245,15 @@ define amdgpu_kernel void @k1() sanitize_address {
!0 = !{i32 4, !"nosanitize_address", i32 1}
;.
-; CHECK: [[PROF3]] = !{!"branch_weights", i32 1, i32 1048575}
-; CHECK: [[META4]] = !{i32 0}
-; CHECK: [[META5]] = !{i32 1}
+; CHECK: attributes #[[ATTR0]] = { sanitize_address }
+; CHECK: attributes #[[ATTR1]] = { sanitize_address "amdgpu-lds-size"="8,8" }
+; CHECK: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(none) }
+; CHECK: attributes #[[ATTR3:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+; CHECK: attributes #[[ATTR4:[0-9]+]] = { convergent nocallback nofree nounwind willreturn }
+;.
+; CHECK: [[META0]] = !{i32 0, i32 1}
+; CHECK: [[META1]] = !{i32 8, i32 9}
+; CHECK: [[META2:![0-9]+]] = !{i32 4, !"nosanitize_address", i32 1}
+; CHECK: [[META3]] = !{i32 0}
+; CHECK: [[META4]] = !{i32 1}
;.
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-indirect-access-asan.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-indirect-access-asan.ll
index 310398ad6948c..d28cdcf5e6ca0 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-indirect-access-asan.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-indirect-access-asan.ll
@@ -8,14 +8,12 @@
@lds_3 = external addrspace(3) global [0 x i8], align 4
@lds_4 = external addrspace(3) global [0 x i8], align 8
-; @llvm.amdgcn.sw.lds.base.table = internal addrspace(1) constant [1 x ptr addrspace(3)] [ptr addrspace(3) @llvm.amdgcn.sw.lds.k0], no_sanitize_address
-; @llvm.amdgcn.sw.lds.offset.table = internal addrspace(1) constant [1 x [2 x ptr addrspace(1)]] {{\[}}[2 x ptr addrspace(1)] [ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0), ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 0)]], no_sanitize_address
;.
; CHECK: @llvm.amdgcn.sw.lds.k0 = internal addrspace(3) global ptr poison, no_sanitize_address, align 8, !absolute_symbol [[META0:![0-9]+]]
; CHECK: @llvm.amdgcn.k0.dynlds = external addrspace(3) global [0 x i8], no_sanitize_address, align 8, !absolute_symbol [[META1:![0-9]+]]
; CHECK: @llvm.amdgcn.sw.lds.k0.md = internal addrspace(1) global %llvm.amdgcn.sw.lds.k0.md.type { %llvm.amdgcn.sw.lds.k0.md.item { i32 0, i32 8, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 32, i32 1, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 64, i32 4, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 96, i32 0, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 128, i32 0, i32 32 } }, no_sanitize_address
-; CHECK: @llvm.amdgcn.sw.lds.base.table = internal addrspace(1) constant [1 x ptr addrspace(3)] [ptr addrspace(3) @llvm.amdgcn.sw.lds.k0], no_sanitize_address
-; CHECK: @llvm.amdgcn.sw.lds.offset.table = internal addrspace(1) constant [1 x [2 x ptr addrspace(1)]] {{\[}}[2 x ptr addrspace(1)] [ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0), ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 0)]], no_sanitize_address
+; @llvm.amdgcn.sw.lds.base.table = internal addrspace(1) constant [1 x ptr addrspace(3)] [ptr addrspace(3) @llvm.amdgcn.sw.lds.k0], no_sanitize_address
+; @llvm.amdgcn.sw.lds.offset.table = internal addrspace(1) constant [1 x [2 x ptr addrspace(1)]] [[2 x ptr addrspace(1)] [ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0), ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 0)]], no_sanitize_address
;.
define void @use_variables() sanitize_address {
; CHECK-LABEL: define void @use_variables(
@@ -35,52 +33,12 @@ define void @use_variables() sanitize_address {
; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr addrspace(3) [[TMP9]] to i32
; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP7]], i32 [[TMP13]]
; CHECK-NEXT: [[TMP47:%.*]] = ptrtoint ptr addrspace(1) [[TMP14]] to i64
-; CHECK-NEXT: [[TMP16:%.*]] = lshr i64 [[TMP47]], 3
-; CHECK-NEXT: [[TMP17:%.*]] = add i64 [[TMP16]], 2147450880
-; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr
-; CHECK-NEXT: [[TMP19:%.*]] = load i8, ptr [[TMP18]], align 1
-; CHECK-NEXT: [[TMP20:%.*]] = icmp ne i8 [[TMP19]], 0
-; CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP47]], 7
-; CHECK-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i8
-; CHECK-NEXT: [[TMP23:%.*]] = icmp sge i8 [[TMP22]], [[TMP19]]
-; CHECK-NEXT: [[TMP24:%.*]] = and i1 [[TMP20]], [[TMP23]]
-; CHECK-NEXT: [[TMP25:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP24]])
-; CHECK-NEXT: [[TMP26:%.*]] = icmp ne i64 [[TMP25]], 0
-; CHECK-NEXT: br i1 [[TMP26]], label [[ASAN_REPORT:%.*]], label [[TMP29:%.*]], !prof [[PROF3:![0-9]+]]
-; CHECK: asan.report:
-; CHECK-NEXT: br i1 [[TMP24]], label [[TMP27:%.*]], label [[TMP28:%.*]]
-; CHECK: 27:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP47]]) #[[ATTR7:[0-9]+]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP28]]
-; CHECK: 28:
-; CHECK-NEXT: br label [[TMP29]]
-; CHECK: 29:
+; CHECK-NEXT: call void @__asan_store1(i64 [[TMP47]])
; CHECK-NEXT: store i8 3, ptr addrspace(1) [[TMP14]], align 4
; CHECK-NEXT: [[TMP30:%.*]] = ptrtoint ptr addrspace(3) [[TMP15]] to i32
; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP7]], i32 [[TMP30]]
; CHECK-NEXT: [[TMP32:%.*]] = ptrtoint ptr addrspace(1) [[TMP31]] to i64
-; CHECK-NEXT: [[TMP33:%.*]] = lshr i64 [[TMP32]], 3
-; CHECK-NEXT: [[TMP34:%.*]] = add i64 [[TMP33]], 2147450880
-; CHECK-NEXT: [[TMP35:%.*]] = inttoptr i64 [[TMP34]] to ptr
-; CHECK-NEXT: [[TMP36:%.*]] = load i8, ptr [[TMP35]], align 1
-; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i8 [[TMP36]], 0
-; CHECK-NEXT: [[TMP38:%.*]] = and i64 [[TMP32]], 7
-; CHECK-NEXT: [[TMP39:%.*]] = trunc i64 [[TMP38]] to i8
-; CHECK-NEXT: [[TMP40:%.*]] = icmp sge i8 [[TMP39]], [[TMP36]]
-; CHECK-NEXT: [[TMP41:%.*]] = and i1 [[TMP37]], [[TMP40]]
-; CHECK-NEXT: [[TMP42:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP41]])
-; CHECK-NEXT: [[TMP43:%.*]] = icmp ne i64 [[TMP42]], 0
-; CHECK-NEXT: br i1 [[TMP43]], label [[ASAN_REPORT1:%.*]], label [[TMP46:%.*]], !prof [[PROF3]]
-; CHECK: asan.report1:
-; CHECK-NEXT: br i1 [[TMP41]], label [[TMP44:%.*]], label [[TMP45:%.*]]
-; CHECK: 44:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP32]]) #[[ATTR7]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP45]]
-; CHECK: 45:
-; CHECK-NEXT: br label [[TMP46]]
-; CHECK: 46:
+; CHECK-NEXT: call void @__asan_store1(i64 [[TMP32]])
; CHECK-NEXT: store i8 3, ptr addrspace(1) [[TMP31]], align 8
; CHECK-NEXT: ret void
;
@@ -91,7 +49,7 @@ define void @use_variables() sanitize_address {
define amdgpu_kernel void @k0() sanitize_address {
; CHECK-LABEL: define amdgpu_kernel void @k0(
-; CHECK-SAME: ) #[[ATTR1:[0-9]+]] !llvm.amdgcn.lds.kernel.id [[META4:![0-9]+]] {
+; CHECK-SAME: ) #[[ATTR1:[0-9]+]] !llvm.amdgcn.lds.kernel.id [[META3:![0-9]+]] {
; CHECK-NEXT: WId:
; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()
@@ -151,77 +109,12 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP38:%.*]] = ptrtoint ptr addrspace(3) [[TMP25]] to i32
; CHECK-NEXT: [[TMP39:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP31]], i32 [[TMP38]]
; CHECK-NEXT: [[TMP40:%.*]] = ptrtoint ptr addrspace(1) [[TMP39]] to i64
-; CHECK-NEXT: [[TMP41:%.*]] = lshr i64 [[TMP40]], 3
-; CHECK-NEXT: [[TMP42:%.*]] = add i64 [[TMP41]], 2147450880
-; CHECK-NEXT: [[TMP43:%.*]] = inttoptr i64 [[TMP42]] to ptr
-; CHECK-NEXT: [[TMP44:%.*]] = load i8, ptr [[TMP43]], align 1
-; CHECK-NEXT: [[TMP45:%.*]] = icmp ne i8 [[TMP44]], 0
-; CHECK-NEXT: [[TMP46:%.*]] = and i64 [[TMP40]], 7
-; CHECK-NEXT: [[TMP47:%.*]] = trunc i64 [[TMP46]] to i8
-; CHECK-NEXT: [[TMP48:%.*]] = icmp sge i8 [[TMP47]], [[TMP44]]
-; CHECK-NEXT: [[TMP49:%.*]] = and i1 [[TMP45]], [[TMP48]]
-; CHECK-NEXT: [[TMP50:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP49]])
-; CHECK-NEXT: [[TMP51:%.*]] = icmp ne i64 [[TMP50]], 0
-; CHECK-NEXT: br i1 [[TMP51]], label [[ASAN_REPORT:%.*]], label [[TMP54:%.*]], !prof [[PROF3]]
-; CHECK: asan.report:
-; CHECK-NEXT: br i1 [[TMP49]], label [[TMP52:%.*]], label [[CONDFREE:%.*]]
-; CHECK: 52:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP40]]) #[[ATTR7]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[CONDFREE]]
-; CHECK: 53:
-; CHECK-NEXT: br label [[TMP54]]
-; CHECK: 54:
+; CHECK-NEXT: call void @__asan_store1(i64 [[TMP40]])
; CHECK-NEXT: store i8 7, ptr addrspace(1) [[TMP39]], align 1
; CHECK-NEXT: [[TMP55:%.*]] = ptrtoint ptr addrspace(3) [[TMP30]] to i32
; CHECK-NEXT: [[TMP56:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP31]], i32 [[TMP55]]
-; CHECK-NEXT: [[TMP57:%.*]] = ptrtoint ptr addrspace(1) [[TMP56]] to i64
-; CHECK-NEXT: [[TMP63:%.*]] = add i64 [[TMP57]], 3
-; CHECK-NEXT: [[TMP90:%.*]] = inttoptr i64 [[TMP63]] to ptr addrspace(1)
; CHECK-NEXT: [[TMP91:%.*]] = ptrtoint ptr addrspace(1) [[TMP56]] to i64
-; CHECK-NEXT: [[TMP58:%.*]] = lshr i64 [[TMP91]], 3
-; CHECK-NEXT: [[TMP59:%.*]] = add i64 [[TMP58]], 2147450880
-; CHECK-NEXT: [[TMP60:%.*]] = inttoptr i64 [[TMP59]] to ptr
-; CHECK-NEXT: [[TMP61:%.*]] = load i8, ptr [[TMP60]], align 1
-; CHECK-NEXT: [[TMP62:%.*]] = icmp ne i8 [[TMP61]], 0
-; CHECK-NEXT: [[TMP64:%.*]] = and i64 [[TMP91]], 7
-; CHECK-NEXT: [[TMP65:%.*]] = trunc i64 [[TMP64]] to i8
-; CHECK-NEXT: [[TMP66:%.*]] = icmp sge i8 [[TMP65]], [[TMP61]]
-; CHECK-NEXT: [[TMP67:%.*]] = and i1 [[TMP62]], [[TMP66]]
-; CHECK-NEXT: [[TMP68:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP67]])
-; CHECK-NEXT: [[TMP69:%.*]] = icmp ne i64 [[TMP68]], 0
-; CHECK-NEXT: br i1 [[TMP69]], label [[ASAN_REPORT1:%.*]], label [[TMP72:%.*]], !prof [[PROF3]]
-; CHECK: asan.report1:
-; CHECK-NEXT: br i1 [[TMP67]], label [[TMP70:%.*]], label [[TMP71:%.*]]
-; CHECK: 72:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP91]]) #[[ATTR7]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP71]]
-; CHECK: 73:
-; CHECK-NEXT: br label [[TMP72]]
-; CHECK: 74:
-; CHECK-NEXT: [[TMP92:%.*]] = ptrtoint ptr addrspace(1) [[TMP90]] to i64
-; CHECK-NEXT: [[TMP76:%.*]] = lshr i64 [[TMP92]], 3
-; CHECK-NEXT: [[TMP77:%.*]] = add i64 [[TMP76]], 2147450880
-; CHECK-NEXT: [[TMP78:%.*]] = inttoptr i64 [[TMP77]] to ptr
-; CHECK-NEXT: [[TMP79:%.*]] = load i8, ptr [[TMP78]], align 1
-; CHECK-NEXT: [[TMP80:%.*]] = icmp ne i8 [[TMP79]], 0
-; CHECK-NEXT: [[TMP81:%.*]] = and i64 [[TMP92]], 7
-; CHECK-NEXT: [[TMP82:%.*]] = trunc i64 [[TMP81]] to i8
-; CHECK-NEXT: [[TMP83:%.*]] = icmp sge i8 [[TMP82]], [[TMP79]]
-; CHECK-NEXT: [[TMP84:%.*]] = and i1 [[TMP80]], [[TMP83]]
-; CHECK-NEXT: [[TMP85:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP84]])
-; CHECK-NEXT: [[TMP86:%.*]] = icmp ne i64 [[TMP85]], 0
-; CHECK-NEXT: br i1 [[TMP86]], label [[ASAN_REPORT2:%.*]], label [[TMP89:%.*]], !prof [[PROF3]]
-; CHECK: asan.report2:
-; CHECK-NEXT: br i1 [[TMP84]], label [[TMP87:%.*]], label [[TMP88:%.*]]
-; CHECK: 87:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP92]]) #[[ATTR7]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP88]]
-; CHECK: 88:
-; CHECK-NEXT: br label [[TMP89]]
-; CHECK: 89:
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP91]], i64 4)
; CHECK-NEXT: store i32 8, ptr addrspace(1) [[TMP56]], align 2
; CHECK-NEXT: br label [[CONDFREE1:%.*]]
; CHECK: CondFree:
@@ -251,13 +144,9 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(none) }
; CHECK: attributes #[[ATTR3:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
; CHECK: attributes #[[ATTR4:[0-9]+]] = { convergent nocallback nofree nounwind willreturn }
-; CHECK: attributes #[[ATTR5:[0-9]+]] = { convergent nocallback nocreateundeforpoison nofree nounwind willreturn memory(none) }
-; CHECK: attributes #[[ATTR6:[0-9]+]] = { convergent nocallback nofree nounwind }
-; CHECK: attributes #[[ATTR7]] = { nomerge }
;.
; CHECK: [[META0]] = !{i32 0, i32 1}
; CHECK: [[META1]] = !{i32 8, i32 9}
; CHECK: [[META2:![0-9]+]] = !{i32 4, !"nosanitize_address", i32 1}
-; CHECK: [[PROF3]] = !{!"branch_weights", i32 1, i32 1048575}
-; CHECK: [[META4]] = !{i32 0}
+; CHECK: [[META3]] = !{i32 0}
;.
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-lds-test-asan.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-lds-test-asan.ll
index e5c606addb3b0..62ce51c120246 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-lds-test-asan.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-lds-test-asan.ll
@@ -77,103 +77,22 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP42:%.*]] = ptrtoint ptr addrspace(3) [[TMP25]] to i32
; CHECK-NEXT: [[TMP43:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP35]], i32 [[TMP42]]
; CHECK-NEXT: [[TMP44:%.*]] = ptrtoint ptr addrspace(1) [[TMP43]] to i64
-; CHECK-NEXT: [[TMP45:%.*]] = lshr i64 [[TMP44]], 3
-; CHECK-NEXT: [[TMP46:%.*]] = add i64 [[TMP45]], 2147450880
-; CHECK-NEXT: [[TMP47:%.*]] = inttoptr i64 [[TMP46]] to ptr
-; CHECK-NEXT: [[TMP48:%.*]] = load i8, ptr [[TMP47]], align 1
-; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i8 [[TMP48]], 0
-; CHECK-NEXT: [[TMP50:%.*]] = and i64 [[TMP44]], 7
-; CHECK-NEXT: [[TMP51:%.*]] = trunc i64 [[TMP50]] to i8
-; CHECK-NEXT: [[TMP52:%.*]] = icmp sge i8 [[TMP51]], [[TMP48]]
-; CHECK-NEXT: [[TMP53:%.*]] = and i1 [[TMP49]], [[TMP52]]
-; CHECK-NEXT: [[TMP54:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP53]])
-; CHECK-NEXT: [[TMP55:%.*]] = icmp ne i64 [[TMP54]], 0
-; CHECK-NEXT: br i1 [[TMP55]], label [[ASAN_REPORT:%.*]], label [[TMP58:%.*]], !prof [[PROF3:![0-9]+]]
-; CHECK: asan.report:
-; CHECK-NEXT: br i1 [[TMP53]], label [[TMP56:%.*]], label [[CONDFREE:%.*]]
-; CHECK: 56:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP44]]) #[[ATTR6:[0-9]+]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[CONDFREE]]
-; CHECK: 57:
-; CHECK-NEXT: br label [[TMP58]]
-; CHECK: 58:
+; CHECK-NEXT: call void @__asan_store1(i64 [[TMP44]])
; CHECK-NEXT: store i8 7, ptr addrspace(1) [[TMP43]], align 4
; CHECK-NEXT: [[TMP59:%.*]] = ptrtoint ptr addrspace(3) [[TMP27]] to i32
; CHECK-NEXT: [[TMP60:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP35]], i32 [[TMP59]]
; CHECK-NEXT: [[TMP61:%.*]] = ptrtoint ptr addrspace(1) [[TMP60]] to i64
-; CHECK-NEXT: [[TMP62:%.*]] = lshr i64 [[TMP61]], 3
-; CHECK-NEXT: [[TMP63:%.*]] = add i64 [[TMP62]], 2147450880
-; CHECK-NEXT: [[TMP64:%.*]] = inttoptr i64 [[TMP63]] to ptr
-; CHECK-NEXT: [[TMP65:%.*]] = load i8, ptr [[TMP64]], align 1
-; CHECK-NEXT: [[TMP66:%.*]] = icmp ne i8 [[TMP65]], 0
-; CHECK-NEXT: [[TMP67:%.*]] = and i64 [[TMP61]], 7
-; CHECK-NEXT: [[TMP68:%.*]] = add i64 [[TMP67]], 3
-; CHECK-NEXT: [[TMP69:%.*]] = trunc i64 [[TMP68]] to i8
-; CHECK-NEXT: [[TMP70:%.*]] = icmp sge i8 [[TMP69]], [[TMP65]]
-; CHECK-NEXT: [[TMP71:%.*]] = and i1 [[TMP66]], [[TMP70]]
-; CHECK-NEXT: [[TMP72:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP71]])
-; CHECK-NEXT: [[TMP73:%.*]] = icmp ne i64 [[TMP72]], 0
-; CHECK-NEXT: br i1 [[TMP73]], label [[ASAN_REPORT1:%.*]], label [[TMP76:%.*]], !prof [[PROF3]]
-; CHECK: asan.report1:
-; CHECK-NEXT: br i1 [[TMP71]], label [[TMP74:%.*]], label [[TMP75:%.*]]
-; CHECK: 74:
-; CHECK-NEXT: call void @__asan_report_store4(i64 [[TMP61]]) #[[ATTR6]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP75]]
-; CHECK: 75:
-; CHECK-NEXT: br label [[TMP76]]
-; CHECK: 76:
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP61]])
; CHECK-NEXT: store i32 8, ptr addrspace(1) [[TMP60]], align 8
; CHECK-NEXT: [[TMP77:%.*]] = ptrtoint ptr addrspace(3) [[TMP29]] to i32
; CHECK-NEXT: [[TMP78:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP35]], i32 [[TMP77]]
; CHECK-NEXT: [[TMP79:%.*]] = ptrtoint ptr addrspace(1) [[TMP78]] to i64
-; CHECK-NEXT: [[TMP80:%.*]] = lshr i64 [[TMP79]], 3
-; CHECK-NEXT: [[TMP81:%.*]] = add i64 [[TMP80]], 2147450880
-; CHECK-NEXT: [[TMP82:%.*]] = inttoptr i64 [[TMP81]] to ptr
-; CHECK-NEXT: [[TMP83:%.*]] = load i8, ptr [[TMP82]], align 1
-; CHECK-NEXT: [[TMP84:%.*]] = icmp ne i8 [[TMP83]], 0
-; CHECK-NEXT: [[TMP85:%.*]] = and i64 [[TMP79]], 7
-; CHECK-NEXT: [[TMP86:%.*]] = trunc i64 [[TMP85]] to i8
-; CHECK-NEXT: [[TMP87:%.*]] = icmp sge i8 [[TMP86]], [[TMP83]]
-; CHECK-NEXT: [[TMP88:%.*]] = and i1 [[TMP84]], [[TMP87]]
-; CHECK-NEXT: [[TMP89:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP88]])
-; CHECK-NEXT: [[TMP90:%.*]] = icmp ne i64 [[TMP89]], 0
-; CHECK-NEXT: br i1 [[TMP90]], label [[ASAN_REPORT2:%.*]], label [[TMP93:%.*]], !prof [[PROF3]]
-; CHECK: asan.report2:
-; CHECK-NEXT: br i1 [[TMP88]], label [[TMP91:%.*]], label [[TMP92:%.*]]
-; CHECK: 91:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP79]]) #[[ATTR6]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP92]]
-; CHECK: 92:
-; CHECK-NEXT: br label [[TMP93]]
-; CHECK: 93:
+; CHECK-NEXT: call void @__asan_store1(i64 [[TMP79]])
; CHECK-NEXT: store i8 7, ptr addrspace(1) [[TMP78]], align 4
; CHECK-NEXT: [[TMP94:%.*]] = ptrtoint ptr addrspace(3) [[TMP34]] to i32
; CHECK-NEXT: [[TMP95:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP35]], i32 [[TMP94]]
; CHECK-NEXT: [[TMP96:%.*]] = ptrtoint ptr addrspace(1) [[TMP95]] to i64
-; CHECK-NEXT: [[TMP97:%.*]] = lshr i64 [[TMP96]], 3
-; CHECK-NEXT: [[TMP98:%.*]] = add i64 [[TMP97]], 2147450880
-; CHECK-NEXT: [[TMP99:%.*]] = inttoptr i64 [[TMP98]] to ptr
-; CHECK-NEXT: [[TMP100:%.*]] = load i8, ptr [[TMP99]], align 1
-; CHECK-NEXT: [[TMP101:%.*]] = icmp ne i8 [[TMP100]], 0
-; CHECK-NEXT: [[TMP102:%.*]] = and i64 [[TMP96]], 7
-; CHECK-NEXT: [[TMP103:%.*]] = trunc i64 [[TMP102]] to i8
-; CHECK-NEXT: [[TMP104:%.*]] = icmp sge i8 [[TMP103]], [[TMP100]]
-; CHECK-NEXT: [[TMP105:%.*]] = and i1 [[TMP101]], [[TMP104]]
-; CHECK-NEXT: [[TMP106:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP105]])
-; CHECK-NEXT: [[TMP107:%.*]] = icmp ne i64 [[TMP106]], 0
-; CHECK-NEXT: br i1 [[TMP107]], label [[ASAN_REPORT3:%.*]], label [[TMP110:%.*]], !prof [[PROF3]]
-; CHECK: asan.report3:
-; CHECK-NEXT: br i1 [[TMP105]], label [[TMP108:%.*]], label [[TMP109:%.*]]
-; CHECK: 108:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP96]]) #[[ATTR6]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP109]]
-; CHECK: 109:
-; CHECK-NEXT: br label [[TMP110]]
-; CHECK: 110:
+; CHECK-NEXT: call void @__asan_store1(i64 [[TMP96]])
; CHECK-NEXT: store i8 8, ptr addrspace(1) [[TMP95]], align 8
; CHECK-NEXT: br label [[CONDFREE1:%.*]]
; CHECK: CondFree:
@@ -203,12 +122,8 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(none) }
; CHECK: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
; CHECK: attributes #[[ATTR3:[0-9]+]] = { convergent nocallback nofree nounwind willreturn }
-; CHECK: attributes #[[ATTR4:[0-9]+]] = { convergent nocallback nocreateundeforpoison nofree nounwind willreturn memory(none) }
-; CHECK: attributes #[[ATTR5:[0-9]+]] = { convergent nocallback nofree nounwind }
-; CHECK: attributes #[[ATTR6]] = { nomerge }
;.
; CHECK: [[META0]] = !{i32 0, i32 1}
; CHECK: [[META1]] = !{i32 8, i32 9}
; CHECK: [[META2:![0-9]+]] = !{i32 4, !"nosanitize_address", i32 1}
-; CHECK: [[PROF3]] = !{!"branch_weights", i32 1, i32 1048575}
;.
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-asan.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-asan.ll
index 9f2287bb54924..76740e0617700 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-asan.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-asan.ll
@@ -7,13 +7,11 @@
@lds_3 = external addrspace(3) global [3 x i8], align 4
@lds_4 = external addrspace(3) global [4 x i8], align 8
-; @llvm.amdgcn.sw.lds.base.table = internal addrspace(1) constant [1 x ptr addrspace(3)] [ptr addrspace(3) @llvm.amdgcn.sw.lds.k0], no_sanitize_address
-; @llvm.amdgcn.sw.lds.offset.table = internal addrspace(1) constant [1 x [2 x ptr addrspace(1)]] {{\[}}[2 x ptr addrspace(1)] [ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0), ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 0)]], no_sanitize_address
;.
; CHECK: @llvm.amdgcn.sw.lds.k0 = internal addrspace(3) global ptr poison, no_sanitize_address, align 8, !absolute_symbol [[META0:![0-9]+]]
; CHECK: @llvm.amdgcn.sw.lds.k0.md = internal addrspace(1) global %llvm.amdgcn.sw.lds.k0.md.type { %llvm.amdgcn.sw.lds.k0.md.item { i32 0, i32 8, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 32, i32 1, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 64, i32 4, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 96, i32 3, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 128, i32 4, i32 32 } }, no_sanitize_address
-; CHECK: @llvm.amdgcn.sw.lds.base.table = internal addrspace(1) constant [1 x ptr addrspace(3)] [ptr addrspace(3) @llvm.amdgcn.sw.lds.k0], no_sanitize_address
-; CHECK: @llvm.amdgcn.sw.lds.offset.table = internal addrspace(1) constant [1 x [2 x ptr addrspace(1)]] {{\[}}[2 x ptr addrspace(1)] [ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0), ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 0)]], no_sanitize_address
+; @llvm.amdgcn.sw.lds.base.table = internal addrspace(1) constant [1 x ptr addrspace(3)] [ptr addrspace(3) @llvm.amdgcn.sw.lds.k0], no_sanitize_address
+; @llvm.amdgcn.sw.lds.offset.table = internal addrspace(1) constant [1 x [2 x ptr addrspace(1)]] [[2 x ptr addrspace(1)] [ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0), ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 0)]], no_sanitize_address
;.
define void @use_variables() sanitize_address {
; CHECK-LABEL: define void @use_variables(
@@ -40,27 +38,7 @@ define void @use_variables() sanitize_address {
; CHECK-NEXT: [[TMP14:%.*]] = ptrtoint ptr addrspace(3) [[TMP15]] to i32
; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP7]], i32 [[TMP14]]
; CHECK-NEXT: [[TMP32:%.*]] = ptrtoint ptr addrspace(1) [[TMP31]] to i64
-; CHECK-NEXT: [[TMP17:%.*]] = lshr i64 [[TMP32]], 3
-; CHECK-NEXT: [[TMP18:%.*]] = add i64 [[TMP17]], 2147450880
-; CHECK-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP18]] to ptr
-; CHECK-NEXT: [[TMP20:%.*]] = load i8, ptr [[TMP19]], align 1
-; CHECK-NEXT: [[TMP21:%.*]] = icmp ne i8 [[TMP20]], 0
-; CHECK-NEXT: [[TMP22:%.*]] = and i64 [[TMP32]], 7
-; CHECK-NEXT: [[TMP23:%.*]] = trunc i64 [[TMP22]] to i8
-; CHECK-NEXT: [[TMP24:%.*]] = icmp sge i8 [[TMP23]], [[TMP20]]
-; CHECK-NEXT: [[TMP25:%.*]] = and i1 [[TMP21]], [[TMP24]]
-; CHECK-NEXT: [[TMP26:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP25]])
-; CHECK-NEXT: [[TMP27:%.*]] = icmp ne i64 [[TMP26]], 0
-; CHECK-NEXT: br i1 [[TMP27]], label %[[ASAN_REPORT:.*]], label %[[BB35:.*]], !prof [[PROF2:![0-9]+]]
-; CHECK: [[ASAN_REPORT]]:
-; CHECK-NEXT: br i1 [[TMP25]], label %[[BB33:.*]], label %[[BB34:.*]]
-; CHECK: [[BB33]]:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP32]]) #[[ATTR7:[0-9]+]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label %[[BB34]]
-; CHECK: [[BB34]]:
-; CHECK-NEXT: br label %[[BB35]]
-; CHECK: [[BB35]]:
+; CHECK-NEXT: call void @__asan_store1(i64 [[TMP32]])
; CHECK-NEXT: store i8 3, ptr addrspace(1) [[TMP31]], align 8
; CHECK-NEXT: ret void
;
@@ -72,7 +50,7 @@ define void @use_variables() sanitize_address {
define amdgpu_kernel void @k0() sanitize_address {
; CHECK-LABEL: define amdgpu_kernel void @k0(
-; CHECK-SAME: ) #[[ATTR1:[0-9]+]] !llvm.amdgcn.lds.kernel.id [[META3:![0-9]+]] {
+; CHECK-SAME: ) #[[ATTR1:[0-9]+]] !llvm.amdgcn.lds.kernel.id [[META2:![0-9]+]] {
; CHECK-NEXT: [[WID:.*]]:
; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()
@@ -119,77 +97,12 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP30:%.*]] = ptrtoint ptr addrspace(3) [[TMP11]] to i32
; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP19]], i32 [[TMP30]]
; CHECK-NEXT: [[TMP32:%.*]] = ptrtoint ptr addrspace(1) [[TMP31]] to i64
-; CHECK-NEXT: [[TMP33:%.*]] = lshr i64 [[TMP32]], 3
-; CHECK-NEXT: [[TMP34:%.*]] = add i64 [[TMP33]], 2147450880
-; CHECK-NEXT: [[TMP35:%.*]] = inttoptr i64 [[TMP34]] to ptr
-; CHECK-NEXT: [[TMP36:%.*]] = load i8, ptr [[TMP35]], align 1
-; CHECK-NEXT: [[TMP37:%.*]] = icmp ne i8 [[TMP36]], 0
-; CHECK-NEXT: [[TMP38:%.*]] = and i64 [[TMP32]], 7
-; CHECK-NEXT: [[TMP39:%.*]] = trunc i64 [[TMP38]] to i8
-; CHECK-NEXT: [[TMP40:%.*]] = icmp sge i8 [[TMP39]], [[TMP36]]
-; CHECK-NEXT: [[TMP41:%.*]] = and i1 [[TMP37]], [[TMP40]]
-; CHECK-NEXT: [[TMP42:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP41]])
-; CHECK-NEXT: [[TMP43:%.*]] = icmp ne i64 [[TMP42]], 0
-; CHECK-NEXT: br i1 [[TMP43]], label %[[ASAN_REPORT:.*]], label %[[BB46:.*]], !prof [[PROF2]]
-; CHECK: [[ASAN_REPORT]]:
-; CHECK-NEXT: br i1 [[TMP41]], label %[[BB44:.*]], label %[[BB45:.*]]
-; CHECK: [[BB44]]:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP32]]) #[[ATTR7]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label %[[BB45]]
-; CHECK: [[BB45]]:
-; CHECK-NEXT: br label %[[BB46]]
-; CHECK: [[BB46]]:
+; CHECK-NEXT: call void @__asan_store1(i64 [[TMP32]])
; CHECK-NEXT: store i8 7, ptr addrspace(1) [[TMP31]], align 1
; CHECK-NEXT: [[TMP47:%.*]] = ptrtoint ptr addrspace(3) [[TMP18]] to i32
; CHECK-NEXT: [[TMP48:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP19]], i32 [[TMP47]]
-; CHECK-NEXT: [[TMP49:%.*]] = ptrtoint ptr addrspace(1) [[TMP48]] to i64
-; CHECK-NEXT: [[TMP55:%.*]] = add i64 [[TMP49]], 3
-; CHECK-NEXT: [[TMP82:%.*]] = inttoptr i64 [[TMP55]] to ptr addrspace(1)
; CHECK-NEXT: [[TMP83:%.*]] = ptrtoint ptr addrspace(1) [[TMP48]] to i64
-; CHECK-NEXT: [[TMP50:%.*]] = lshr i64 [[TMP83]], 3
-; CHECK-NEXT: [[TMP51:%.*]] = add i64 [[TMP50]], 2147450880
-; CHECK-NEXT: [[TMP52:%.*]] = inttoptr i64 [[TMP51]] to ptr
-; CHECK-NEXT: [[TMP53:%.*]] = load i8, ptr [[TMP52]], align 1
-; CHECK-NEXT: [[TMP54:%.*]] = icmp ne i8 [[TMP53]], 0
-; CHECK-NEXT: [[TMP56:%.*]] = and i64 [[TMP83]], 7
-; CHECK-NEXT: [[TMP57:%.*]] = trunc i64 [[TMP56]] to i8
-; CHECK-NEXT: [[TMP58:%.*]] = icmp sge i8 [[TMP57]], [[TMP53]]
-; CHECK-NEXT: [[TMP59:%.*]] = and i1 [[TMP54]], [[TMP58]]
-; CHECK-NEXT: [[TMP60:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP59]])
-; CHECK-NEXT: [[TMP61:%.*]] = icmp ne i64 [[TMP60]], 0
-; CHECK-NEXT: br i1 [[TMP61]], label %[[ASAN_REPORT1:.*]], label %[[BB66:.*]], !prof [[PROF2]]
-; CHECK: [[ASAN_REPORT1]]:
-; CHECK-NEXT: br i1 [[TMP59]], label %[[BB64:.*]], label %[[BB65:.*]]
-; CHECK: [[BB64]]:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP83]]) #[[ATTR7]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label %[[BB65]]
-; CHECK: [[BB65]]:
-; CHECK-NEXT: br label %[[BB66]]
-; CHECK: [[BB66]]:
-; CHECK-NEXT: [[TMP84:%.*]] = ptrtoint ptr addrspace(1) [[TMP82]] to i64
-; CHECK-NEXT: [[TMP85:%.*]] = lshr i64 [[TMP84]], 3
-; CHECK-NEXT: [[TMP69:%.*]] = add i64 [[TMP85]], 2147450880
-; CHECK-NEXT: [[TMP70:%.*]] = inttoptr i64 [[TMP69]] to ptr
-; CHECK-NEXT: [[TMP71:%.*]] = load i8, ptr [[TMP70]], align 1
-; CHECK-NEXT: [[TMP72:%.*]] = icmp ne i8 [[TMP71]], 0
-; CHECK-NEXT: [[TMP73:%.*]] = and i64 [[TMP84]], 7
-; CHECK-NEXT: [[TMP74:%.*]] = trunc i64 [[TMP73]] to i8
-; CHECK-NEXT: [[TMP75:%.*]] = icmp sge i8 [[TMP74]], [[TMP71]]
-; CHECK-NEXT: [[TMP76:%.*]] = and i1 [[TMP72]], [[TMP75]]
-; CHECK-NEXT: [[TMP77:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP76]])
-; CHECK-NEXT: [[TMP78:%.*]] = icmp ne i64 [[TMP77]], 0
-; CHECK-NEXT: br i1 [[TMP78]], label %[[ASAN_REPORT2:.*]], label %[[BB81:.*]], !prof [[PROF2]]
-; CHECK: [[ASAN_REPORT2]]:
-; CHECK-NEXT: br i1 [[TMP76]], label %[[BB79:.*]], label %[[BB80:.*]]
-; CHECK: [[BB79]]:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP84]]) #[[ATTR7]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label %[[BB80]]
-; CHECK: [[BB80]]:
-; CHECK-NEXT: br label %[[BB81]]
-; CHECK: [[BB81]]:
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP83]], i64 4)
; CHECK-NEXT: store i32 8, ptr addrspace(1) [[TMP48]], align 2
; CHECK-NEXT: br label %[[CONDFREE:.*]]
; CHECK: [[CONDFREE]]:
@@ -219,12 +132,8 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
; CHECK: attributes #[[ATTR3:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(none) }
; CHECK: attributes #[[ATTR4:[0-9]+]] = { convergent nocallback nofree nounwind willreturn }
-; CHECK: attributes #[[ATTR5:[0-9]+]] = { convergent nocallback nocreateundeforpoison nofree nounwind willreturn memory(none) }
-; CHECK: attributes #[[ATTR6:[0-9]+]] = { convergent nocallback nofree nounwind }
-; CHECK: attributes #[[ATTR7]] = { nomerge }
;.
; CHECK: [[META0]] = !{i32 0, i32 1}
; CHECK: [[META1:![0-9]+]] = !{i32 4, !"nosanitize_address", i32 1}
-; CHECK: [[PROF2]] = !{!"branch_weights", i32 1, i32 1048575}
-; CHECK: [[META3]] = !{i32 0}
+; CHECK: [[META2]] = !{i32 0}
;.
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-function-param-asan.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-function-param-asan.ll
index 6ca68376befb4..0c1af29cf5350 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-function-param-asan.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-function-param-asan.ll
@@ -6,11 +6,10 @@
@lds_var = internal addrspace(3) global [1024 x i32] poison, align 4
-; @llvm.amdgcn.sw.lds.base.table = internal addrspace(1) constant [1 x ptr addrspace(3)] [ptr addrspace(3) @llvm.amdgcn.sw.lds.my_kernel], no_sanitize_address
;.
; CHECK: @llvm.amdgcn.sw.lds.my_kernel = internal addrspace(3) global ptr poison, no_sanitize_address, align 4, !absolute_symbol [[META0:![0-9]+]]
; CHECK: @llvm.amdgcn.sw.lds.my_kernel.md = internal addrspace(1) global %llvm.amdgcn.sw.lds.my_kernel.md.type { %llvm.amdgcn.sw.lds.my_kernel.md.item { i32 0, i32 8, i32 32 }, %llvm.amdgcn.sw.lds.my_kernel.md.item { i32 32, i32 4096, i32 5120 } }, no_sanitize_address
-; CHECK: @llvm.amdgcn.sw.lds.base.table = internal addrspace(1) constant [1 x ptr addrspace(3)] [ptr addrspace(3) @llvm.amdgcn.sw.lds.my_kernel], no_sanitize_address
+; @llvm.amdgcn.sw.lds.base.table = internal addrspace(1) constant [1 x ptr addrspace(3)] [ptr addrspace(3) @llvm.amdgcn.sw.lds.my_kernel], no_sanitize_address
;.
define void @my_function(ptr addrspace(3) %lds_arg) sanitize_address {
; CHECK-LABEL: define void @my_function(
@@ -22,55 +21,13 @@ define void @my_function(ptr addrspace(3) %lds_arg) sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr addrspace(3) [[LDS_ARG]] to i32
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP4]], i32 [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr addrspace(1) [[TMP6]] to i64
-; CHECK-NEXT: [[TMP8:%.*]] = lshr i64 [[TMP7]], 3
-; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[TMP8]], 2147450880
-; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to ptr
-; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr [[TMP10]], align 1
-; CHECK-NEXT: [[TMP12:%.*]] = icmp ne i8 [[TMP11]], 0
-; CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP7]], 7
-; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[TMP13]], 3
-; CHECK-NEXT: [[TMP15:%.*]] = trunc i64 [[TMP14]] to i8
-; CHECK-NEXT: [[TMP16:%.*]] = icmp sge i8 [[TMP15]], [[TMP11]]
-; CHECK-NEXT: [[TMP17:%.*]] = and i1 [[TMP12]], [[TMP16]]
-; CHECK-NEXT: [[TMP18:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP17]])
-; CHECK-NEXT: [[TMP19:%.*]] = icmp ne i64 [[TMP18]], 0
-; CHECK-NEXT: br i1 [[TMP19]], label [[ASAN_REPORT:%.*]], label [[TMP22:%.*]], !prof [[PROF2:![0-9]+]]
-; CHECK: asan.report:
-; CHECK-NEXT: br i1 [[TMP17]], label [[TMP20:%.*]], label [[TMP21:%.*]]
-; CHECK: 20:
-; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP7]]) #[[ATTR7:[0-9]+]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP21]]
-; CHECK: 21:
-; CHECK-NEXT: br label [[TMP22]]
-; CHECK: 22:
+; CHECK-NEXT: call void @__asan_load4(i64 [[TMP7]])
; CHECK-NEXT: [[LDS_VAL:%.*]] = load i32, ptr addrspace(1) [[TMP6]], align 4
; CHECK-NEXT: [[NEW_LDS_VAL:%.*]] = add i32 [[LDS_VAL]], 1
; CHECK-NEXT: [[TMP24:%.*]] = ptrtoint ptr addrspace(3) [[LDS_ARG]] to i32
; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP4]], i32 [[TMP24]]
; CHECK-NEXT: [[TMP26:%.*]] = ptrtoint ptr addrspace(1) [[TMP25]] to i64
-; CHECK-NEXT: [[TMP27:%.*]] = lshr i64 [[TMP26]], 3
-; CHECK-NEXT: [[TMP28:%.*]] = add i64 [[TMP27]], 2147450880
-; CHECK-NEXT: [[TMP29:%.*]] = inttoptr i64 [[TMP28]] to ptr
-; CHECK-NEXT: [[TMP30:%.*]] = load i8, ptr [[TMP29]], align 1
-; CHECK-NEXT: [[TMP31:%.*]] = icmp ne i8 [[TMP30]], 0
-; CHECK-NEXT: [[TMP32:%.*]] = and i64 [[TMP26]], 7
-; CHECK-NEXT: [[TMP33:%.*]] = add i64 [[TMP32]], 3
-; CHECK-NEXT: [[TMP34:%.*]] = trunc i64 [[TMP33]] to i8
-; CHECK-NEXT: [[TMP35:%.*]] = icmp sge i8 [[TMP34]], [[TMP30]]
-; CHECK-NEXT: [[TMP36:%.*]] = and i1 [[TMP31]], [[TMP35]]
-; CHECK-NEXT: [[TMP37:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP36]])
-; CHECK-NEXT: [[TMP38:%.*]] = icmp ne i64 [[TMP37]], 0
-; CHECK-NEXT: br i1 [[TMP38]], label [[ASAN_REPORT1:%.*]], label [[TMP41:%.*]], !prof [[PROF2]]
-; CHECK: asan.report1:
-; CHECK-NEXT: br i1 [[TMP36]], label [[TMP39:%.*]], label [[TMP40:%.*]]
-; CHECK: 39:
-; CHECK-NEXT: call void @__asan_report_store4(i64 [[TMP26]]) #[[ATTR7]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP40]]
-; CHECK: 40:
-; CHECK-NEXT: br label [[TMP41]]
-; CHECK: 41:
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP26]])
; CHECK-NEXT: store i32 [[NEW_LDS_VAL]], ptr addrspace(1) [[TMP25]], align 4
; CHECK-NEXT: ret void
;
@@ -82,7 +39,7 @@ define void @my_function(ptr addrspace(3) %lds_arg) sanitize_address {
define amdgpu_kernel void @my_kernel() sanitize_address {
; CHECK-LABEL: define amdgpu_kernel void @my_kernel(
-; CHECK-SAME: ) #[[ATTR1:[0-9]+]] !llvm.amdgcn.lds.kernel.id [[META3:![0-9]+]] {
+; CHECK-SAME: ) #[[ATTR1:[0-9]+]] !llvm.amdgcn.lds.kernel.id [[META2:![0-9]+]] {
; CHECK-NEXT: WId:
; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()
@@ -143,12 +100,8 @@ define amdgpu_kernel void @my_kernel() sanitize_address {
; CHECK: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
; CHECK: attributes #[[ATTR3:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(none) }
; CHECK: attributes #[[ATTR4:[0-9]+]] = { convergent nocallback nofree nounwind willreturn }
-; CHECK: attributes #[[ATTR5:[0-9]+]] = { convergent nocallback nocreateundeforpoison nofree nounwind willreturn memory(none) }
-; CHECK: attributes #[[ATTR6:[0-9]+]] = { convergent nocallback nofree nounwind }
-; CHECK: attributes #[[ATTR7]] = { nomerge }
;.
; CHECK: [[META0]] = !{i32 0, i32 1}
; CHECK: [[META1:![0-9]+]] = !{i32 4, !"nosanitize_address", i32 1}
-; CHECK: [[PROF2]] = !{!"branch_weights", i32 1, i32 1048575}
-; CHECK: [[META3]] = !{i32 0}
+; CHECK: [[META2]] = !{i32 0}
;.
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-no-heap-ptr.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-no-heap-ptr.ll
index eca24adad5258..7af67527ed3b4 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-no-heap-ptr.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-no-heap-ptr.ll
@@ -52,77 +52,12 @@ define amdgpu_kernel void @k0() sanitize_address #1 {
; CHECK-NEXT: [[TMP26:%.*]] = ptrtoint ptr addrspace(3) [[TMP23]] to i32
; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP21]], i32 [[TMP26]]
; CHECK-NEXT: [[TMP28:%.*]] = ptrtoint ptr addrspace(1) [[TMP27]] to i64
-; CHECK-NEXT: [[TMP29:%.*]] = lshr i64 [[TMP28]], 3
-; CHECK-NEXT: [[TMP30:%.*]] = add i64 [[TMP29]], 2147450880
-; CHECK-NEXT: [[TMP31:%.*]] = inttoptr i64 [[TMP30]] to ptr
-; CHECK-NEXT: [[TMP32:%.*]] = load i8, ptr [[TMP31]], align 1
-; CHECK-NEXT: [[TMP33:%.*]] = icmp ne i8 [[TMP32]], 0
-; CHECK-NEXT: [[TMP34:%.*]] = and i64 [[TMP28]], 7
-; CHECK-NEXT: [[TMP35:%.*]] = trunc i64 [[TMP34]] to i8
-; CHECK-NEXT: [[TMP36:%.*]] = icmp sge i8 [[TMP35]], [[TMP32]]
-; CHECK-NEXT: [[TMP37:%.*]] = and i1 [[TMP33]], [[TMP36]]
-; CHECK-NEXT: [[TMP38:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP37]])
-; CHECK-NEXT: [[TMP39:%.*]] = icmp ne i64 [[TMP38]], 0
-; CHECK-NEXT: br i1 [[TMP39]], label %[[ASAN_REPORT:.*]], label %[[BB42:.*]], !prof [[PROF2:![0-9]+]]
-; CHECK: [[ASAN_REPORT]]:
-; CHECK-NEXT: br i1 [[TMP37]], label %[[BB40:.*]], label %[[BB41:.*]]
-; CHECK: [[BB40]]:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP28]]) #[[ATTR6:[0-9]+]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label %[[BB41]]
-; CHECK: [[BB41]]:
-; CHECK-NEXT: br label %[[BB42]]
-; CHECK: [[BB42]]:
+; CHECK-NEXT: call void @__asan_store1(i64 [[TMP28]])
; CHECK-NEXT: store i8 7, ptr addrspace(1) [[TMP27]], align 4
; CHECK-NEXT: [[TMP43:%.*]] = ptrtoint ptr addrspace(3) [[TMP25]] to i32
; CHECK-NEXT: [[TMP44:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP21]], i32 [[TMP43]]
-; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr addrspace(1) [[TMP44]] to i64
-; CHECK-NEXT: [[TMP46:%.*]] = add i64 [[TMP45]], 3
-; CHECK-NEXT: [[TMP47:%.*]] = inttoptr i64 [[TMP46]] to ptr addrspace(1)
; CHECK-NEXT: [[TMP48:%.*]] = ptrtoint ptr addrspace(1) [[TMP44]] to i64
-; CHECK-NEXT: [[TMP49:%.*]] = lshr i64 [[TMP48]], 3
-; CHECK-NEXT: [[TMP50:%.*]] = add i64 [[TMP49]], 2147450880
-; CHECK-NEXT: [[TMP51:%.*]] = inttoptr i64 [[TMP50]] to ptr
-; CHECK-NEXT: [[TMP52:%.*]] = load i8, ptr [[TMP51]], align 1
-; CHECK-NEXT: [[TMP53:%.*]] = icmp ne i8 [[TMP52]], 0
-; CHECK-NEXT: [[TMP54:%.*]] = and i64 [[TMP48]], 7
-; CHECK-NEXT: [[TMP55:%.*]] = trunc i64 [[TMP54]] to i8
-; CHECK-NEXT: [[TMP56:%.*]] = icmp sge i8 [[TMP55]], [[TMP52]]
-; CHECK-NEXT: [[TMP57:%.*]] = and i1 [[TMP53]], [[TMP56]]
-; CHECK-NEXT: [[TMP58:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP57]])
-; CHECK-NEXT: [[TMP59:%.*]] = icmp ne i64 [[TMP58]], 0
-; CHECK-NEXT: br i1 [[TMP59]], label %[[ASAN_REPORT1:.*]], label %[[BB62:.*]], !prof [[PROF2]]
-; CHECK: [[ASAN_REPORT1]]:
-; CHECK-NEXT: br i1 [[TMP57]], label %[[BB60:.*]], label %[[BB61:.*]]
-; CHECK: [[BB60]]:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP48]]) #[[ATTR6]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label %[[BB61]]
-; CHECK: [[BB61]]:
-; CHECK-NEXT: br label %[[BB62]]
-; CHECK: [[BB62]]:
-; CHECK-NEXT: [[TMP63:%.*]] = ptrtoint ptr addrspace(1) [[TMP47]] to i64
-; CHECK-NEXT: [[TMP64:%.*]] = lshr i64 [[TMP63]], 3
-; CHECK-NEXT: [[TMP65:%.*]] = add i64 [[TMP64]], 2147450880
-; CHECK-NEXT: [[TMP66:%.*]] = inttoptr i64 [[TMP65]] to ptr
-; CHECK-NEXT: [[TMP67:%.*]] = load i8, ptr [[TMP66]], align 1
-; CHECK-NEXT: [[TMP68:%.*]] = icmp ne i8 [[TMP67]], 0
-; CHECK-NEXT: [[TMP69:%.*]] = and i64 [[TMP63]], 7
-; CHECK-NEXT: [[TMP70:%.*]] = trunc i64 [[TMP69]] to i8
-; CHECK-NEXT: [[TMP71:%.*]] = icmp sge i8 [[TMP70]], [[TMP67]]
-; CHECK-NEXT: [[TMP72:%.*]] = and i1 [[TMP68]], [[TMP71]]
-; CHECK-NEXT: [[TMP73:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP72]])
-; CHECK-NEXT: [[TMP74:%.*]] = icmp ne i64 [[TMP73]], 0
-; CHECK-NEXT: br i1 [[TMP74]], label %[[ASAN_REPORT2:.*]], label %[[BB77:.*]], !prof [[PROF2]]
-; CHECK: [[ASAN_REPORT2]]:
-; CHECK-NEXT: br i1 [[TMP72]], label %[[BB75:.*]], label %[[BB76:.*]]
-; CHECK: [[BB75]]:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP63]]) #[[ATTR6]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label %[[BB76]]
-; CHECK: [[BB76]]:
-; CHECK-NEXT: br label %[[BB77]]
-; CHECK: [[BB77]]:
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP48]], i64 4)
; CHECK-NEXT: store i32 8, ptr addrspace(1) [[TMP44]], align 2
; CHECK-NEXT: br label %[[CONDFREE:.*]]
; CHECK: [[CONDFREE]]:
@@ -150,11 +85,7 @@ attributes #1 = { "amdgpu-no-heap-ptr" }
; CHECK: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
; CHECK: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(none) }
; CHECK: attributes #[[ATTR3:[0-9]+]] = { convergent nocallback nofree nounwind willreturn }
-; CHECK: attributes #[[ATTR4:[0-9]+]] = { convergent nocallback nocreateundeforpoison nofree nounwind willreturn memory(none) }
-; CHECK: attributes #[[ATTR5:[0-9]+]] = { convergent nocallback nofree nounwind }
-; CHECK: attributes #[[ATTR6]] = { nomerge }
;.
; CHECK: [[META0]] = !{i32 0, i32 1}
; CHECK: [[META1:![0-9]+]] = !{i32 4, !"nosanitize_address", i32 1}
-; CHECK: [[PROF2]] = !{!"branch_weights", i32 1, i32 1048575}
;.
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-asan.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-asan.ll
index aa54a96d3658c..5a277e29617f4 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-asan.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-asan.ll
@@ -51,77 +51,12 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP26:%.*]] = ptrtoint ptr addrspace(3) [[TMP18]] to i32
; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP19]], i32 [[TMP26]]
; CHECK-NEXT: [[TMP28:%.*]] = ptrtoint ptr addrspace(1) [[TMP27]] to i64
-; CHECK-NEXT: [[TMP29:%.*]] = lshr i64 [[TMP28]], 3
-; CHECK-NEXT: [[TMP30:%.*]] = add i64 [[TMP29]], 2147450880
-; CHECK-NEXT: [[TMP31:%.*]] = inttoptr i64 [[TMP30]] to ptr
-; CHECK-NEXT: [[TMP32:%.*]] = load i8, ptr [[TMP31]], align 1
-; CHECK-NEXT: [[TMP33:%.*]] = icmp ne i8 [[TMP32]], 0
-; CHECK-NEXT: [[TMP34:%.*]] = and i64 [[TMP28]], 7
-; CHECK-NEXT: [[TMP35:%.*]] = trunc i64 [[TMP34]] to i8
-; CHECK-NEXT: [[TMP36:%.*]] = icmp sge i8 [[TMP35]], [[TMP32]]
-; CHECK-NEXT: [[TMP37:%.*]] = and i1 [[TMP33]], [[TMP36]]
-; CHECK-NEXT: [[TMP38:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP37]])
-; CHECK-NEXT: [[TMP39:%.*]] = icmp ne i64 [[TMP38]], 0
-; CHECK-NEXT: br i1 [[TMP39]], label [[ASAN_REPORT:%.*]], label [[TMP42:%.*]], !prof [[PROF2:![0-9]+]]
-; CHECK: asan.report:
-; CHECK-NEXT: br i1 [[TMP37]], label [[TMP40:%.*]], label [[CONDFREE:%.*]]
-; CHECK: 40:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP28]]) #[[ATTR6:[0-9]+]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[CONDFREE]]
-; CHECK: 41:
-; CHECK-NEXT: br label [[TMP42]]
-; CHECK: 42:
+; CHECK-NEXT: call void @__asan_store1(i64 [[TMP28]])
; CHECK-NEXT: store i8 7, ptr addrspace(1) [[TMP27]], align 4
; CHECK-NEXT: [[TMP43:%.*]] = ptrtoint ptr addrspace(3) [[TMP24]] to i32
; CHECK-NEXT: [[TMP44:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP19]], i32 [[TMP43]]
-; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr addrspace(1) [[TMP44]] to i64
-; CHECK-NEXT: [[TMP51:%.*]] = add i64 [[TMP45]], 3
-; CHECK-NEXT: [[TMP78:%.*]] = inttoptr i64 [[TMP51]] to ptr addrspace(1)
; CHECK-NEXT: [[TMP79:%.*]] = ptrtoint ptr addrspace(1) [[TMP44]] to i64
-; CHECK-NEXT: [[TMP46:%.*]] = lshr i64 [[TMP79]], 3
-; CHECK-NEXT: [[TMP47:%.*]] = add i64 [[TMP46]], 2147450880
-; CHECK-NEXT: [[TMP48:%.*]] = inttoptr i64 [[TMP47]] to ptr
-; CHECK-NEXT: [[TMP49:%.*]] = load i8, ptr [[TMP48]], align 1
-; CHECK-NEXT: [[TMP50:%.*]] = icmp ne i8 [[TMP49]], 0
-; CHECK-NEXT: [[TMP52:%.*]] = and i64 [[TMP79]], 7
-; CHECK-NEXT: [[TMP53:%.*]] = trunc i64 [[TMP52]] to i8
-; CHECK-NEXT: [[TMP54:%.*]] = icmp sge i8 [[TMP53]], [[TMP49]]
-; CHECK-NEXT: [[TMP55:%.*]] = and i1 [[TMP50]], [[TMP54]]
-; CHECK-NEXT: [[TMP56:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP55]])
-; CHECK-NEXT: [[TMP57:%.*]] = icmp ne i64 [[TMP56]], 0
-; CHECK-NEXT: br i1 [[TMP57]], label [[ASAN_REPORT1:%.*]], label [[TMP60:%.*]], !prof [[PROF2]]
-; CHECK: asan.report1:
-; CHECK-NEXT: br i1 [[TMP55]], label [[TMP58:%.*]], label [[TMP59:%.*]]
-; CHECK: 60:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP79]]) #[[ATTR6]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP59]]
-; CHECK: 61:
-; CHECK-NEXT: br label [[TMP60]]
-; CHECK: 62:
-; CHECK-NEXT: [[TMP80:%.*]] = ptrtoint ptr addrspace(1) [[TMP78]] to i64
-; CHECK-NEXT: [[TMP81:%.*]] = lshr i64 [[TMP80]], 3
-; CHECK-NEXT: [[TMP65:%.*]] = add i64 [[TMP81]], 2147450880
-; CHECK-NEXT: [[TMP66:%.*]] = inttoptr i64 [[TMP65]] to ptr
-; CHECK-NEXT: [[TMP67:%.*]] = load i8, ptr [[TMP66]], align 1
-; CHECK-NEXT: [[TMP68:%.*]] = icmp ne i8 [[TMP67]], 0
-; CHECK-NEXT: [[TMP69:%.*]] = and i64 [[TMP80]], 7
-; CHECK-NEXT: [[TMP70:%.*]] = trunc i64 [[TMP69]] to i8
-; CHECK-NEXT: [[TMP71:%.*]] = icmp sge i8 [[TMP70]], [[TMP67]]
-; CHECK-NEXT: [[TMP72:%.*]] = and i1 [[TMP68]], [[TMP71]]
-; CHECK-NEXT: [[TMP73:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP72]])
-; CHECK-NEXT: [[TMP74:%.*]] = icmp ne i64 [[TMP73]], 0
-; CHECK-NEXT: br i1 [[TMP74]], label [[ASAN_REPORT2:%.*]], label [[TMP77:%.*]], !prof [[PROF2]]
-; CHECK: asan.report2:
-; CHECK-NEXT: br i1 [[TMP72]], label [[TMP75:%.*]], label [[TMP76:%.*]]
-; CHECK: 75:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP80]]) #[[ATTR6]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP76]]
-; CHECK: 76:
-; CHECK-NEXT: br label [[TMP77]]
-; CHECK: 77:
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP79]], i64 4)
; CHECK-NEXT: store i32 8, ptr addrspace(1) [[TMP44]], align 2
; CHECK-NEXT: br label [[CONDFREE1:%.*]]
; CHECK: CondFree:
@@ -149,11 +84,7 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
; CHECK: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(none) }
; CHECK: attributes #[[ATTR3:[0-9]+]] = { convergent nocallback nofree nounwind willreturn }
-; CHECK: attributes #[[ATTR4:[0-9]+]] = { convergent nocallback nocreateundeforpoison nofree nounwind willreturn memory(none) }
-; CHECK: attributes #[[ATTR5:[0-9]+]] = { convergent nocallback nofree nounwind }
-; CHECK: attributes #[[ATTR6]] = { nomerge }
;.
; CHECK: [[META0]] = !{i32 0, i32 1}
; CHECK: [[META1:![0-9]+]] = !{i32 4, !"nosanitize_address", i32 1}
-; CHECK: [[PROF2]] = !{!"branch_weights", i32 1, i32 1048575}
;.
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-atomic-cmpxchg-asan.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-atomic-cmpxchg-asan.ll
index fe3e677485c54..53a6c56bbec27 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-atomic-cmpxchg-asan.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-atomic-cmpxchg-asan.ll
@@ -44,53 +44,8 @@ define amdgpu_kernel void @atomic_xchg_kernel(ptr addrspace(1) %out, [8 x i32],
; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr addrspace(3) [[TMP23]], i32 4
; CHECK-NEXT: [[TMP24:%.*]] = ptrtoint ptr addrspace(3) [[GEP]] to i32
; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP21]], i32 [[TMP24]]
-; CHECK-NEXT: [[TMP26:%.*]] = ptrtoint ptr addrspace(1) [[TMP25]] to i64
-; CHECK-NEXT: [[TMP32:%.*]] = add i64 [[TMP26]], 3
-; CHECK-NEXT: [[TMP59:%.*]] = inttoptr i64 [[TMP32]] to ptr addrspace(1)
; CHECK-NEXT: [[TMP60:%.*]] = ptrtoint ptr addrspace(1) [[TMP25]] to i64
-; CHECK-NEXT: [[TMP27:%.*]] = lshr i64 [[TMP60]], 3
-; CHECK-NEXT: [[TMP28:%.*]] = add i64 [[TMP27]], 2147450880
-; CHECK-NEXT: [[TMP29:%.*]] = inttoptr i64 [[TMP28]] to ptr
-; CHECK-NEXT: [[TMP30:%.*]] = load i8, ptr [[TMP29]], align 1
-; CHECK-NEXT: [[TMP31:%.*]] = icmp ne i8 [[TMP30]], 0
-; CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP60]], 7
-; CHECK-NEXT: [[TMP34:%.*]] = trunc i64 [[TMP33]] to i8
-; CHECK-NEXT: [[TMP35:%.*]] = icmp sge i8 [[TMP34]], [[TMP30]]
-; CHECK-NEXT: [[TMP36:%.*]] = and i1 [[TMP31]], [[TMP35]]
-; CHECK-NEXT: [[TMP37:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP36]])
-; CHECK-NEXT: [[TMP38:%.*]] = icmp ne i64 [[TMP37]], 0
-; CHECK-NEXT: br i1 [[TMP38]], label [[ASAN_REPORT:%.*]], label [[TMP41:%.*]], !prof [[PROF2:![0-9]+]]
-; CHECK: asan.report:
-; CHECK-NEXT: br i1 [[TMP36]], label [[TMP39:%.*]], label [[TMP40:%.*]]
-; CHECK: 41:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP60]]) #[[ATTR6:[0-9]+]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP40]]
-; CHECK: 42:
-; CHECK-NEXT: br label [[TMP41]]
-; CHECK: 43:
-; CHECK-NEXT: [[TMP61:%.*]] = ptrtoint ptr addrspace(1) [[TMP59]] to i64
-; CHECK-NEXT: [[TMP62:%.*]] = lshr i64 [[TMP61]], 3
-; CHECK-NEXT: [[TMP46:%.*]] = add i64 [[TMP62]], 2147450880
-; CHECK-NEXT: [[TMP47:%.*]] = inttoptr i64 [[TMP46]] to ptr
-; CHECK-NEXT: [[TMP48:%.*]] = load i8, ptr [[TMP47]], align 1
-; CHECK-NEXT: [[TMP49:%.*]] = icmp ne i8 [[TMP48]], 0
-; CHECK-NEXT: [[TMP50:%.*]] = and i64 [[TMP61]], 7
-; CHECK-NEXT: [[TMP51:%.*]] = trunc i64 [[TMP50]] to i8
-; CHECK-NEXT: [[TMP52:%.*]] = icmp sge i8 [[TMP51]], [[TMP48]]
-; CHECK-NEXT: [[TMP53:%.*]] = and i1 [[TMP49]], [[TMP52]]
-; CHECK-NEXT: [[TMP54:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP53]])
-; CHECK-NEXT: [[TMP55:%.*]] = icmp ne i64 [[TMP54]], 0
-; CHECK-NEXT: br i1 [[TMP55]], label [[ASAN_REPORT1:%.*]], label [[TMP58:%.*]], !prof [[PROF2]]
-; CHECK: asan.report1:
-; CHECK-NEXT: br i1 [[TMP53]], label [[TMP56:%.*]], label [[TMP57:%.*]]
-; CHECK: 56:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP61]]) #[[ATTR6]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP57]]
-; CHECK: 57:
-; CHECK-NEXT: br label [[TMP58]]
-; CHECK: 58:
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP60]], i64 4)
; CHECK-NEXT: [[TMP42:%.*]] = cmpxchg ptr addrspace(1) [[TMP25]], i32 7, i32 [[SWAP]] seq_cst monotonic, align 4
; CHECK-NEXT: [[RESULT:%.*]] = extractvalue { i32, i1 } [[TMP42]], 0
; CHECK-NEXT: store i32 [[RESULT]], ptr addrspace(1) [[OUT]], align 4
@@ -122,11 +77,7 @@ define amdgpu_kernel void @atomic_xchg_kernel(ptr addrspace(1) %out, [8 x i32],
; CHECK: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
; CHECK: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(none) }
; CHECK: attributes #[[ATTR3:[0-9]+]] = { convergent nocallback nofree nounwind willreturn }
-; CHECK: attributes #[[ATTR4:[0-9]+]] = { convergent nocallback nocreateundeforpoison nofree nounwind willreturn memory(none) }
-; CHECK: attributes #[[ATTR5:[0-9]+]] = { convergent nocallback nofree nounwind }
-; CHECK: attributes #[[ATTR6]] = { nomerge }
;.
; CHECK: [[META0]] = !{i32 0, i32 1}
; CHECK: [[META1:![0-9]+]] = !{i32 4, !"nosanitize_address", i32 1}
-; CHECK: [[PROF2]] = !{!"branch_weights", i32 1, i32 1048575}
;.
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-atomicrmw-asan.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-atomicrmw-asan.ll
index 502b1cc9ec5ef..6c65547e07088 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-atomicrmw-asan.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-atomicrmw-asan.ll
@@ -51,130 +51,19 @@ define amdgpu_kernel void @atomicrmw_kernel(ptr addrspace(1) %arg0) sanitize_add
; CHECK-NEXT: [[TMP1:%.*]] = load volatile i32, ptr addrspace(1) [[ARG0]], align 4
; CHECK-NEXT: [[TMP27:%.*]] = ptrtoint ptr addrspace(3) [[TMP23]] to i32
; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP21]], i32 [[TMP27]]
-; CHECK-NEXT: [[TMP29:%.*]] = ptrtoint ptr addrspace(1) [[TMP28]] to i64
-; CHECK-NEXT: [[TMP35:%.*]] = add i64 [[TMP29]], 3
-; CHECK-NEXT: [[TMP98:%.*]] = inttoptr i64 [[TMP35]] to ptr addrspace(1)
; CHECK-NEXT: [[TMP99:%.*]] = ptrtoint ptr addrspace(1) [[TMP28]] to i64
-; CHECK-NEXT: [[TMP30:%.*]] = lshr i64 [[TMP99]], 3
-; CHECK-NEXT: [[TMP31:%.*]] = add i64 [[TMP30]], 2147450880
-; CHECK-NEXT: [[TMP32:%.*]] = inttoptr i64 [[TMP31]] to ptr
-; CHECK-NEXT: [[TMP33:%.*]] = load i8, ptr [[TMP32]], align 1
-; CHECK-NEXT: [[TMP34:%.*]] = icmp ne i8 [[TMP33]], 0
-; CHECK-NEXT: [[TMP36:%.*]] = and i64 [[TMP99]], 7
-; CHECK-NEXT: [[TMP37:%.*]] = trunc i64 [[TMP36]] to i8
-; CHECK-NEXT: [[TMP38:%.*]] = icmp sge i8 [[TMP37]], [[TMP33]]
-; CHECK-NEXT: [[TMP39:%.*]] = and i1 [[TMP34]], [[TMP38]]
-; CHECK-NEXT: [[TMP40:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP39]])
-; CHECK-NEXT: [[TMP41:%.*]] = icmp ne i64 [[TMP40]], 0
-; CHECK-NEXT: br i1 [[TMP41]], label [[ASAN_REPORT:%.*]], label [[TMP44:%.*]], !prof [[PROF2:![0-9]+]]
-; CHECK: asan.report:
-; CHECK-NEXT: br i1 [[TMP39]], label [[TMP42:%.*]], label [[TMP43:%.*]]
-; CHECK: 44:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP99]]) #[[ATTR6:[0-9]+]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP43]]
-; CHECK: 45:
-; CHECK-NEXT: br label [[TMP44]]
-; CHECK: 46:
-; CHECK-NEXT: [[TMP100:%.*]] = ptrtoint ptr addrspace(1) [[TMP98]] to i64
-; CHECK-NEXT: [[TMP101:%.*]] = lshr i64 [[TMP100]], 3
-; CHECK-NEXT: [[TMP102:%.*]] = add i64 [[TMP101]], 2147450880
-; CHECK-NEXT: [[TMP103:%.*]] = inttoptr i64 [[TMP102]] to ptr
-; CHECK-NEXT: [[TMP104:%.*]] = load i8, ptr [[TMP103]], align 1
-; CHECK-NEXT: [[TMP105:%.*]] = icmp ne i8 [[TMP104]], 0
-; CHECK-NEXT: [[TMP106:%.*]] = and i64 [[TMP100]], 7
-; CHECK-NEXT: [[TMP54:%.*]] = trunc i64 [[TMP106]] to i8
-; CHECK-NEXT: [[TMP107:%.*]] = icmp sge i8 [[TMP54]], [[TMP104]]
-; CHECK-NEXT: [[TMP108:%.*]] = and i1 [[TMP105]], [[TMP107]]
-; CHECK-NEXT: [[TMP109:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP108]])
-; CHECK-NEXT: [[TMP110:%.*]] = icmp ne i64 [[TMP109]], 0
-; CHECK-NEXT: br i1 [[TMP110]], label [[ASAN_REPORT1:%.*]], label [[TMP111:%.*]], !prof [[PROF2]]
-; CHECK: asan.report1:
-; CHECK-NEXT: br i1 [[TMP108]], label [[TMP112:%.*]], label [[TMP113:%.*]]
-; CHECK: 59:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP100]]) #[[ATTR6]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP113]]
-; CHECK: 60:
-; CHECK-NEXT: br label [[TMP111]]
-; CHECK: 61:
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP99]], i64 4)
; CHECK-NEXT: [[TMP2:%.*]] = atomicrmw umin ptr addrspace(1) [[TMP28]], i32 [[TMP1]] seq_cst, align 4
; CHECK-NEXT: [[TMP46:%.*]] = ptrtoint ptr addrspace(3) [[TMP23]] to i32
; CHECK-NEXT: [[TMP47:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP21]], i32 [[TMP46]]
-; CHECK-NEXT: [[TMP48:%.*]] = ptrtoint ptr addrspace(1) [[TMP47]] to i64
-; CHECK-NEXT: [[TMP114:%.*]] = add i64 [[TMP48]], 3
-; CHECK-NEXT: [[TMP115:%.*]] = inttoptr i64 [[TMP114]] to ptr addrspace(1)
; CHECK-NEXT: [[TMP116:%.*]] = ptrtoint ptr addrspace(1) [[TMP47]] to i64
-; CHECK-NEXT: [[TMP49:%.*]] = lshr i64 [[TMP116]], 3
-; CHECK-NEXT: [[TMP50:%.*]] = add i64 [[TMP49]], 2147450880
-; CHECK-NEXT: [[TMP51:%.*]] = inttoptr i64 [[TMP50]] to ptr
-; CHECK-NEXT: [[TMP52:%.*]] = load i8, ptr [[TMP51]], align 1
-; CHECK-NEXT: [[TMP53:%.*]] = icmp ne i8 [[TMP52]], 0
-; CHECK-NEXT: [[TMP55:%.*]] = and i64 [[TMP116]], 7
-; CHECK-NEXT: [[TMP56:%.*]] = trunc i64 [[TMP55]] to i8
-; CHECK-NEXT: [[TMP57:%.*]] = icmp sge i8 [[TMP56]], [[TMP52]]
-; CHECK-NEXT: [[TMP58:%.*]] = and i1 [[TMP53]], [[TMP57]]
-; CHECK-NEXT: [[TMP59:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP58]])
-; CHECK-NEXT: [[TMP60:%.*]] = icmp ne i64 [[TMP59]], 0
-; CHECK-NEXT: br i1 [[TMP60]], label [[ASAN_REPORT2:%.*]], label [[TMP63:%.*]], !prof [[PROF2]]
-; CHECK: asan.report2:
-; CHECK-NEXT: br i1 [[TMP58]], label [[TMP61:%.*]], label [[TMP62:%.*]]
-; CHECK: 80:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP116]]) #[[ATTR6]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP62]]
-; CHECK: 81:
-; CHECK-NEXT: br label [[TMP63]]
-; CHECK: 82:
-; CHECK-NEXT: [[TMP117:%.*]] = ptrtoint ptr addrspace(1) [[TMP115]] to i64
-; CHECK-NEXT: [[TMP118:%.*]] = lshr i64 [[TMP117]], 3
-; CHECK-NEXT: [[TMP119:%.*]] = add i64 [[TMP118]], 2147450880
-; CHECK-NEXT: [[TMP120:%.*]] = inttoptr i64 [[TMP119]] to ptr
-; CHECK-NEXT: [[TMP87:%.*]] = load i8, ptr [[TMP120]], align 1
-; CHECK-NEXT: [[TMP88:%.*]] = icmp ne i8 [[TMP87]], 0
-; CHECK-NEXT: [[TMP89:%.*]] = and i64 [[TMP117]], 7
-; CHECK-NEXT: [[TMP90:%.*]] = trunc i64 [[TMP89]] to i8
-; CHECK-NEXT: [[TMP91:%.*]] = icmp sge i8 [[TMP90]], [[TMP87]]
-; CHECK-NEXT: [[TMP92:%.*]] = and i1 [[TMP88]], [[TMP91]]
-; CHECK-NEXT: [[TMP93:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP92]])
-; CHECK-NEXT: [[TMP94:%.*]] = icmp ne i64 [[TMP93]], 0
-; CHECK-NEXT: br i1 [[TMP94]], label [[ASAN_REPORT3:%.*]], label [[TMP97:%.*]], !prof [[PROF2]]
-; CHECK: asan.report3:
-; CHECK-NEXT: br i1 [[TMP92]], label [[TMP95:%.*]], label [[TMP96:%.*]]
-; CHECK: 95:
-; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP117]]) #[[ATTR6]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP96]]
-; CHECK: 96:
-; CHECK-NEXT: br label [[TMP97]]
-; CHECK: 97:
+; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP116]], i64 4)
; CHECK-NEXT: [[TMP3:%.*]] = atomicrmw umax ptr addrspace(1) [[TMP47]], i32 [[TMP1]] seq_cst, align 4
; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP2]], [[TMP3]]
; CHECK-NEXT: [[TMP66:%.*]] = ptrtoint ptr addrspace(3) [[TMP25]] to i32
; CHECK-NEXT: [[TMP67:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP21]], i32 [[TMP66]]
; CHECK-NEXT: [[TMP68:%.*]] = ptrtoint ptr addrspace(1) [[TMP67]] to i64
-; CHECK-NEXT: [[TMP69:%.*]] = lshr i64 [[TMP68]], 3
-; CHECK-NEXT: [[TMP70:%.*]] = add i64 [[TMP69]], 2147450880
-; CHECK-NEXT: [[TMP71:%.*]] = inttoptr i64 [[TMP70]] to ptr
-; CHECK-NEXT: [[TMP72:%.*]] = load i8, ptr [[TMP71]], align 1
-; CHECK-NEXT: [[TMP73:%.*]] = icmp ne i8 [[TMP72]], 0
-; CHECK-NEXT: [[TMP74:%.*]] = and i64 [[TMP68]], 7
-; CHECK-NEXT: [[TMP75:%.*]] = add i64 [[TMP74]], 3
-; CHECK-NEXT: [[TMP76:%.*]] = trunc i64 [[TMP75]] to i8
-; CHECK-NEXT: [[TMP77:%.*]] = icmp sge i8 [[TMP76]], [[TMP72]]
-; CHECK-NEXT: [[TMP78:%.*]] = and i1 [[TMP73]], [[TMP77]]
-; CHECK-NEXT: [[TMP79:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP78]])
-; CHECK-NEXT: [[TMP80:%.*]] = icmp ne i64 [[TMP79]], 0
-; CHECK-NEXT: br i1 [[TMP80]], label [[ASAN_REPORT4:%.*]], label [[TMP83:%.*]], !prof [[PROF2]]
-; CHECK: asan.report4:
-; CHECK-NEXT: br i1 [[TMP78]], label [[TMP81:%.*]], label [[TMP82:%.*]]
-; CHECK: 115:
-; CHECK-NEXT: call void @__asan_report_store4(i64 [[TMP68]]) #[[ATTR6]]
-; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP82]]
-; CHECK: 116:
-; CHECK-NEXT: br label [[TMP83]]
-; CHECK: 117:
+; CHECK-NEXT: call void @__asan_store4(i64 [[TMP68]])
; CHECK-NEXT: store i32 [[TMP4]], ptr addrspace(1) [[TMP67]], align 4
; CHECK-NEXT: br label [[CONDFREE:%.*]]
; CHECK: CondFree:
@@ -204,11 +93,7 @@ define amdgpu_kernel void @atomicrmw_kernel(ptr addrspace(1) %arg0) sanitize_add
; CHECK: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
; CHECK: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(none) }
; CHECK: attributes #[[ATTR3:[0-9]+]] = { convergent nocallback nofree nounwind willreturn }
-; CHECK: attributes #[[ATTR4:[0-9]+]] = { convergent nocallback nocreateundeforpoison nofree nounwind willreturn memory(none) }
-; CHECK: attributes #[[ATTR5:[0-9]+]] = { convergent nocallback nofree nounwind }
-; CHECK: attributes #[[ATTR6]] = { nomerge }
;.
; CHECK: [[META0]] = !{i32 0, i32 1}
; CHECK: [[META1:![0-9]+]] = !{i32 4, !"nosanitize_address", i32 1}
-; CHECK: [[PROF2]] = !{!"branch_weights", i32 1, i32 1048575}
;.
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