[llvm] [DAG] computeKnownFPClass - add ISD::FNEG handling + test coverage (PR #190325)

[via llvm-commits]

https://github.com/s-mv created https://github.com/llvm/llvm-project/pull/190325

Fixes #189483 

- Implement computeKnownFPClass for ISD::FNEG in SelectionDAG.cpp
- Add tests for RISC-V in llvm/test/CodeGen/RISCV/known-fpclass-fneg.ll

>From c0df7f16a7444b1c5b712fe956ba43d300d4ff61 Mon Sep 17 00:00:00 2001
From: smv <shreerangvaidya28 at gmail.com>
Date: Fri, 3 Apr 2026 14:50:33 +0530
Subject: [PATCH] [DAG] add ISD::FNEG handling to computeKnownFPClass + tests

---
 .../lib/CodeGen/SelectionDAG/SelectionDAG.cpp |  6 +++
 llvm/test/CodeGen/RISCV/known-fpclass-fneg.ll | 40 +++++++++++++++++++
 2 files changed, 46 insertions(+)
 create mode 100644 llvm/test/CodeGen/RISCV/known-fpclass-fneg.ll

diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 6eb8853550a19..f7f266e89ff37 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -6055,6 +6055,12 @@ KnownFPClass SelectionDAG::computeKnownFPClass(SDValue Op,
     Known.SignBit = false;
     break;
   }
+  case ISD::FNEG: {
+    Known = computeKnownFPClass(Op.getOperand(0), DemandedElts,
+                                InterestedClasses, Depth + 1);
+    Known.fneg();
+    break;
+  }
   case ISD::BUILD_VECTOR: {
     assert(!VT.isScalableVector());
     bool First = true;
diff --git a/llvm/test/CodeGen/RISCV/known-fpclass-fneg.ll b/llvm/test/CodeGen/RISCV/known-fpclass-fneg.ll
new file mode 100644
index 0000000000000..3c1c02c8d8a75
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/known-fpclass-fneg.ll
@@ -0,0 +1,40 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+f,+d | FileCheck %s
+
+declare i1 @llvm.is.fpclass.f32(float, i32)
+
+define i1 @fneg_const_not_inf() nounwind {
+; CHECK-LABEL: fneg_const_not_inf:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    ret
+  %n = fneg float 1.0
+  %r = call i1 @llvm.is.fpclass.f32(float %n, i32 512) ; +inf
+  ret i1 %r
+}
+
+define i1 @fneg_mask_not_nan(i32 %a) nounwind {
+; CHECK-LABEL: fneg_mask_not_nan:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    ret
+  %m = and i32 %a, u0x007fffff
+  %x = bitcast i32 %m to float
+  %n = fneg float %x
+  %r = call i1 @llvm.is.fpclass.f32(float %n, i32 3) ; nan
+  ret i1 %r
+}
+
+define i1 @fneg_shift_not_inf(i32 %x) nounwind {
+; CHECK-LABEL: fneg_shift_not_inf:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 0
+; CHECK-NEXT:    ret
+  %shl = shl i32 %x, 2
+  %shr = lshr i32 %shl, 2
+  %y = bitcast i32 %shr to float
+
+  %n = fneg float %y
+  %r = call i1 @llvm.is.fpclass.f32(float %n, i32 512) ; +inf
+  ret i1 %r
+}