[llvm] [RISCV] Add scheduler definitions for XiangShan-KunMingHu (PR #148581)
Lin Wang via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 2 02:43:13 PDT 2026
https://github.com/MrLinWang updated https://github.com/llvm/llvm-project/pull/148581
>From 25a96f7568e8771bae335f96e73f5d21571d05dd Mon Sep 17 00:00:00 2001
From: LinWang <linwang2048 at 163.com>
Date: Mon, 14 Jul 2025 15:01:35 +0700
Subject: [PATCH 1/3] [RISC-V] Add scheduler definitions for
XiangShan-KunMingHu
---
llvm/lib/Target/RISCV/RISCV.td | 1 +
llvm/lib/Target/RISCV/RISCVProcessors.td | 2 +-
.../RISCV/RISCVSchedXiangShanKunMingHu.td | 356 ++++++++++++++++++
3 files changed, 358 insertions(+), 1 deletion(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index b24d8637cb27f..2ce3662c88020 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -66,6 +66,7 @@ include "RISCVSchedSyntacoreSCR345.td"
include "RISCVSchedSyntacoreSCR7.td"
include "RISCVSchedTTAscalonD8.td"
include "RISCVSchedXiangShanNanHu.td"
+include "RISCVSchedXiangShanKunMingHu.td"
//===----------------------------------------------------------------------===//
// RISC-V processors supported.
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 838edf6c57250..fa86fa66101f2 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -628,7 +628,7 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
TuneShiftedZExtWFusion]>;
def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
- NoSchedModel,
+ XiangShanKunMingHuModel,
!listconcat(RVA23S64Features,
[FeatureStdExtZacas,
FeatureStdExtZbc,
diff --git a/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td b/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
new file mode 100644
index 0000000000000..06c2b8a0e4aa2
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
@@ -0,0 +1,356 @@
+//==- RISCVSchedXiangShanKunMingHu.td - XiangShanKunMingHu Scheduling Defs -*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+// The XiangShan is a high-performance open-source RISC-V processor project
+// initiated by the Institute of Computing Technology(ICT), Chinese Academy of Sciences(CAS).
+// The KunMingHu architecture is its third-generation derivative,
+// developed by the Institute of Computing Technology, Chinese Academy of Sciences
+// and the Beijing Institute of Open Source Chip (BOSC),
+// with a focus on achieving higher performance.
+// Source: https://github.com/OpenXiangShan/XiangShan
+// Documentation: https://github.com/OpenXiangShan/XiangShan-doc
+
+//===----------------------------------------------------------------------===//
+// KunMingHu core supports "RV64IMAFDCV_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh
+// _zksed_zksh_svinval_zicbom_zicboz_zicsr_zifencei"
+// then floating-point SEW can only be 64 and 32, not 16 and 8.
+//===----------------------------------------------------------------------===//
+
+def XiangShanKunMingHuModel : SchedMachineModel {
+ let IssueWidth = 6; // 6-way decode and dispatch
+ let MicroOpBufferSize = 256;
+ let LoopMicroOpBufferSize = 48; // Instruction queue size
+ let LoadLatency = 6;
+ let MispredictPenalty = 13; // Based on estimate of pipeline depth.
+ let CompleteModel = 0;
+ let UnsupportedFeatures = [HasStdExtZcmt, HasStdExtZkr, HasVInstructions,
+ HasVInstructionsI64];
+}
+
+let SchedModel = XiangShanKunMingHuModel in {
+// Define each kind of processor resource and number available.
+/// Pipline
+let BufferSize = 12 in {
+ // Integer
+ def XSPipeALU0 : ProcResource<1>; // ALU, MUL, BKU
+ def XSPipeALU1 : ProcResource<1>; // ALU, MUL, BKU
+ def XSPipeALU2 : ProcResource<1>; // ALU
+ def XSPipeALU3 : ProcResource<1>; // ALU
+
+ def XSPipeBJU0 : ProcResource<1>; // BRU, JMP
+ def XSPipeBJU1 : ProcResource<1>; // BRU, JMP
+ def XSPipeBJU2 : ProcResource<1>; // BRU, JMP, I2F, I2V, CSR
+ def XSPipeDIV : ProcResource<1>; // DIV
+
+ // Floating-point
+ def XSPipeFEX0 : ProcResource<1>; // FALU, FMA
+ def XSPipeFEX1 : ProcResource<1>; // FCVT
+ def XSPipeFEX2 : ProcResource<1>; // FALU, FMA
+ def XSPipeFEX3 : ProcResource<1>; // FDIV
+}
+
+let BufferSize = 24 in {
+ // Load and store
+ def XSPipeLDU : ProcResource<3>; // LDU
+
+ def XSPipeSTA : ProcResource<2>; // STA
+ def XSPipeSTD : ProcResource<2>; // STD
+}
+
+def XSPipeGroupALU : ProcResGroup<[XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3]>;
+def XSPipeGroupMUL : ProcResGroup<[XSPipeALU0, XSPipeALU1]>;
+def XSPipeGroupBKU : ProcResGroup<[XSPipeALU0, XSPipeALU1]>;
+def XSPipeGroupBRU : ProcResGroup<[XSPipeBJU0, XSPipeBJU1, XSPipeBJU2]>;
+def XSPipeGroupJMP : ProcResGroup<[XSPipeBJU0, XSPipeBJU1, XSPipeBJU2]>;
+
+def XSPipeGroupFALU : ProcResGroup<[XSPipeFEX0, XSPipeFEX2]>;
+def XSPipeGroupFMA : ProcResGroup<[XSPipeFEX0, XSPipeFEX2]>;
+
+def XSPipeGroupSTU : ProcResGroup<[XSPipeSTA, XSPipeSTD]>;
+
+//===----------------------------------------------------------------------===//
+
+
+// Jump
+def : WriteRes<WriteJmp, [XSPipeGroupBRU]>;
+def : WriteRes<WriteJal, [XSPipeGroupJMP]>;
+def : WriteRes<WriteJalr, [XSPipeGroupJMP]>;
+
+// Integer arithmetic and logic
+def : WriteRes<WriteIALU32, [XSPipeGroupALU]>;
+def : WriteRes<WriteIALU, [XSPipeGroupALU]>;
+def : WriteRes<WriteShiftImm32, [XSPipeGroupALU]>;
+def : WriteRes<WriteShiftImm, [XSPipeGroupALU]>;
+def : WriteRes<WriteShiftReg32, [XSPipeGroupALU]>;
+def : WriteRes<WriteShiftReg, [XSPipeGroupALU]>;
+
+// Integer multiplication
+let Latency = 2 in {
+ def : WriteRes<WriteIMul, [XSPipeGroupMUL]>;
+ def : WriteRes<WriteIMul32, [XSPipeGroupMUL]>;
+}
+
+// Integer division
+// Worst case latency is used.
+// The latency of integer division ranges from 4 to 20.
+let Latency = 20, ReleaseAtCycles = [20] in {
+ def : WriteRes<WriteIDiv32, [XSPipeDIV]>;
+ def : WriteRes<WriteIDiv, [XSPipeDIV]>;
+ def : WriteRes<WriteIRem32, [XSPipeDIV]>;
+ def : WriteRes<WriteIRem, [XSPipeDIV]>;
+}
+
+// Memory
+let Latency = 4 in {
+ def : WriteRes<WriteSTB, [XSPipeGroupSTU]>;
+ def : WriteRes<WriteSTH, [XSPipeGroupSTU]>;
+ def : WriteRes<WriteSTW, [XSPipeGroupSTU]>;
+ def : WriteRes<WriteSTD, [XSPipeGroupSTU]>;
+ def : WriteRes<WriteFST32, [XSPipeGroupSTU]>;
+ def : WriteRes<WriteFST64, [XSPipeGroupSTU]>;
+ def : WriteRes<WriteAtomicSTW, [XSPipeGroupSTU]>;
+ def : WriteRes<WriteAtomicSTD, [XSPipeGroupSTU]>;
+}
+
+let Latency = 6 in {
+ def : WriteRes<WriteLDB, [XSPipeLDU]>;
+ def : WriteRes<WriteLDH, [XSPipeLDU]>;
+ def : WriteRes<WriteLDW, [XSPipeLDU]>;
+ def : WriteRes<WriteLDD, [XSPipeLDU]>;
+
+ def : WriteRes<WriteFLD32, [XSPipeLDU]>;
+ def : WriteRes<WriteFLD64, [XSPipeLDU]>;
+
+ def : WriteRes<WriteAtomicW, [XSPipeLDU]>;
+ def : WriteRes<WriteAtomicD, [XSPipeLDU]>;
+ def : WriteRes<WriteAtomicLDW, [XSPipeLDU]>;
+ def : WriteRes<WriteAtomicLDD, [XSPipeLDU]>;
+}
+
+let Latency = 2 in {
+ def : WriteRes<WriteFAdd32, [XSPipeGroupFALU]>;
+ def : WriteRes<WriteFAdd64, [XSPipeGroupFALU]>;
+ def : WriteRes<WriteFCmp32, [XSPipeGroupFALU]>;
+ def : WriteRes<WriteFCmp64, [XSPipeGroupFALU]>;
+ def : WriteRes<WriteFMinMax32, [XSPipeGroupFALU]>;
+ def : WriteRes<WriteFMinMax64, [XSPipeGroupFALU]>;
+ def : WriteRes<WriteFClass32, [XSPipeGroupFALU]>;
+ def : WriteRes<WriteFClass64, [XSPipeGroupFALU]>;
+ def : WriteRes<WriteFSGNJ32, [XSPipeGroupFALU]>;
+ def : WriteRes<WriteFSGNJ64, [XSPipeGroupFALU]>;
+}
+
+let Latency = 2 in {
+ def : WriteRes<WriteFMul32, [XSPipeGroupFMA]>;
+ def : WriteRes<WriteFMul64, [XSPipeGroupFMA]>;
+ def : WriteRes<WriteFMA32, [XSPipeGroupFMA]>;
+ def : WriteRes<WriteFMA64, [XSPipeGroupFMA]>;
+}
+
+// FDIV
+let Latency = 10 in {
+ def : WriteRes<WriteFDiv32, [XSPipeFEX3]>;
+ def : WriteRes<WriteFSqrt32, [XSPipeFEX3]>;
+}
+let Latency = 15 in {
+ def : WriteRes<WriteFDiv64, [XSPipeFEX3]>;
+ def : WriteRes<WriteFSqrt64, [XSPipeFEX3]>;
+}
+
+// FCVT
+let Latency = 3 in {
+ def : WriteRes<WriteFCvtF32ToI32, [XSPipeFEX1]>;
+ def : WriteRes<WriteFCvtF32ToI64, [XSPipeFEX1]>;
+ def : WriteRes<WriteFCvtF64ToI32, [XSPipeFEX1]>;
+ def : WriteRes<WriteFCvtF64ToI64, [XSPipeFEX1]>;
+ def : WriteRes<WriteFCvtF64ToF32, [XSPipeFEX1]>;
+ def : WriteRes<WriteFCvtF32ToF64, [XSPipeFEX1]>;
+ def : WriteRes<WriteFMovF64ToI64, [XSPipeFEX1]>;
+ def : WriteRes<WriteFMovF32ToI32, [XSPipeFEX1]>;
+}
+
+// I2V
+let Latency = 1 in {
+ def : WriteRes<WriteFMovI64ToF64, [XSPipeBJU2]>;
+ def : WriteRes<WriteFMovI32ToF32, [XSPipeBJU2]>;
+}
+
+// I2F
+let Latency = 3 in {
+ def : WriteRes<WriteFCvtI32ToF32, [XSPipeBJU2]>;
+ def : WriteRes<WriteFCvtI64ToF32, [XSPipeBJU2]>;
+ def : WriteRes<WriteFCvtI32ToF64, [XSPipeBJU2]>;
+ def : WriteRes<WriteFCvtI64ToF64, [XSPipeBJU2]>;
+}
+
+/// Zb*
+let Latency = 1 in {
+ // Zba
+ def : WriteRes<WriteSHXADD, [XSPipeGroupALU]>;
+ def : WriteRes<WriteSHXADD32, [XSPipeGroupALU]>;
+
+ // Zbb
+ def : WriteRes<WriteRotateImm, [XSPipeGroupALU]>;
+ def : WriteRes<WriteRotateImm32, [XSPipeGroupALU]>;
+ def : WriteRes<WriteRotateReg, [XSPipeGroupALU]>;
+ def : WriteRes<WriteRotateReg32, [XSPipeGroupALU]>;
+ def : WriteRes<WriteREV8, [XSPipeGroupALU]>;
+ def : WriteRes<WriteORCB, [XSPipeGroupALU]>;
+ def : WriteRes<WriteIMinMax, [XSPipeGroupALU]>;
+
+ // Zbs
+ def : WriteRes<WriteSingleBit, [XSPipeGroupALU]>;
+ def : WriteRes<WriteSingleBitImm, [XSPipeGroupALU]>;
+ def : WriteRes<WriteBEXT, [XSPipeGroupALU]>;
+ def : WriteRes<WriteBEXTI, [XSPipeGroupALU]>;
+
+ // Zbkb
+ def : WriteRes<WriteBREV8, [XSPipeGroupALU]>;
+ def : WriteRes<WritePACK, [XSPipeGroupALU]>;
+ def : WriteRes<WritePACK32, [XSPipeGroupALU]>;
+ def : WriteRes<WriteZIP, [XSPipeGroupALU]>;
+}
+
+let Latency = 3 in {
+ // Zbb
+ def : WriteRes<WriteCLZ, [XSPipeGroupBKU]>;
+ def : WriteRes<WriteCLZ32, [XSPipeGroupBKU]>;
+ def : WriteRes<WriteCTZ, [XSPipeGroupBKU]>;
+ def : WriteRes<WriteCTZ32, [XSPipeGroupBKU]>;
+ def : WriteRes<WriteCPOP, [XSPipeGroupBKU]>;
+ def : WriteRes<WriteCPOP32, [XSPipeGroupBKU]>;
+
+ // Zbc
+ def : WriteRes<WriteCLMUL, [XSPipeGroupBKU]>;
+
+ // Zbkx
+ def : WriteRes<WriteXPERM, [XSPipeGroupBKU]>;
+}
+
+// Others
+def : WriteRes<WriteCSR, [XSPipeBJU2]>;
+def : WriteRes<WriteNop, []>;
+
+def : InstRW<[WriteIALU], (instrs COPY)>;
+
+//===----------------------------------------------------------------------===//
+
+// Bypass and advance
+
+class XSLDUtoAnyBypass<SchedRead read, int cycles = 2>
+ : ReadAdvance<read, cycles, [WriteLDB, WriteLDH,
+ WriteLDW, WriteLDD,
+ WriteFLD32, WriteFLD64,
+ WriteAtomicW, WriteAtomicD,
+ WriteAtomicLDW, WriteAtomicLDD]>;
+
+def : ReadAdvance<ReadJmp, 0>;
+def : ReadAdvance<ReadJalr, 0>;
+def : ReadAdvance<ReadCSR, 0>;
+def : ReadAdvance<ReadStoreData, 0>;
+def : ReadAdvance<ReadMemBase, 0>;
+def : XSLDUtoAnyBypass<ReadIALU>;
+def : XSLDUtoAnyBypass<ReadIALU32>;
+def : XSLDUtoAnyBypass<ReadShiftImm>;
+def : XSLDUtoAnyBypass<ReadShiftImm32>;
+def : XSLDUtoAnyBypass<ReadShiftReg>;
+def : XSLDUtoAnyBypass<ReadShiftReg32>;
+def : ReadAdvance<ReadIDiv, 0>;
+def : ReadAdvance<ReadIDiv32, 0>;
+def : ReadAdvance<ReadIRem, 0>;
+def : ReadAdvance<ReadIRem32, 0>;
+def : ReadAdvance<ReadIMul, 0>;
+def : ReadAdvance<ReadIMul32, 0>;
+def : XSLDUtoAnyBypass<ReadAtomicWA>;
+def : XSLDUtoAnyBypass<ReadAtomicWD>;
+def : XSLDUtoAnyBypass<ReadAtomicDA>;
+def : XSLDUtoAnyBypass<ReadAtomicDD>;
+def : XSLDUtoAnyBypass<ReadAtomicLDW>;
+def : XSLDUtoAnyBypass<ReadAtomicLDD>;
+def : ReadAdvance<ReadAtomicSTW, 0>;
+def : ReadAdvance<ReadAtomicSTD, 0>;
+def : ReadAdvance<ReadFStoreData, 0>;
+def : ReadAdvance<ReadFMemBase, 0>;
+def : ReadAdvance<ReadFAdd32, 0>;
+def : ReadAdvance<ReadFAdd64, 0>;
+def : ReadAdvance<ReadFMul32, 0>;
+def : ReadAdvance<ReadFMul64, 0>;
+def : ReadAdvance<ReadFMA32, 0>;
+def : ReadAdvance<ReadFMA32Addend, 0>;
+def : ReadAdvance<ReadFMA64, 0>;
+def : ReadAdvance<ReadFMA64Addend, 0>;
+def : ReadAdvance<ReadFDiv32, 0>;
+def : ReadAdvance<ReadFDiv64, 0>;
+def : ReadAdvance<ReadFSqrt32, 0>;
+def : ReadAdvance<ReadFSqrt64, 0>;
+def : ReadAdvance<ReadFCmp32, 0>;
+def : ReadAdvance<ReadFCmp64, 0>;
+def : ReadAdvance<ReadFSGNJ32, 0>;
+def : ReadAdvance<ReadFSGNJ64, 0>;
+def : ReadAdvance<ReadFMinMax32, 0>;
+def : ReadAdvance<ReadFMinMax64, 0>;
+def : ReadAdvance<ReadFCvtF32ToI32, 0>;
+def : ReadAdvance<ReadFCvtF32ToI64, 0>;
+def : ReadAdvance<ReadFCvtF64ToI32, 0>;
+def : ReadAdvance<ReadFCvtF64ToI64, 0>;
+def : ReadAdvance<ReadFCvtI32ToF32, 0>;
+def : ReadAdvance<ReadFCvtI32ToF64, 0>;
+def : ReadAdvance<ReadFCvtI64ToF32, 0>;
+def : ReadAdvance<ReadFCvtI64ToF64, 0>;
+def : ReadAdvance<ReadFCvtF32ToF64, 0>;
+def : ReadAdvance<ReadFCvtF64ToF32, 0>;
+def : ReadAdvance<ReadFMovF32ToI32, 0>;
+def : ReadAdvance<ReadFMovI32ToF32, 0>;
+def : ReadAdvance<ReadFMovF64ToI64, 0>;
+def : ReadAdvance<ReadFMovI64ToF64, 0>;
+def : ReadAdvance<ReadFClass32, 0>;
+def : ReadAdvance<ReadFClass64, 0>;
+
+/// B extension
+// Zba
+def : ReadAdvance<ReadSHXADD, 0>;
+def : ReadAdvance<ReadSHXADD32, 0>;
+// Zbb
+def : ReadAdvance<ReadRotateImm, 0>;
+def : ReadAdvance<ReadRotateImm32, 0>;
+def : ReadAdvance<ReadRotateReg, 0>;
+def : ReadAdvance<ReadRotateReg32, 0>;
+def : ReadAdvance<ReadCLZ, 0>;
+def : ReadAdvance<ReadCLZ32, 0>;
+def : ReadAdvance<ReadCTZ, 0>;
+def : ReadAdvance<ReadCTZ32, 0>;
+def : ReadAdvance<ReadCPOP, 0>;
+def : ReadAdvance<ReadCPOP32, 0>;
+def : ReadAdvance<ReadREV8, 0>;
+def : ReadAdvance<ReadORCB, 0>;
+def : ReadAdvance<ReadIMinMax, 0>;
+// Zbc
+def : ReadAdvance<ReadCLMUL, 0>;
+// Zbs
+def : ReadAdvance<ReadSingleBit, 0>;
+def : ReadAdvance<ReadSingleBitImm, 0>;
+// Zbkb
+def : ReadAdvance<ReadBREV8, 0>;
+def : ReadAdvance<ReadPACK, 0>;
+def : ReadAdvance<ReadPACK32, 0>;
+def : ReadAdvance<ReadZIP, 0>;
+// Zbkx
+def : ReadAdvance<ReadXPERM, 0>;
+
+//===----------------------------------------------------------------------===//
+// Unsupported extensions
+defm : UnsupportedSchedQ;
+defm : UnsupportedSchedV;
+defm : UnsupportedSchedZfa;
+defm : UnsupportedSchedZfhmin;
+defm : UnsupportedSchedSFB;
+defm : UnsupportedSchedZabha;
+defm : UnsupportedSchedXsf;
+defm : UnsupportedSchedZvk;
+
+} // SchedModel
>From a75f2e1561e05f60765e51fedafc6849dbe68180 Mon Sep 17 00:00:00 2001
From: LinWang <linwang2048 at 163.com>
Date: Thu, 2 Apr 2026 15:35:46 +0800
Subject: [PATCH 2/3] [RISCV] Add XiangShan Kunminghu scheduling model and test
cases
Add llvm-mca test cases for the XiangShan Kunminghu microarchitecture, including:
- Basic integer and floating-point operation tests
- Branch and memory access instruction tests
- Bit-manipulation extension tests
- Floating-point division and conversion tests
Also update the XiangShan Kunminghu scheduling model:
- Adjust pipeline resource groupings
- Optimize instruction latency and throughput
- Add support for bit-manipulation extensions
- Improve floating-point operation scheduling
---
.../RISCV/RISCVSchedXiangShanKunMingHu.td | 74 ++--
.../RISCV/XiangShan-Kunminghu/bitmanip.s | 179 +++++++++
.../RISCV/XiangShan-Kunminghu/branch.s | 84 +++++
.../RISCV/XiangShan-Kunminghu/cascade-fma.s | 55 +++
.../RISCV/XiangShan-Kunminghu/div-fdiv.s | 119 ++++++
.../RISCV/XiangShan-Kunminghu/fpr-bypass.s | 250 +++++++++++++
.../RISCV/XiangShan-Kunminghu/gpr-bypass.s | 353 ++++++++++++++++++
.../RISCV/XiangShan-Kunminghu/load-store.s | 100 +++++
.../RISCV/XiangShan-Kunminghu/load-to-alu.s | 75 ++++
.../RISCV/XiangShan-Kunminghu/load-to-fpu.s | 75 ++++
.../RISCV/XiangShan-Kunminghu/mul-fmul.s | 74 ++++
.../cascade-fma.s | 0
.../gpr-bypass.s | 0
.../load-to-alu.s | 0
14 files changed, 1404 insertions(+), 34 deletions(-)
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/bitmanip.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/branch.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/cascade-fma.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/div-fdiv.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/fpr-bypass.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/gpr-bypass.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-store.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-alu.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-fpu.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/mul-fmul.s
rename llvm/test/tools/llvm-mca/RISCV/{XiangShan => XiangShan-Nanhu}/cascade-fma.s (100%)
rename llvm/test/tools/llvm-mca/RISCV/{XiangShan => XiangShan-Nanhu}/gpr-bypass.s (100%)
rename llvm/test/tools/llvm-mca/RISCV/{XiangShan => XiangShan-Nanhu}/load-to-alu.s (100%)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td b/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
index 06c2b8a0e4aa2..52a52c99c2245 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
@@ -35,7 +35,7 @@ def XiangShanKunMingHuModel : SchedMachineModel {
let SchedModel = XiangShanKunMingHuModel in {
// Define each kind of processor resource and number available.
/// Pipline
-let BufferSize = 12 in {
+let BufferSize = 24 in {
// Integer
def XSPipeALU0 : ProcResource<1>; // ALU, MUL, BKU
def XSPipeALU1 : ProcResource<1>; // ALU, MUL, BKU
@@ -44,17 +44,20 @@ let BufferSize = 12 in {
def XSPipeBJU0 : ProcResource<1>; // BRU, JMP
def XSPipeBJU1 : ProcResource<1>; // BRU, JMP
- def XSPipeBJU2 : ProcResource<1>; // BRU, JMP, I2F, I2V, CSR
- def XSPipeDIV : ProcResource<1>; // DIV
+ def XSPipeBJU2 : ProcResource<1>; // BRU, JMP, I2F, I2V, VSet
+ def XSPipeBJU3 : ProcResource<1>; // CSR, Fence, DIV
+}
+let BufferSize = 18 in {
// Floating-point
- def XSPipeFEX0 : ProcResource<1>; // FALU, FMA
- def XSPipeFEX1 : ProcResource<1>; // FCVT
+ def XSPipeFEX0 : ProcResource<1>; // FALU, FMA, FCVT, F2V
+ def XSPipeFEX1 : ProcResource<1>; // FDIV
def XSPipeFEX2 : ProcResource<1>; // FALU, FMA
def XSPipeFEX3 : ProcResource<1>; // FDIV
+ def XSPipeFEX4 : ProcResource<1>; // FALU, FMA
}
-let BufferSize = 24 in {
+let BufferSize = 16 in {
// Load and store
def XSPipeLDU : ProcResource<3>; // LDU
@@ -66,10 +69,10 @@ def XSPipeGroupALU : ProcResGroup<[XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU
def XSPipeGroupMUL : ProcResGroup<[XSPipeALU0, XSPipeALU1]>;
def XSPipeGroupBKU : ProcResGroup<[XSPipeALU0, XSPipeALU1]>;
def XSPipeGroupBRU : ProcResGroup<[XSPipeBJU0, XSPipeBJU1, XSPipeBJU2]>;
-def XSPipeGroupJMP : ProcResGroup<[XSPipeBJU0, XSPipeBJU1, XSPipeBJU2]>;
-def XSPipeGroupFALU : ProcResGroup<[XSPipeFEX0, XSPipeFEX2]>;
-def XSPipeGroupFMA : ProcResGroup<[XSPipeFEX0, XSPipeFEX2]>;
+def XSPipeGroupFALU : ProcResGroup<[XSPipeFEX0, XSPipeFEX2, XSPipeFEX4]>;
+def XSPipeGroupFMA : ProcResGroup<[XSPipeFEX0, XSPipeFEX2, XSPipeFEX4]>;
+def XSPipeGroupFDIV : ProcResGroup<[XSPipeFEX1, XSPipeFEX3]>;
def XSPipeGroupSTU : ProcResGroup<[XSPipeSTA, XSPipeSTD]>;
@@ -78,8 +81,8 @@ def XSPipeGroupSTU : ProcResGroup<[XSPipeSTA, XSPipeSTD]>;
// Jump
def : WriteRes<WriteJmp, [XSPipeGroupBRU]>;
-def : WriteRes<WriteJal, [XSPipeGroupJMP]>;
-def : WriteRes<WriteJalr, [XSPipeGroupJMP]>;
+def : WriteRes<WriteJal, [XSPipeGroupBRU]>;
+def : WriteRes<WriteJalr, [XSPipeGroupBRU]>;
// Integer arithmetic and logic
def : WriteRes<WriteIALU32, [XSPipeGroupALU]>;
@@ -99,10 +102,10 @@ let Latency = 2 in {
// Worst case latency is used.
// The latency of integer division ranges from 4 to 20.
let Latency = 20, ReleaseAtCycles = [20] in {
- def : WriteRes<WriteIDiv32, [XSPipeDIV]>;
- def : WriteRes<WriteIDiv, [XSPipeDIV]>;
- def : WriteRes<WriteIRem32, [XSPipeDIV]>;
- def : WriteRes<WriteIRem, [XSPipeDIV]>;
+ def : WriteRes<WriteIDiv32, [XSPipeBJU3]>;
+ def : WriteRes<WriteIDiv, [XSPipeBJU3]>;
+ def : WriteRes<WriteIRem32, [XSPipeBJU3]>;
+ def : WriteRes<WriteIRem, [XSPipeBJU3]>;
}
// Memory
@@ -132,9 +135,12 @@ let Latency = 6 in {
def : WriteRes<WriteAtomicLDD, [XSPipeLDU]>;
}
-let Latency = 2 in {
+let Latency = 1 in {
def : WriteRes<WriteFAdd32, [XSPipeGroupFALU]>;
def : WriteRes<WriteFAdd64, [XSPipeGroupFALU]>;
+}
+
+let Latency = 2 in {
def : WriteRes<WriteFCmp32, [XSPipeGroupFALU]>;
def : WriteRes<WriteFCmp64, [XSPipeGroupFALU]>;
def : WriteRes<WriteFMinMax32, [XSPipeGroupFALU]>;
@@ -145,7 +151,7 @@ let Latency = 2 in {
def : WriteRes<WriteFSGNJ64, [XSPipeGroupFALU]>;
}
-let Latency = 2 in {
+let Latency = 3 in {
def : WriteRes<WriteFMul32, [XSPipeGroupFMA]>;
def : WriteRes<WriteFMul64, [XSPipeGroupFMA]>;
def : WriteRes<WriteFMA32, [XSPipeGroupFMA]>;
@@ -154,34 +160,34 @@ let Latency = 2 in {
// FDIV
let Latency = 10 in {
- def : WriteRes<WriteFDiv32, [XSPipeFEX3]>;
- def : WriteRes<WriteFSqrt32, [XSPipeFEX3]>;
+ def : WriteRes<WriteFDiv32, [XSPipeGroupFDIV]>;
+ def : WriteRes<WriteFSqrt32, [XSPipeGroupFDIV]>;
}
let Latency = 15 in {
- def : WriteRes<WriteFDiv64, [XSPipeFEX3]>;
- def : WriteRes<WriteFSqrt64, [XSPipeFEX3]>;
+ def : WriteRes<WriteFDiv64, [XSPipeGroupFDIV]>;
+ def : WriteRes<WriteFSqrt64, [XSPipeGroupFDIV]>;
}
// FCVT
-let Latency = 3 in {
- def : WriteRes<WriteFCvtF32ToI32, [XSPipeFEX1]>;
- def : WriteRes<WriteFCvtF32ToI64, [XSPipeFEX1]>;
- def : WriteRes<WriteFCvtF64ToI32, [XSPipeFEX1]>;
- def : WriteRes<WriteFCvtF64ToI64, [XSPipeFEX1]>;
- def : WriteRes<WriteFCvtF64ToF32, [XSPipeFEX1]>;
- def : WriteRes<WriteFCvtF32ToF64, [XSPipeFEX1]>;
- def : WriteRes<WriteFMovF64ToI64, [XSPipeFEX1]>;
- def : WriteRes<WriteFMovF32ToI32, [XSPipeFEX1]>;
+let Latency = 2 in {
+ def : WriteRes<WriteFCvtF32ToI32, [XSPipeFEX0]>;
+ def : WriteRes<WriteFCvtF32ToI64, [XSPipeFEX0]>;
+ def : WriteRes<WriteFCvtF64ToI32, [XSPipeFEX0]>;
+ def : WriteRes<WriteFCvtF64ToI64, [XSPipeFEX0]>;
+ def : WriteRes<WriteFCvtF64ToF32, [XSPipeFEX0]>;
+ def : WriteRes<WriteFCvtF32ToF64, [XSPipeFEX0]>;
+ def : WriteRes<WriteFMovF64ToI64, [XSPipeFEX0]>;
+ def : WriteRes<WriteFMovF32ToI32, [XSPipeFEX0]>;
}
// I2V
-let Latency = 1 in {
+let Latency = 0 in {
def : WriteRes<WriteFMovI64ToF64, [XSPipeBJU2]>;
def : WriteRes<WriteFMovI32ToF32, [XSPipeBJU2]>;
}
// I2F
-let Latency = 3 in {
+let Latency = 2 in {
def : WriteRes<WriteFCvtI32ToF32, [XSPipeBJU2]>;
def : WriteRes<WriteFCvtI64ToF32, [XSPipeBJU2]>;
def : WriteRes<WriteFCvtI32ToF64, [XSPipeBJU2]>;
@@ -216,7 +222,7 @@ let Latency = 1 in {
def : WriteRes<WriteZIP, [XSPipeGroupALU]>;
}
-let Latency = 3 in {
+let Latency = 2 in {
// Zbb
def : WriteRes<WriteCLZ, [XSPipeGroupBKU]>;
def : WriteRes<WriteCLZ32, [XSPipeGroupBKU]>;
@@ -233,7 +239,7 @@ let Latency = 3 in {
}
// Others
-def : WriteRes<WriteCSR, [XSPipeBJU2]>;
+def : WriteRes<WriteCSR, [XSPipeBJU3]>;
def : WriteRes<WriteNop, []>;
def : InstRW<[WriteIALU], (instrs COPY)>;
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/bitmanip.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/bitmanip.s
new file mode 100644
index 0000000000000..924fc43a59df1
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/bitmanip.s
@@ -0,0 +1,179 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -mattr=+zba,+zbb,+zbs -iterations=1 < %s | FileCheck %s
+
+sh1add a0, a1, a2
+sh2add a0, a1, a2
+sh3add a0, a1, a2
+sh1add.uw a0, a1, a2
+sh2add.uw a0, a1, a2
+sh3add.uw a0, a1, a2
+add.uw a0, a1, a2
+slli.uw a0, a1, 1
+
+clz a0, a1
+clzw a0, a1
+ctz a0, a1
+ctzw a0, a1
+cpop a0, a1
+cpopw a0, a1
+
+andn a0, a1, a2
+orn a0, a1, a2
+xnor a0, a1, a2
+
+rol a0, a1, a2
+rolw a0, a1, a2
+ror a0, a1, a2
+rorw a0, a1, a2
+rori a0, a1, 1
+roriw a0, a1, 1
+
+min a0, a1, a2
+minu a0, a1, a2
+max a0, a1, a2
+maxu a0, a1, a2
+
+sext.b a0, a1
+sext.h a0, a1
+zext.h a0, a1
+
+rev8 a0, a1
+orc.b a0, a1
+
+bclr a0, a1, a2
+bclri a0, a1, 1
+bext a0, a1, a2
+bexti a0, a1, 1
+binv a0, a1, a2
+binvi a0, a1, 1
+bset a0, a1, a2
+bseti a0, a1, 1
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 40
+# CHECK-NEXT: Total Cycles: 13
+# CHECK-NEXT: Total uOps: 40
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 3.08
+# CHECK-NEXT: IPC: 3.08
+# CHECK-NEXT: Block RThroughput: 8.5
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 sh1add a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 sh2add a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 sh3add a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 sh1add.uw a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 sh2add.uw a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 sh3add.uw a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 add.uw a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 slli.uw a0, a1, 1
+# CHECK-NEXT: 1 2 0.50 clz a0, a1
+# CHECK-NEXT: 1 2 0.50 clzw a0, a1
+# CHECK-NEXT: 1 2 0.50 ctz a0, a1
+# CHECK-NEXT: 1 2 0.50 ctzw a0, a1
+# CHECK-NEXT: 1 2 0.50 cpop a0, a1
+# CHECK-NEXT: 1 2 0.50 cpopw a0, a1
+# CHECK-NEXT: 1 1 0.25 andn a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 orn a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 xnor a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 rol a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 rolw a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 ror a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 rorw a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 rori a0, a1, 1
+# CHECK-NEXT: 1 1 0.25 roriw a0, a1, 1
+# CHECK-NEXT: 1 1 0.25 min a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 minu a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 max a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 maxu a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 sext.b a0, a1
+# CHECK-NEXT: 1 1 0.25 sext.h a0, a1
+# CHECK-NEXT: 1 1 0.25 zext.h a0, a1
+# CHECK-NEXT: 1 1 0.25 rev8 a0, a1
+# CHECK-NEXT: 1 1 0.25 orc.b a0, a1
+# CHECK-NEXT: 1 1 0.25 bclr a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 bclri a0, a1, 1
+# CHECK-NEXT: 1 1 0.25 bext a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 bexti a0, a1, 1
+# CHECK-NEXT: 1 1 0.25 binv a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 binvi a0, a1, 1
+# CHECK-NEXT: 1 1 0.25 bset a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 bseti a0, a1, 1
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: 10.00 10.00 10.00 10.00 - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - sh1add a0, a1, a2
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - sh2add a0, a1, a2
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - sh3add a0, a1, a2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - sh1add.uw a0, a1, a2
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - sh2add.uw a0, a1, a2
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - sh3add.uw a0, a1, a2
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - add.uw a0, a1, a2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - slli.uw a0, a1, 1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - clz a0, a1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - clzw a0, a1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - ctz a0, a1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - ctzw a0, a1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - cpop a0, a1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - cpopw a0, a1
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - andn a0, a1, a2
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - orn a0, a1, a2
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - xnor a0, a1, a2
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - rol a0, a1, a2
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - rolw a0, a1, a2
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - ror a0, a1, a2
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - rorw a0, a1, a2
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - rori a0, a1, 1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - roriw a0, a1, 1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - min a0, a1, a2
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - minu a0, a1, a2
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - max a0, a1, a2
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - maxu a0, a1, a2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - sext.b a0, a1
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - sext.h a0, a1
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - zext.h a0, a1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - rev8 a0, a1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - orc.b a0, a1
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - bclr a0, a1, a2
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - bclri a0, a1, 1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - bext a0, a1, a2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - bexti a0, a1, 1
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - binv a0, a1, a2
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - binvi a0, a1, 1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - bset a0, a1, a2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - bseti a0, a1, 1
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/branch.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/branch.s
new file mode 100644
index 0000000000000..d153cecf582b4
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/branch.s
@@ -0,0 +1,84 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -iterations=1 < %s | FileCheck %s
+
+j 1f
+1:
+jr ra
+
+beq a0, a1, 1f
+1:
+bne a0, a1, 1f
+1:
+blt a0, a1, 1f
+1:
+bge a0, a1, 1f
+1:
+bltu a0, a1, 1f
+1:
+bgeu a0, a1, 1f
+1:
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 8
+# CHECK-NEXT: Total Cycles: 6
+# CHECK-NEXT: Total uOps: 8
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 1.33
+# CHECK-NEXT: IPC: 1.33
+# CHECK-NEXT: Block RThroughput: 2.7
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.33 j .Ltmp0
+# CHECK-NEXT: 1 1 0.33 ret
+# CHECK-NEXT: 1 1 0.33 beq a0, a1, .Ltmp1
+# CHECK-NEXT: 1 1 0.33 bne a0, a1, .Ltmp2
+# CHECK-NEXT: 1 1 0.33 blt a0, a1, .Ltmp3
+# CHECK-NEXT: 1 1 0.33 bge a0, a1, .Ltmp4
+# CHECK-NEXT: 1 1 0.33 bltu a0, a1, .Ltmp5
+# CHECK-NEXT: 1 1 0.33 bgeu a0, a1, .Ltmp6
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: - - - - 2.00 3.00 3.00 - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - j .Ltmp0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - - ret
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - beq a0, a1, .Ltmp1
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - bne a0, a1, .Ltmp2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - - blt a0, a1, .Ltmp3
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - bge a0, a1, .Ltmp4
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - bltu a0, a1, .Ltmp5
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - - bgeu a0, a1, .Ltmp6
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/cascade-fma.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/cascade-fma.s
new file mode 100644
index 0000000000000..c7cf24ab0016f
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/cascade-fma.s
@@ -0,0 +1,55 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu < %s | FileCheck %s
+
+fmadd.s fa0, fa1, fa2, fa0
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 100
+# CHECK-NEXT: Total Cycles: 303
+# CHECK-NEXT: Total uOps: 100
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 0.33
+# CHECK-NEXT: IPC: 0.33
+# CHECK-NEXT: Block RThroughput: 0.3
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.33 fmadd.s fa0, fa1, fa2, fa0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.34 - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.34 - - - - - - - fmadd.s fa0, fa1, fa2, fa0
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/div-fdiv.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/div-fdiv.s
new file mode 100644
index 0000000000000..ad6a54bd28e26
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/div-fdiv.s
@@ -0,0 +1,119 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -timeline -iterations=1 < %s | FileCheck %s
+
+div a0, a1, a2
+divu a0, a1, a2
+divw a0, a1, a2
+divuw a0, a1, a2
+rem a0, a1, a2
+remu a0, a1, a2
+remw a0, a1, a2
+remuw a0, a1, a2
+
+fdiv.s fa0, fa1, fa2
+fdiv.d fa0, fa1, fa2
+fsqrt.s fa0, fa1
+fsqrt.d fa0, fa1
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 12
+# CHECK-NEXT: Total Cycles: 163
+# CHECK-NEXT: Total uOps: 12
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 0.07
+# CHECK-NEXT: IPC: 0.07
+# CHECK-NEXT: Block RThroughput: 160.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 20 20.00 div a0, a1, a2
+# CHECK-NEXT: 1 20 20.00 divu a0, a1, a2
+# CHECK-NEXT: 1 20 20.00 divw a0, a1, a2
+# CHECK-NEXT: 1 20 20.00 divuw a0, a1, a2
+# CHECK-NEXT: 1 20 20.00 rem a0, a1, a2
+# CHECK-NEXT: 1 20 20.00 remu a0, a1, a2
+# CHECK-NEXT: 1 20 20.00 remw a0, a1, a2
+# CHECK-NEXT: 1 20 20.00 remuw a0, a1, a2
+# CHECK-NEXT: 1 10 0.50 fdiv.s fa0, fa1, fa2
+# CHECK-NEXT: 1 15 0.50 fdiv.d fa0, fa1, fa2
+# CHECK-NEXT: 1 10 0.50 fsqrt.s fa0, fa1
+# CHECK-NEXT: 1 15 0.50 fsqrt.d fa0, fa1
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: - - - - - - - 160.00 - 2.00 - 2.00 - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - - - - - - - 20.00 - - - - - - - - - - - - div a0, a1, a2
+# CHECK-NEXT: - - - - - - - 20.00 - - - - - - - - - - - - divu a0, a1, a2
+# CHECK-NEXT: - - - - - - - 20.00 - - - - - - - - - - - - divw a0, a1, a2
+# CHECK-NEXT: - - - - - - - 20.00 - - - - - - - - - - - - divuw a0, a1, a2
+# CHECK-NEXT: - - - - - - - 20.00 - - - - - - - - - - - - rem a0, a1, a2
+# CHECK-NEXT: - - - - - - - 20.00 - - - - - - - - - - - - remu a0, a1, a2
+# CHECK-NEXT: - - - - - - - 20.00 - - - - - - - - - - - - remw a0, a1, a2
+# CHECK-NEXT: - - - - - - - 20.00 - - - - - - - - - - - - remuw a0, a1, a2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - fdiv.s fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - fdiv.d fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - fsqrt.s fa0, fa1
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - fsqrt.d fa0, fa1
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789 0123456789 0123456789
+# CHECK-NEXT: Index 0123456789 0123456789 0123456789 012
+
+# CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeeER . . . . . . . . . div a0, a1, a2
+# CHECK-NEXT: [0,1] D====================eeeeeeeeeeeeeeeeeeeeER . . . . . divu a0, a1, a2
+# CHECK-NEXT: [0,2] D========================================eeeeeeeeeeeeeeeeeeeeER divw a0, a1, a2
+# CHECK-NEXT: Truncated display due to cycle limit
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 div a0, a1, a2
+# CHECK-NEXT: 1. 1 21.0 21.0 0.0 divu a0, a1, a2
+# CHECK-NEXT: 2. 1 41.0 41.0 0.0 divw a0, a1, a2
+# CHECK-NEXT: 3. 1 61.0 61.0 0.0 divuw a0, a1, a2
+# CHECK-NEXT: 4. 1 81.0 81.0 0.0 rem a0, a1, a2
+# CHECK-NEXT: 5. 1 101.0 101.0 0.0 remu a0, a1, a2
+# CHECK-NEXT: 6. 1 120.0 120.0 0.0 remw a0, a1, a2
+# CHECK-NEXT: 7. 1 140.0 140.0 0.0 remuw a0, a1, a2
+# CHECK-NEXT: 8. 1 1.0 1.0 149.0 fdiv.s fa0, fa1, fa2
+# CHECK-NEXT: 9. 1 1.0 1.0 144.0 fdiv.d fa0, fa1, fa2
+# CHECK-NEXT: 10. 1 2.0 2.0 148.0 fsqrt.s fa0, fa1
+# CHECK-NEXT: 11. 1 2.0 2.0 143.0 fsqrt.d fa0, fa1
+# CHECK-NEXT: 1 47.7 47.7 48.7 <total>
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/fpr-bypass.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/fpr-bypass.s
new file mode 100644
index 0000000000000..b850d3526e870
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/fpr-bypass.s
@@ -0,0 +1,250 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -iterations=1 < %s | FileCheck %s
+
+fadd.s fa0, fa1, fa2
+fadd.d fa0, fa1, fa2
+fsub.s fa0, fa1, fa2
+fsub.d fa0, fa1, fa2
+
+fmul.s fa0, fa1, fa2
+fmul.d fa0, fa1, fa2
+
+fdiv.s fa0, fa1, fa2
+fdiv.d fa0, fa1, fa2
+fsqrt.s fa0, fa1
+fsqrt.d fa0, fa1
+
+fmadd.s fa0, fa1, fa2, fa3
+fmadd.d fa0, fa1, fa2, fa3
+fmsub.s fa0, fa1, fa2, fa3
+fmsub.d fa0, fa1, fa2, fa3
+fnmadd.s fa0, fa1, fa2, fa3
+fnmadd.d fa0, fa1, fa2, fa3
+fnmsub.s fa0, fa1, fa2, fa3
+fnmsub.d fa0, fa1, fa2, fa3
+
+feq.s a0, fa1, fa2
+feq.d a0, fa1, fa2
+flt.s a0, fa1, fa2
+flt.d a0, fa1, fa2
+fle.s a0, fa1, fa2
+fle.d a0, fa1, fa2
+
+fmin.s fa0, fa1, fa2
+fmin.d fa0, fa1, fa2
+fmax.s fa0, fa1, fa2
+fmax.d fa0, fa1, fa2
+
+fsgnj.s fa0, fa1, fa2
+fsgnj.d fa0, fa1, fa2
+fsgnjn.s fa0, fa1, fa2
+fsgnjn.d fa0, fa1, fa2
+fsgnjx.s fa0, fa1, fa2
+fsgnjx.d fa0, fa1, fa2
+
+fmv.x.w a0, fa0
+fmv.x.d a0, fa0
+fmv.w.x fa0, a0
+fmv.d.x fa0, a0
+
+fcvt.s.w fa0, a0
+fcvt.s.wu fa0, a0
+fcvt.s.l fa0, a0
+fcvt.s.lu fa0, a0
+fcvt.d.w fa0, a0
+fcvt.d.wu fa0, a0
+fcvt.d.l fa0, a0
+fcvt.d.lu fa0, a0
+
+fcvt.w.s a0, fa0
+fcvt.wu.s a0, fa0
+fcvt.l.s a0, fa0
+fcvt.lu.s a0, fa0
+fcvt.w.d a0, fa0
+fcvt.wu.d a0, fa0
+fcvt.l.d a0, fa0
+fcvt.lu.d a0, fa0
+
+fcvt.s.d fa0, fa1
+fcvt.d.s fa0, fa1
+
+fclass.s a0, fa0
+fclass.d a0, fa0
+
+flw fa0, 0(a0)
+fld fa0, 0(a0)
+fsw fa0, 0(a0)
+fsd fa0, 0(a0)
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 62
+# CHECK-NEXT: Total Cycles: 29
+# CHECK-NEXT: Total uOps: 62
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 2.14
+# CHECK-NEXT: IPC: 2.14
+# CHECK-NEXT: Block RThroughput: 12.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.33 fadd.s fa0, fa1, fa2
+# CHECK-NEXT: 1 1 0.33 fadd.d fa0, fa1, fa2
+# CHECK-NEXT: 1 1 0.33 fsub.s fa0, fa1, fa2
+# CHECK-NEXT: 1 1 0.33 fsub.d fa0, fa1, fa2
+# CHECK-NEXT: 1 3 0.33 fmul.s fa0, fa1, fa2
+# CHECK-NEXT: 1 3 0.33 fmul.d fa0, fa1, fa2
+# CHECK-NEXT: 1 10 0.50 fdiv.s fa0, fa1, fa2
+# CHECK-NEXT: 1 15 0.50 fdiv.d fa0, fa1, fa2
+# CHECK-NEXT: 1 10 0.50 fsqrt.s fa0, fa1
+# CHECK-NEXT: 1 15 0.50 fsqrt.d fa0, fa1
+# CHECK-NEXT: 1 3 0.33 fmadd.s fa0, fa1, fa2, fa3
+# CHECK-NEXT: 1 3 0.33 fmadd.d fa0, fa1, fa2, fa3
+# CHECK-NEXT: 1 3 0.33 fmsub.s fa0, fa1, fa2, fa3
+# CHECK-NEXT: 1 3 0.33 fmsub.d fa0, fa1, fa2, fa3
+# CHECK-NEXT: 1 3 0.33 fnmadd.s fa0, fa1, fa2, fa3
+# CHECK-NEXT: 1 3 0.33 fnmadd.d fa0, fa1, fa2, fa3
+# CHECK-NEXT: 1 3 0.33 fnmsub.s fa0, fa1, fa2, fa3
+# CHECK-NEXT: 1 3 0.33 fnmsub.d fa0, fa1, fa2, fa3
+# CHECK-NEXT: 1 2 0.33 feq.s a0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 feq.d a0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 flt.s a0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 flt.d a0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 fle.s a0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 fle.d a0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 fmin.s fa0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 fmin.d fa0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 fmax.s fa0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 fmax.d fa0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 fsgnj.s fa0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 fsgnj.d fa0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 fsgnjn.s fa0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 fsgnjn.d fa0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 fsgnjx.s fa0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 fsgnjx.d fa0, fa1, fa2
+# CHECK-NEXT: 1 2 1.00 fmv.x.w a0, fa0
+# CHECK-NEXT: 1 2 1.00 fmv.x.d a0, fa0
+# CHECK-NEXT: 1 0 1.00 fmv.w.x fa0, a0
+# CHECK-NEXT: 1 0 1.00 fmv.d.x fa0, a0
+# CHECK-NEXT: 1 2 1.00 fcvt.s.w fa0, a0
+# CHECK-NEXT: 1 2 1.00 fcvt.s.wu fa0, a0
+# CHECK-NEXT: 1 2 1.00 fcvt.s.l fa0, a0
+# CHECK-NEXT: 1 2 1.00 fcvt.s.lu fa0, a0
+# CHECK-NEXT: 1 2 1.00 fcvt.d.w fa0, a0
+# CHECK-NEXT: 1 2 1.00 fcvt.d.wu fa0, a0
+# CHECK-NEXT: 1 2 1.00 fcvt.d.l fa0, a0
+# CHECK-NEXT: 1 2 1.00 fcvt.d.lu fa0, a0
+# CHECK-NEXT: 1 2 1.00 fcvt.w.s a0, fa0
+# CHECK-NEXT: 1 2 1.00 fcvt.wu.s a0, fa0
+# CHECK-NEXT: 1 2 1.00 fcvt.l.s a0, fa0
+# CHECK-NEXT: 1 2 1.00 fcvt.lu.s a0, fa0
+# CHECK-NEXT: 1 2 1.00 fcvt.w.d a0, fa0
+# CHECK-NEXT: 1 2 1.00 fcvt.wu.d a0, fa0
+# CHECK-NEXT: 1 2 1.00 fcvt.l.d a0, fa0
+# CHECK-NEXT: 1 2 1.00 fcvt.lu.d a0, fa0
+# CHECK-NEXT: 1 2 1.00 fcvt.s.d fa0, fa1
+# CHECK-NEXT: 1 2 1.00 fcvt.d.s fa0, fa1
+# CHECK-NEXT: 1 2 0.33 fclass.s a0, fa0
+# CHECK-NEXT: 1 2 0.33 fclass.d a0, fa0
+# CHECK-NEXT: 1 6 0.33 * flw fa0, 0(a0)
+# CHECK-NEXT: 1 6 0.33 * fld fa0, 0(a0)
+# CHECK-NEXT: 1 4 0.25 * fsw fa0, 0(a0)
+# CHECK-NEXT: 1 4 0.25 * fsd fa0, 0(a0)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: - - - - - - 10.00 - 22.00 2.00 11.00 2.00 11.00 - 1.00 1.00 - - 1.00 1.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fadd.s fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fadd.d fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fsub.s fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fsub.d fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fmul.s fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fmul.d fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - fdiv.s fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - fdiv.d fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - fsqrt.s fa0, fa1
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - fsqrt.d fa0, fa1
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fmadd.s fa0, fa1, fa2, fa3
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fmadd.d fa0, fa1, fa2, fa3
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fmsub.s fa0, fa1, fa2, fa3
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fmsub.d fa0, fa1, fa2, fa3
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fnmadd.s fa0, fa1, fa2, fa3
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fnmadd.d fa0, fa1, fa2, fa3
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fnmsub.s fa0, fa1, fa2, fa3
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fnmsub.d fa0, fa1, fa2, fa3
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - feq.s a0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - feq.d a0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - flt.s a0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - flt.d a0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fle.s a0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fle.d a0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fmin.s fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fmin.d fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fmax.s fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fmax.d fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fsgnj.s fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fsgnj.d fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fsgnjn.s fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fsgnjn.d fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fsgnjx.s fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fsgnjx.d fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fmv.x.w a0, fa0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fmv.x.d a0, fa0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fmv.w.x fa0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fmv.d.x fa0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.s.w fa0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.s.wu fa0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.s.l fa0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.s.lu fa0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.d.w fa0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.d.wu fa0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.d.l fa0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.d.lu fa0, a0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.w.s a0, fa0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.wu.s a0, fa0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.l.s a0, fa0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.lu.s a0, fa0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.w.d a0, fa0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.wu.d a0, fa0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.l.d a0, fa0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.lu.d a0, fa0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.s.d fa0, fa1
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.d.s fa0, fa1
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fclass.s a0, fa0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fclass.d a0, fa0
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - flw fa0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - - - - fld fa0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 fsw fa0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 - fsd fa0, 0(a0)
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/gpr-bypass.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/gpr-bypass.s
new file mode 100644
index 0000000000000..ce6b171f54c78
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/gpr-bypass.s
@@ -0,0 +1,353 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -timeline \
+# RUN: -timeline-max-cycles=1000 -iterations=1 < %s | FileCheck %s
+
+lui a0, 1
+auipc a1, 1
+
+add a0, a0, a1
+addi a0, a0, 1
+addw a0, a0, a0
+addiw a0, a0, 1
+
+sub a0, a0, a0
+subw a0, a0, a0
+
+and a0, a0, a1
+andi a0, a0, 1
+or a0, a0, a1
+ori a0, a0, 1
+xor a0, a0, a1
+xori a0, a0, 1
+
+sll a0, a0, a1
+slli a0, a0, 1
+sllw a0, a0, a1
+slliw a0, a0, 1
+srl a0, a0, a1
+srli a0, a0, 1
+srlw a0, a0, a1
+srliw a0, a0, 1
+sra a0, a0, a1
+srai a0, a0, 1
+sraw a0, a0, a1
+sraiw a0, a0, 1
+
+slt a0, a0, a1
+slti a0, a0, 1
+sltu a0, a0, a1
+sltiu a0, a0, 1
+
+mul a0, a0, a1
+mulh a0, a0, a1
+mulhsu a0, a0, a1
+mulhu a0, a0, a1
+mulw a0, a0, a1
+
+j 1f
+1:
+jr ra
+beq a0, a1, 1f
+1:
+bne a0, a1, 1f
+1:
+blt a0, a1, 1f
+1:
+bge a0, a1, 1f
+1:
+bltu a0, a1, 1f
+1:
+bgeu a0, a1, 1f
+1:
+
+lb a0, 0(a1)
+lh a0, 0(a1)
+lw a0, 0(a1)
+ld a0, 0(a1)
+lbu a0, 0(a1)
+lhu a0, 0(a1)
+lwu a0, 0(a1)
+
+sb a0, 0(a1)
+sh a0, 0(a1)
+sw a0, 0(a1)
+sd a0, 0(a1)
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 54
+# CHECK-NEXT: Total Cycles: 44
+# CHECK-NEXT: Total uOps: 54
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 1.23
+# CHECK-NEXT: IPC: 1.23
+# CHECK-NEXT: Block RThroughput: 9.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 lui a0, 1
+# CHECK-NEXT: 1 1 0.25 auipc a1, 1
+# CHECK-NEXT: 1 1 0.25 add a0, a0, a1
+# CHECK-NEXT: 1 1 0.25 addi a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 addw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 addiw a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 sub a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 subw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 and a0, a0, a1
+# CHECK-NEXT: 1 1 0.25 andi a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 or a0, a0, a1
+# CHECK-NEXT: 1 1 0.25 ori a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 xor a0, a0, a1
+# CHECK-NEXT: 1 1 0.25 xori a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 sll a0, a0, a1
+# CHECK-NEXT: 1 1 0.25 slli a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 sllw a0, a0, a1
+# CHECK-NEXT: 1 1 0.25 slliw a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 srl a0, a0, a1
+# CHECK-NEXT: 1 1 0.25 srli a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 srlw a0, a0, a1
+# CHECK-NEXT: 1 1 0.25 srliw a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 sra a0, a0, a1
+# CHECK-NEXT: 1 1 0.25 srai a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 sraw a0, a0, a1
+# CHECK-NEXT: 1 1 0.25 sraiw a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 slt a0, a0, a1
+# CHECK-NEXT: 1 1 0.25 slti a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 sltu a0, a0, a1
+# CHECK-NEXT: 1 1 0.25 seqz a0, a0
+# CHECK-NEXT: 1 2 0.50 mul a0, a0, a1
+# CHECK-NEXT: 1 2 0.50 mulh a0, a0, a1
+# CHECK-NEXT: 1 2 0.50 mulhsu a0, a0, a1
+# CHECK-NEXT: 1 2 0.50 mulhu a0, a0, a1
+# CHECK-NEXT: 1 2 0.50 mulw a0, a0, a1
+# CHECK-NEXT: 1 1 0.33 j .Ltmp0
+# CHECK-NEXT: 1 1 0.33 ret
+# CHECK-NEXT: 1 1 0.33 beq a0, a1, .Ltmp1
+# CHECK-NEXT: 1 1 0.33 bne a0, a1, .Ltmp2
+# CHECK-NEXT: 1 1 0.33 blt a0, a1, .Ltmp3
+# CHECK-NEXT: 1 1 0.33 bge a0, a1, .Ltmp4
+# CHECK-NEXT: 1 1 0.33 bltu a0, a1, .Ltmp5
+# CHECK-NEXT: 1 1 0.33 bgeu a0, a1, .Ltmp6
+# CHECK-NEXT: 1 6 0.33 * lb a0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * lh a0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * lw a0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * ld a0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * lbu a0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * lhu a0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * lwu a0, 0(a1)
+# CHECK-NEXT: 1 4 0.25 * sb a0, 0(a1)
+# CHECK-NEXT: 1 4 0.25 * sh a0, 0(a1)
+# CHECK-NEXT: 1 4 0.25 * sw a0, 0(a1)
+# CHECK-NEXT: 1 4 0.25 * sd a0, 0(a1)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: 9.00 10.00 8.00 8.00 2.00 3.00 3.00 - - - - - - 2.00 2.00 3.00 1.00 1.00 1.00 1.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - lui a0, 1
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - auipc a1, 1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - add a0, a0, a1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - addi a0, a0, 1
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - addw a0, a0, a0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - addiw a0, a0, 1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - sub a0, a0, a0
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - subw a0, a0, a0
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - and a0, a0, a1
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - andi a0, a0, 1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - or a0, a0, a1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - ori a0, a0, 1
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - xor a0, a0, a1
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - xori a0, a0, 1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - sll a0, a0, a1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - slli a0, a0, 1
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - sllw a0, a0, a1
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - slliw a0, a0, 1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - srl a0, a0, a1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - srli a0, a0, 1
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - srlw a0, a0, a1
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - srliw a0, a0, 1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - sra a0, a0, a1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - srai a0, a0, 1
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - sraw a0, a0, a1
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - sraiw a0, a0, 1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - slt a0, a0, a1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - slti a0, a0, 1
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - sltu a0, a0, a1
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - seqz a0, a0
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - mul a0, a0, a1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - mulh a0, a0, a1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - mulhsu a0, a0, a1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - mulhu a0, a0, a1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - mulw a0, a0, a1
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - j .Ltmp0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - - ret
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - beq a0, a1, .Ltmp1
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - bne a0, a1, .Ltmp2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - - blt a0, a1, .Ltmp3
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - bge a0, a1, .Ltmp4
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - bltu a0, a1, .Ltmp5
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - - bgeu a0, a1, .Ltmp6
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - - - - lb a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - lh a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - - - - lw a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - ld a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - - - - lbu a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - - - - lhu a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - - - - lwu a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 sb a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 - sh a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - sw a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - sd a0, 0(a1)
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789 0123456789
+# CHECK-NEXT: Index 0123456789 0123456789 0123
+
+# CHECK: [0,0] DeER . . . . . . . . . lui a0, 1
+# CHECK-NEXT: [0,1] DeER . . . . . . . . . auipc a1, 1
+# CHECK-NEXT: [0,2] D=eER. . . . . . . . . add a0, a0, a1
+# CHECK-NEXT: [0,3] D==eER . . . . . . . . addi a0, a0, 1
+# CHECK-NEXT: [0,4] D===eER . . . . . . . . addw a0, a0, a0
+# CHECK-NEXT: [0,5] D====eER . . . . . . . . addiw a0, a0, 1
+# CHECK-NEXT: [0,6] .D====eER . . . . . . . . sub a0, a0, a0
+# CHECK-NEXT: [0,7] .D=====eER. . . . . . . . subw a0, a0, a0
+# CHECK-NEXT: [0,8] .D======eER . . . . . . . and a0, a0, a1
+# CHECK-NEXT: [0,9] .D=======eER . . . . . . . andi a0, a0, 1
+# CHECK-NEXT: [0,10] .D========eER . . . . . . . or a0, a0, a1
+# CHECK-NEXT: [0,11] .D=========eER . . . . . . . ori a0, a0, 1
+# CHECK-NEXT: [0,12] . D=========eER. . . . . . . xor a0, a0, a1
+# CHECK-NEXT: [0,13] . D==========eER . . . . . . xori a0, a0, 1
+# CHECK-NEXT: [0,14] . D===========eER . . . . . . sll a0, a0, a1
+# CHECK-NEXT: [0,15] . D============eER . . . . . . slli a0, a0, 1
+# CHECK-NEXT: [0,16] . D=============eER . . . . . . sllw a0, a0, a1
+# CHECK-NEXT: [0,17] . D==============eER. . . . . . slliw a0, a0, 1
+# CHECK-NEXT: [0,18] . D==============eER . . . . . srl a0, a0, a1
+# CHECK-NEXT: [0,19] . D===============eER . . . . . srli a0, a0, 1
+# CHECK-NEXT: [0,20] . D================eER . . . . . srlw a0, a0, a1
+# CHECK-NEXT: [0,21] . D=================eER . . . . . srliw a0, a0, 1
+# CHECK-NEXT: [0,22] . D==================eER. . . . . sra a0, a0, a1
+# CHECK-NEXT: [0,23] . D===================eER . . . . srai a0, a0, 1
+# CHECK-NEXT: [0,24] . D===================eER . . . . sraw a0, a0, a1
+# CHECK-NEXT: [0,25] . D====================eER . . . . sraiw a0, a0, 1
+# CHECK-NEXT: [0,26] . D=====================eER . . . . slt a0, a0, a1
+# CHECK-NEXT: [0,27] . D======================eER. . . . slti a0, a0, 1
+# CHECK-NEXT: [0,28] . D=======================eER . . . sltu a0, a0, a1
+# CHECK-NEXT: [0,29] . D========================eER . . . seqz a0, a0
+# CHECK-NEXT: [0,30] . D========================eeER . . . mul a0, a0, a1
+# CHECK-NEXT: [0,31] . D==========================eeER . . mulh a0, a0, a1
+# CHECK-NEXT: [0,32] . D============================eeER . . mulhsu a0, a0, a1
+# CHECK-NEXT: [0,33] . D==============================eeER. . mulhu a0, a0, a1
+# CHECK-NEXT: [0,34] . D================================eeER . mulw a0, a0, a1
+# CHECK-NEXT: [0,35] . DeE---------------------------------R . j .Ltmp0
+# CHECK-NEXT: [0,36] . .DeE--------------------------------R . ret
+# CHECK-NEXT: [0,37] . .D=================================eER. beq a0, a1, .Ltmp1
+# CHECK-NEXT: [0,38] . .D=================================eER. bne a0, a1, .Ltmp2
+# CHECK-NEXT: [0,39] . .D=================================eER. blt a0, a1, .Ltmp3
+# CHECK-NEXT: [0,40] . .D==================================eER bge a0, a1, .Ltmp4
+# CHECK-NEXT: [0,41] . .D==================================eER bltu a0, a1, .Ltmp5
+# CHECK-NEXT: [0,42] . . D=================================eER bgeu a0, a1, .Ltmp6
+# CHECK-NEXT: [0,43] . . DeeeeeeE----------------------------R lb a0, 0(a1)
+# CHECK-NEXT: [0,44] . . DeeeeeeE----------------------------R lh a0, 0(a1)
+# CHECK-NEXT: [0,45] . . DeeeeeeE----------------------------R lw a0, 0(a1)
+# CHECK-NEXT: [0,46] . . D=eeeeeeE---------------------------R ld a0, 0(a1)
+# CHECK-NEXT: [0,47] . . D=eeeeeeE---------------------------R lbu a0, 0(a1)
+# CHECK-NEXT: [0,48] . . D=eeeeeeE--------------------------R lhu a0, 0(a1)
+# CHECK-NEXT: [0,49] . . DeeeeeeE---------------------------R lwu a0, 0(a1)
+# CHECK-NEXT: [0,50] . . D======eeeeE-----------------------R sb a0, 0(a1)
+# CHECK-NEXT: [0,51] . . D======eeeeE-----------------------R sh a0, 0(a1)
+# CHECK-NEXT: [0,52] . . D======eeeeE-----------------------R sw a0, 0(a1)
+# CHECK-NEXT: [0,53] . . D======eeeeE-----------------------R sd a0, 0(a1)
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 lui a0, 1
+# CHECK-NEXT: 1. 1 1.0 1.0 0.0 auipc a1, 1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 add a0, a0, a1
+# CHECK-NEXT: 3. 1 3.0 0.0 0.0 addi a0, a0, 1
+# CHECK-NEXT: 4. 1 4.0 0.0 0.0 addw a0, a0, a0
+# CHECK-NEXT: 5. 1 5.0 0.0 0.0 addiw a0, a0, 1
+# CHECK-NEXT: 6. 1 5.0 0.0 0.0 sub a0, a0, a0
+# CHECK-NEXT: 7. 1 6.0 0.0 0.0 subw a0, a0, a0
+# CHECK-NEXT: 8. 1 7.0 0.0 0.0 and a0, a0, a1
+# CHECK-NEXT: 9. 1 8.0 0.0 0.0 andi a0, a0, 1
+# CHECK-NEXT: 10. 1 9.0 0.0 0.0 or a0, a0, a1
+# CHECK-NEXT: 11. 1 10.0 0.0 0.0 ori a0, a0, 1
+# CHECK-NEXT: 12. 1 10.0 0.0 0.0 xor a0, a0, a1
+# CHECK-NEXT: 13. 1 11.0 0.0 0.0 xori a0, a0, 1
+# CHECK-NEXT: 14. 1 12.0 0.0 0.0 sll a0, a0, a1
+# CHECK-NEXT: 15. 1 13.0 0.0 0.0 slli a0, a0, 1
+# CHECK-NEXT: 16. 1 14.0 0.0 0.0 sllw a0, a0, a1
+# CHECK-NEXT: 17. 1 15.0 0.0 0.0 slliw a0, a0, 1
+# CHECK-NEXT: 18. 1 15.0 0.0 0.0 srl a0, a0, a1
+# CHECK-NEXT: 19. 1 16.0 0.0 0.0 srli a0, a0, 1
+# CHECK-NEXT: 20. 1 17.0 0.0 0.0 srlw a0, a0, a1
+# CHECK-NEXT: 21. 1 18.0 0.0 0.0 srliw a0, a0, 1
+# CHECK-NEXT: 22. 1 19.0 0.0 0.0 sra a0, a0, a1
+# CHECK-NEXT: 23. 1 20.0 0.0 0.0 srai a0, a0, 1
+# CHECK-NEXT: 24. 1 20.0 0.0 0.0 sraw a0, a0, a1
+# CHECK-NEXT: 25. 1 21.0 0.0 0.0 sraiw a0, a0, 1
+# CHECK-NEXT: 26. 1 22.0 0.0 0.0 slt a0, a0, a1
+# CHECK-NEXT: 27. 1 23.0 0.0 0.0 slti a0, a0, 1
+# CHECK-NEXT: 28. 1 24.0 0.0 0.0 sltu a0, a0, a1
+# CHECK-NEXT: 29. 1 25.0 0.0 0.0 seqz a0, a0
+# CHECK-NEXT: 30. 1 25.0 0.0 0.0 mul a0, a0, a1
+# CHECK-NEXT: 31. 1 27.0 0.0 0.0 mulh a0, a0, a1
+# CHECK-NEXT: 32. 1 29.0 0.0 0.0 mulhsu a0, a0, a1
+# CHECK-NEXT: 33. 1 31.0 0.0 0.0 mulhu a0, a0, a1
+# CHECK-NEXT: 34. 1 33.0 0.0 0.0 mulw a0, a0, a1
+# CHECK-NEXT: 35. 1 1.0 1.0 33.0 j .Ltmp0
+# CHECK-NEXT: 36. 1 1.0 1.0 32.0 ret
+# CHECK-NEXT: 37. 1 34.0 0.0 0.0 beq a0, a1, .Ltmp1
+# CHECK-NEXT: 38. 1 34.0 0.0 0.0 bne a0, a1, .Ltmp2
+# CHECK-NEXT: 39. 1 34.0 0.0 0.0 blt a0, a1, .Ltmp3
+# CHECK-NEXT: 40. 1 35.0 1.0 0.0 bge a0, a1, .Ltmp4
+# CHECK-NEXT: 41. 1 35.0 1.0 0.0 bltu a0, a1, .Ltmp5
+# CHECK-NEXT: 42. 1 34.0 1.0 0.0 bgeu a0, a1, .Ltmp6
+# CHECK-NEXT: 43. 1 1.0 1.0 28.0 lb a0, 0(a1)
+# CHECK-NEXT: 44. 1 1.0 1.0 28.0 lh a0, 0(a1)
+# CHECK-NEXT: 45. 1 1.0 1.0 28.0 lw a0, 0(a1)
+# CHECK-NEXT: 46. 1 2.0 2.0 27.0 ld a0, 0(a1)
+# CHECK-NEXT: 47. 1 2.0 2.0 27.0 lbu a0, 0(a1)
+# CHECK-NEXT: 48. 1 2.0 2.0 26.0 lhu a0, 0(a1)
+# CHECK-NEXT: 49. 1 1.0 1.0 27.0 lwu a0, 0(a1)
+# CHECK-NEXT: 50. 1 7.0 0.0 23.0 sb a0, 0(a1)
+# CHECK-NEXT: 51. 1 7.0 0.0 23.0 sh a0, 0(a1)
+# CHECK-NEXT: 52. 1 7.0 0.0 23.0 sw a0, 0(a1)
+# CHECK-NEXT: 53. 1 7.0 0.0 23.0 sd a0, 0(a1)
+# CHECK-NEXT: 1 14.2 0.3 6.4 <total>
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-store.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-store.s
new file mode 100644
index 0000000000000..ac95fce7e614a
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-store.s
@@ -0,0 +1,100 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -iterations=1 < %s | FileCheck %s
+
+lb a0, 0(a1)
+lh a0, 0(a1)
+lw a0, 0(a1)
+ld a0, 0(a1)
+lbu a0, 0(a1)
+lhu a0, 0(a1)
+lwu a0, 0(a1)
+
+flw fa0, 0(a1)
+fld fa0, 0(a1)
+
+sb a0, 0(a1)
+sh a0, 0(a1)
+sw a0, 0(a1)
+sd a0, 0(a1)
+
+fsw fa0, 0(a1)
+fsd fa0, 0(a1)
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 15
+# CHECK-NEXT: Total Cycles: 15
+# CHECK-NEXT: Total uOps: 15
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 1.00
+# CHECK-NEXT: IPC: 1.00
+# CHECK-NEXT: Block RThroughput: 3.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 6 0.33 * lb a0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * lh a0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * lw a0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * ld a0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * lbu a0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * lhu a0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * lwu a0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * flw fa0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * fld fa0, 0(a1)
+# CHECK-NEXT: 1 4 0.25 * sb a0, 0(a1)
+# CHECK-NEXT: 1 4 0.25 * sh a0, 0(a1)
+# CHECK-NEXT: 1 4 0.25 * sw a0, 0(a1)
+# CHECK-NEXT: 1 4 0.25 * sd a0, 0(a1)
+# CHECK-NEXT: 1 4 0.25 * fsw fa0, 0(a1)
+# CHECK-NEXT: 1 4 0.25 * fsd fa0, 0(a1)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: - - - - - - - - - - - - - 3.00 3.00 3.00 1.00 1.00 2.00 2.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - - - - lb a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - lh a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - - - - lw a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - - - - ld a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - - - - lbu a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - - - - lhu a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - lwu a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - - - - flw fa0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - fld fa0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 sb a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 - sh a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - sw a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - sd a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 fsw fa0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 - fsd fa0, 0(a1)
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-alu.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-alu.s
new file mode 100644
index 0000000000000..7665598ab198e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-alu.s
@@ -0,0 +1,75 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -timeline -iterations=1 < %s | FileCheck %s
+
+ld a1, 0(a0)
+addi a2, a1, 1
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 2
+# CHECK-NEXT: Total Cycles: 9
+# CHECK-NEXT: Total uOps: 2
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 0.22
+# CHECK-NEXT: IPC: 0.22
+# CHECK-NEXT: Block RThroughput: 0.3
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 6 0.33 * ld a1, 0(a0)
+# CHECK-NEXT: 1 1 0.25 addi a2, a1, 1
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - 1.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - - - - ld a1, 0(a0)
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - addi a2, a1, 1
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 012345678
+
+# CHECK: [0,0] DeeeeeeER ld a1, 0(a0)
+# CHECK-NEXT: [0,1] D====eE-R addi a2, a1, 1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld a1, 0(a0)
+# CHECK-NEXT: 1. 1 5.0 0.0 1.0 addi a2, a1, 1
+# CHECK-NEXT: 1 3.0 0.5 0.5 <total>
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-fpu.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-fpu.s
new file mode 100644
index 0000000000000..6c3ffe9f2ff8e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-fpu.s
@@ -0,0 +1,75 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -timeline -iterations=1 < %s | FileCheck %s
+
+fld fa1, 0(a0)
+fadd.s fa2, fa1, fa3
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 2
+# CHECK-NEXT: Total Cycles: 10
+# CHECK-NEXT: Total uOps: 2
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 0.20
+# CHECK-NEXT: IPC: 0.20
+# CHECK-NEXT: Block RThroughput: 0.3
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 6 0.33 * fld fa1, 0(a0)
+# CHECK-NEXT: 1 1 0.33 fadd.s fa2, fa1, fa3
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - 1.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - - - - fld fa1, 0(a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fadd.s fa2, fa1, fa3
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeER. fld fa1, 0(a0)
+# CHECK-NEXT: [0,1] D======eER fadd.s fa2, fa1, fa3
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 fld fa1, 0(a0)
+# CHECK-NEXT: 1. 1 7.0 0.0 0.0 fadd.s fa2, fa1, fa3
+# CHECK-NEXT: 1 4.0 0.5 0.0 <total>
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/mul-fmul.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/mul-fmul.s
new file mode 100644
index 0000000000000..1b36ac96d1fa8
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/mul-fmul.s
@@ -0,0 +1,74 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -iterations=1 < %s | FileCheck %s
+
+mul a0, a1, a2
+mulh a0, a1, a2
+mulhsu a0, a1, a2
+mulhu a0, a1, a2
+mulw a0, a1, a2
+
+fmul.s fa0, fa1, fa2
+fmul.d fa0, fa1, fa2
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 7
+# CHECK-NEXT: Total Cycles: 7
+# CHECK-NEXT: Total uOps: 7
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 1.00
+# CHECK-NEXT: IPC: 1.00
+# CHECK-NEXT: Block RThroughput: 2.5
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 2 0.50 mul a0, a1, a2
+# CHECK-NEXT: 1 2 0.50 mulh a0, a1, a2
+# CHECK-NEXT: 1 2 0.50 mulhsu a0, a1, a2
+# CHECK-NEXT: 1 2 0.50 mulhu a0, a1, a2
+# CHECK-NEXT: 1 2 0.50 mulw a0, a1, a2
+# CHECK-NEXT: 1 3 0.33 fmul.s fa0, fa1, fa2
+# CHECK-NEXT: 1 3 0.33 fmul.d fa0, fa1, fa2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: 2.00 3.00 - - - - - - - - 1.00 - 1.00 - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - mul a0, a1, a2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - mulh a0, a1, a2
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - mulhsu a0, a1, a2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - mulhu a0, a1, a2
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - mulw a0, a1, a2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fmul.s fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fmul.d fa0, fa1, fa2
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan/cascade-fma.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Nanhu/cascade-fma.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/XiangShan/cascade-fma.s
rename to llvm/test/tools/llvm-mca/RISCV/XiangShan-Nanhu/cascade-fma.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan/gpr-bypass.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Nanhu/gpr-bypass.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/XiangShan/gpr-bypass.s
rename to llvm/test/tools/llvm-mca/RISCV/XiangShan-Nanhu/gpr-bypass.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan/load-to-alu.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Nanhu/load-to-alu.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/XiangShan/load-to-alu.s
rename to llvm/test/tools/llvm-mca/RISCV/XiangShan-Nanhu/load-to-alu.s
>From bbab42d7261df124f0f12f867d55c255993be9a2 Mon Sep 17 00:00:00 2001
From: LinWang <linwang2048 at 163.com>
Date: Thu, 2 Apr 2026 17:42:41 +0800
Subject: [PATCH 3/3] [RISCV] Update XiangShan Kunminghu core documentation
links
Update the XiangShan Kunminghu core documentation links to point to the latest official documentation and user guide.
Co-Authored-By: Chyaka <lilium23187 at gmail.com>
Co-Authored-By: Bhe6669 <hebo at bosc.ac.cn>
Co-Authored-By: Tang Haojin <tanghaojin at outlook.com>
Co-authored-by: buggfg <wangyingying at bosc.ac.cn>
---
llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td | 9 ++-------
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td b/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
index 52a52c99c2245..7602451aedd4a 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
@@ -13,13 +13,8 @@
// and the Beijing Institute of Open Source Chip (BOSC),
// with a focus on achieving higher performance.
// Source: https://github.com/OpenXiangShan/XiangShan
-// Documentation: https://github.com/OpenXiangShan/XiangShan-doc
-
-//===----------------------------------------------------------------------===//
-// KunMingHu core supports "RV64IMAFDCV_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh
-// _zksed_zksh_svinval_zicbom_zicboz_zicsr_zifencei"
-// then floating-point SEW can only be 64 and 32, not 16 and 8.
-//===----------------------------------------------------------------------===//
+// Documentation: https://docs.xiangshan.cc/projects/design/en/latest/
+// User Guide: https://docs.xiangshan.cc/projects/user-guide/en/latest/
def XiangShanKunMingHuModel : SchedMachineModel {
let IssueWidth = 6; // 6-way decode and dispatch
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