[llvm] [X86] LowerShiftByScalarImmediate - vXi8 shl(X,2) - prefer PADDB+PADDB pair over PSLLW+PAND (PR #186095)
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llvm-commits at lists.llvm.org
Thu Apr 2 01:53:06 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: Simon Pilgrim (RKSimon)
<details>
<summary>Changes</summary>
For all targets, (V)PADDB is always as fast as (V)PSLLW (usually faster) - and usually as fast as (V)PAND, and avoids having to load a mask - so for shift lefts by 2, a pair of (V)PADDB is a better choice vs (V)PSLLW+(V)PAND
This is only necessary if we're avoiding a (V)PAND mask - otherwise we just need a single (V)PSLLW.
---
Patch is 159.38 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/186095.diff
33 Files Affected:
- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+7-3)
- (modified) llvm/test/CodeGen/X86/2011-12-15-vec_shift.ll (+10-10)
- (modified) llvm/test/CodeGen/X86/avx-shift.ll (+4-3)
- (modified) llvm/test/CodeGen/X86/avx2-vector-shifts.ll (+4-4)
- (modified) llvm/test/CodeGen/X86/gfni-funnel-shifts.ll (+12-5)
- (modified) llvm/test/CodeGen/X86/known-never-zero.ll (+8-8)
- (modified) llvm/test/CodeGen/X86/pr162812.ll (+26-30)
- (modified) llvm/test/CodeGen/X86/prefer-avx256-shift.ll (+6-6)
- (modified) llvm/test/CodeGen/X86/sshl_sat_vec.ll (+4-4)
- (modified) llvm/test/CodeGen/X86/undo-mul-and.ll (+21-8)
- (modified) llvm/test/CodeGen/X86/ushl_sat_vec.ll (+4-4)
- (modified) llvm/test/CodeGen/X86/vec_shift4.ll (+4-4)
- (modified) llvm/test/CodeGen/X86/vector-fshl-256.ll (+16-16)
- (modified) llvm/test/CodeGen/X86/vector-fshl-512.ll (+28-30)
- (modified) llvm/test/CodeGen/X86/vector-fshl-rot-128.ll (+8-8)
- (modified) llvm/test/CodeGen/X86/vector-fshl-rot-256.ll (+22-19)
- (modified) llvm/test/CodeGen/X86/vector-fshl-rot-512.ll (+45-39)
- (modified) llvm/test/CodeGen/X86/vector-fshr-128.ll (+83-87)
- (modified) llvm/test/CodeGen/X86/vector-fshr-256.ll (+90-91)
- (modified) llvm/test/CodeGen/X86/vector-fshr-512.ll (+30-32)
- (modified) llvm/test/CodeGen/X86/vector-fshr-rot-128.ll (+18-17)
- (modified) llvm/test/CodeGen/X86/vector-fshr-rot-256.ll (+12-12)
- (modified) llvm/test/CodeGen/X86/vector-mul-i8-decompose.ll (+145-177)
- (modified) llvm/test/CodeGen/X86/vector-mul.ll (+34-61)
- (modified) llvm/test/CodeGen/X86/vector-rotate-128.ll (+8-8)
- (modified) llvm/test/CodeGen/X86/vector-rotate-256.ll (+22-19)
- (modified) llvm/test/CodeGen/X86/vector-rotate-512.ll (+45-39)
- (modified) llvm/test/CodeGen/X86/vector-shift-lut.ll (+139-141)
- (modified) llvm/test/CodeGen/X86/vector-shift-shl-128.ll (+8-8)
- (modified) llvm/test/CodeGen/X86/vector-shift-shl-256.ll (+46-48)
- (modified) llvm/test/CodeGen/X86/vector-shift-shl-512.ll (+19-20)
- (modified) llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll (+24-24)
- (modified) llvm/test/CodeGen/X86/vshift-6.ll (+4-4)
``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index d1de545f86b6a..116a65e0bd113 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -30844,15 +30844,19 @@ static SDValue LowerShiftByScalarImmediate(SDValue Op, SelectionDAG &DAG,
unsigned NumElts = VT.getVectorNumElements();
MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
- // Simple i8 add case
- if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1) {
+ // Simple i8 add case for shl by 1 or 2 (if PSLLW requires masking).
+ if (Op.getOpcode() == ISD::SHL &&
+ (ShiftAmt == 1 ||
+ (ShiftAmt == 2 && !DAG.MaskedValueIsZero(R, APInt(8, 0xC0))))) {
// R may be undef at run-time, but (shl R, 1) must be an even number (LSB
// must be 0). (add undef, undef) however can be any value. To make this
// safe, we must freeze R to ensure that register allocation uses the same
// register for an undefined value. This ensures that the result will
// still be even and preserves the original semantics.
R = DAG.getFreeze(R);
- return DAG.getNode(ISD::ADD, dl, VT, R, R);
+ for (unsigned I = 0; I != ShiftAmt; ++I)
+ R = DAG.getNode(ISD::ADD, dl, VT, R, R);
+ return R;
}
// ashr(R, 7) === cmp_slt(R, 0)
diff --git a/llvm/test/CodeGen/X86/2011-12-15-vec_shift.ll b/llvm/test/CodeGen/X86/2011-12-15-vec_shift.ll
index fd991074f7b54..3f3c86f98f7fc 100644
--- a/llvm/test/CodeGen/X86/2011-12-15-vec_shift.ll
+++ b/llvm/test/CodeGen/X86/2011-12-15-vec_shift.ll
@@ -20,8 +20,8 @@ define <16 x i8> @shift(<16 x i8> %a, <16 x i8> %b) nounwind {
; CHECK-W-SSE4-NEXT: movdqa %xmm1, %xmm0
; CHECK-W-SSE4-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; CHECK-W-SSE4-NEXT: movdqa %xmm2, %xmm3
-; CHECK-W-SSE4-NEXT: psllw $2, %xmm3
-; CHECK-W-SSE4-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
+; CHECK-W-SSE4-NEXT: paddb %xmm2, %xmm3
+; CHECK-W-SSE4-NEXT: paddb %xmm3, %xmm3
; CHECK-W-SSE4-NEXT: paddb %xmm1, %xmm1
; CHECK-W-SSE4-NEXT: movdqa %xmm1, %xmm0
; CHECK-W-SSE4-NEXT: pblendvb %xmm0, %xmm3, %xmm2
@@ -37,22 +37,22 @@ define <16 x i8> @shift(<16 x i8> %a, <16 x i8> %b) nounwind {
; CHECK-WO-SSE4: ## %bb.0:
; CHECK-WO-SSE4-NEXT: psllw $5, %xmm1
; CHECK-WO-SSE4-NEXT: pxor %xmm2, %xmm2
-; CHECK-WO-SSE4-NEXT: pcmpgtb %xmm1, %xmm2
-; CHECK-WO-SSE4-NEXT: movdqa %xmm2, %xmm3
-; CHECK-WO-SSE4-NEXT: pandn %xmm0, %xmm3
+; CHECK-WO-SSE4-NEXT: pxor %xmm3, %xmm3
+; CHECK-WO-SSE4-NEXT: pcmpgtb %xmm1, %xmm3
+; CHECK-WO-SSE4-NEXT: movdqa %xmm3, %xmm4
+; CHECK-WO-SSE4-NEXT: pandn %xmm0, %xmm4
; CHECK-WO-SSE4-NEXT: psllw $4, %xmm0
-; CHECK-WO-SSE4-NEXT: pand %xmm2, %xmm0
+; CHECK-WO-SSE4-NEXT: pand %xmm3, %xmm0
; CHECK-WO-SSE4-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; CHECK-WO-SSE4-NEXT: pxor %xmm2, %xmm2
-; CHECK-WO-SSE4-NEXT: por %xmm3, %xmm0
+; CHECK-WO-SSE4-NEXT: por %xmm4, %xmm0
; CHECK-WO-SSE4-NEXT: paddb %xmm1, %xmm1
; CHECK-WO-SSE4-NEXT: pxor %xmm3, %xmm3
; CHECK-WO-SSE4-NEXT: pcmpgtb %xmm1, %xmm3
; CHECK-WO-SSE4-NEXT: movdqa %xmm3, %xmm4
; CHECK-WO-SSE4-NEXT: pandn %xmm0, %xmm4
-; CHECK-WO-SSE4-NEXT: psllw $2, %xmm0
+; CHECK-WO-SSE4-NEXT: paddb %xmm0, %xmm0
+; CHECK-WO-SSE4-NEXT: paddb %xmm0, %xmm0
; CHECK-WO-SSE4-NEXT: pand %xmm3, %xmm0
-; CHECK-WO-SSE4-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-WO-SSE4-NEXT: por %xmm4, %xmm0
; CHECK-WO-SSE4-NEXT: paddb %xmm1, %xmm1
; CHECK-WO-SSE4-NEXT: pcmpgtb %xmm1, %xmm2
diff --git a/llvm/test/CodeGen/X86/avx-shift.ll b/llvm/test/CodeGen/X86/avx-shift.ll
index 3bce84348b7f0..fd5e2c85916ae 100644
--- a/llvm/test/CodeGen/X86/avx-shift.ll
+++ b/llvm/test/CodeGen/X86/avx-shift.ll
@@ -149,11 +149,12 @@ define <32 x i8> @vshift11(<32 x i8> %a) {
define <32 x i8> @vshift12(<32 x i8> %a) {
; CHECK-LABEL: vshift12:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpsllw $2, %xmm0, %xmm1
+; CHECK-NEXT: vpaddb %xmm0, %xmm0, %xmm1
+; CHECK-NEXT: vpaddb %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
-; CHECK-NEXT: vpsllw $2, %xmm0, %xmm0
+; CHECK-NEXT: vpaddb %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vpaddb %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
-; CHECK-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: retq
%s = shl <32 x i8> %a, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
ret <32 x i8> %s
diff --git a/llvm/test/CodeGen/X86/avx2-vector-shifts.ll b/llvm/test/CodeGen/X86/avx2-vector-shifts.ll
index 95c2eda5059e5..7343546488ece 100644
--- a/llvm/test/CodeGen/X86/avx2-vector-shifts.ll
+++ b/llvm/test/CodeGen/X86/avx2-vector-shifts.ll
@@ -373,8 +373,8 @@ define <32 x i8> @shl_32i8(<32 x i8> %r, <32 x i8> %a) nounwind {
; X86-NEXT: vpsllw $4, %ymm0, %ymm2
; X86-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm2
; X86-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
-; X86-NEXT: vpsllw $2, %ymm0, %ymm2
-; X86-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm2
+; X86-NEXT: vpaddb %ymm0, %ymm0, %ymm2
+; X86-NEXT: vpaddb %ymm2, %ymm2, %ymm2
; X86-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; X86-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; X86-NEXT: vpaddb %ymm0, %ymm0, %ymm2
@@ -388,8 +388,8 @@ define <32 x i8> @shl_32i8(<32 x i8> %r, <32 x i8> %a) nounwind {
; X64-NEXT: vpsllw $4, %ymm0, %ymm2
; X64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; X64-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
-; X64-NEXT: vpsllw $2, %ymm0, %ymm2
-; X64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
+; X64-NEXT: vpaddb %ymm0, %ymm0, %ymm2
+; X64-NEXT: vpaddb %ymm2, %ymm2, %ymm2
; X64-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; X64-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; X64-NEXT: vpaddb %ymm0, %ymm0, %ymm2
diff --git a/llvm/test/CodeGen/X86/gfni-funnel-shifts.ll b/llvm/test/CodeGen/X86/gfni-funnel-shifts.ll
index 52415c212b1aa..dcbba6929d735 100644
--- a/llvm/test/CodeGen/X86/gfni-funnel-shifts.ll
+++ b/llvm/test/CodeGen/X86/gfni-funnel-shifts.ll
@@ -1225,25 +1225,32 @@ define <32 x i8> @splatconstant_fshr_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind
; GFNISSE: # %bb.0:
; GFNISSE-NEXT: movdqa {{.*#+}} xmm4 = [0,0,0,0,0,0,128,64,0,0,0,0,0,0,128,64]
; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm2
-; GFNISSE-NEXT: movdqa {{.*#+}} xmm5 = [32,16,8,4,2,1,0,0,32,16,8,4,2,1,0,0]
-; GFNISSE-NEXT: gf2p8affineqb $0, %xmm5, %xmm0
+; GFNISSE-NEXT: paddb %xmm0, %xmm0
+; GFNISSE-NEXT: paddb %xmm0, %xmm0
; GFNISSE-NEXT: por %xmm2, %xmm0
; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm3
-; GFNISSE-NEXT: gf2p8affineqb $0, %xmm5, %xmm1
+; GFNISSE-NEXT: paddb %xmm1, %xmm1
+; GFNISSE-NEXT: paddb %xmm1, %xmm1
; GFNISSE-NEXT: por %xmm3, %xmm1
; GFNISSE-NEXT: retq
;
; GFNIAVX1-LABEL: splatconstant_fshr_v32i8:
; GFNIAVX1: # %bb.0:
+; GFNIAVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm2
+; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm2, %xmm2
+; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
+; GFNIAVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm0
+; GFNIAVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm0
+; GFNIAVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
; GFNIAVX1-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
-; GFNIAVX1-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; GFNIAVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
; GFNIAVX1-NEXT: retq
;
; GFNIAVX2-LABEL: splatconstant_fshr_v32i8:
; GFNIAVX2: # %bb.0:
; GFNIAVX2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
-; GFNIAVX2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; GFNIAVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm0
+; GFNIAVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm0
; GFNIAVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; GFNIAVX2-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/known-never-zero.ll b/llvm/test/CodeGen/X86/known-never-zero.ll
index 37c10219b471d..948c49b3dc867 100644
--- a/llvm/test/CodeGen/X86/known-never-zero.ll
+++ b/llvm/test/CodeGen/X86/known-never-zero.ll
@@ -511,9 +511,9 @@ define i32 @umax_known_nonzero_vec(<16 x i8> %x, ptr %p) {
; X86-NEXT: pcmpgtb %xmm3, %xmm4
; X86-NEXT: movdqa %xmm4, %xmm5
; X86-NEXT: pandn %xmm1, %xmm5
-; X86-NEXT: psllw $2, %xmm1
+; X86-NEXT: paddb %xmm1, %xmm1
+; X86-NEXT: paddb %xmm1, %xmm1
; X86-NEXT: pand %xmm4, %xmm1
-; X86-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-NEXT: por %xmm5, %xmm1
; X86-NEXT: paddb %xmm3, %xmm3
; X86-NEXT: pcmpgtb %xmm3, %xmm2
@@ -533,8 +533,8 @@ define i32 @umax_known_nonzero_vec(<16 x i8> %x, ptr %p) {
; X64-NEXT: vpsllw $5, %xmm0, %xmm1
; X64-NEXT: vpmovsxbq {{.*#+}} xmm2 = [4,0]
; X64-NEXT: vpblendvb %xmm1, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; X64-NEXT: vpsllw $2, %xmm2, %xmm3
-; X64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
+; X64-NEXT: vpaddb %xmm2, %xmm2, %xmm3
+; X64-NEXT: vpaddb %xmm3, %xmm3, %xmm3
; X64-NEXT: vpaddb %xmm1, %xmm1, %xmm1
; X64-NEXT: vpblendvb %xmm1, %xmm3, %xmm2, %xmm2
; X64-NEXT: vpaddb %xmm2, %xmm2, %xmm3
@@ -627,9 +627,9 @@ define i32 @umin_known_nonzero_vec(<16 x i8> %x, ptr %p) {
; X86-NEXT: pcmpgtb %xmm3, %xmm4
; X86-NEXT: movdqa %xmm4, %xmm5
; X86-NEXT: pandn %xmm1, %xmm5
-; X86-NEXT: psllw $2, %xmm1
+; X86-NEXT: paddb %xmm1, %xmm1
+; X86-NEXT: paddb %xmm1, %xmm1
; X86-NEXT: pand %xmm4, %xmm1
-; X86-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-NEXT: por %xmm5, %xmm1
; X86-NEXT: paddb %xmm3, %xmm3
; X86-NEXT: pcmpgtb %xmm3, %xmm2
@@ -651,8 +651,8 @@ define i32 @umin_known_nonzero_vec(<16 x i8> %x, ptr %p) {
; X64-NEXT: vpsllw $5, %xmm0, %xmm1
; X64-NEXT: vpmovsxbq {{.*#+}} xmm2 = [4,0]
; X64-NEXT: vpblendvb %xmm1, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; X64-NEXT: vpsllw $2, %xmm2, %xmm3
-; X64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
+; X64-NEXT: vpaddb %xmm2, %xmm2, %xmm3
+; X64-NEXT: vpaddb %xmm3, %xmm3, %xmm3
; X64-NEXT: vpaddb %xmm1, %xmm1, %xmm1
; X64-NEXT: vpblendvb %xmm1, %xmm3, %xmm2, %xmm2
; X64-NEXT: vpaddb %xmm2, %xmm2, %xmm3
diff --git a/llvm/test/CodeGen/X86/pr162812.ll b/llvm/test/CodeGen/X86/pr162812.ll
index c17f8d2c7a732..5aab21de1e847 100644
--- a/llvm/test/CodeGen/X86/pr162812.ll
+++ b/llvm/test/CodeGen/X86/pr162812.ll
@@ -241,9 +241,8 @@ define <32 x i8> @shl2_v32i8(<32 x i8> %a, <32 x i8> %mask) {
; SSE2-NEXT: pcmpgtb %xmm2, %xmm6
; SSE2-NEXT: movdqa %xmm6, %xmm7
; SSE2-NEXT: pandn %xmm0, %xmm7
-; SSE2-NEXT: psllw $2, %xmm0
-; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; SSE2-NEXT: pand %xmm8, %xmm0
+; SSE2-NEXT: paddb %xmm0, %xmm0
+; SSE2-NEXT: paddb %xmm0, %xmm0
; SSE2-NEXT: pand %xmm6, %xmm0
; SSE2-NEXT: por %xmm7, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm2
@@ -259,8 +258,8 @@ define <32 x i8> @shl2_v32i8(<32 x i8> %a, <32 x i8> %mask) {
; SSE2-NEXT: pcmpgtb %xmm3, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm5
; SSE2-NEXT: pandn %xmm1, %xmm5
-; SSE2-NEXT: psllw $2, %xmm1
-; SSE2-NEXT: pand %xmm8, %xmm1
+; SSE2-NEXT: paddb %xmm1, %xmm1
+; SSE2-NEXT: paddb %xmm1, %xmm1
; SSE2-NEXT: pand %xmm2, %xmm1
; SSE2-NEXT: por %xmm5, %xmm1
; SSE2-NEXT: paddb %xmm3, %xmm3
@@ -274,41 +273,38 @@ define <32 x i8> @shl2_v32i8(<32 x i8> %a, <32 x i8> %mask) {
;
; SSE42-LABEL: shl2_v32i8:
; SSE42: # %bb.0:
-; SSE42-NEXT: movdqa %xmm3, %xmm4
-; SSE42-NEXT: movdqa %xmm2, %xmm5
+; SSE42-NEXT: movdqa %xmm2, %xmm4
; SSE42-NEXT: movdqa %xmm0, %xmm2
-; SSE42-NEXT: movdqa {{.*#+}} xmm3 = [49344,49344,49344,49344,49344,49344,49344,49344]
-; SSE42-NEXT: movdqa %xmm5, %xmm6
-; SSE42-NEXT: pand %xmm3, %xmm6
-; SSE42-NEXT: paddb %xmm6, %xmm6
-; SSE42-NEXT: movdqa %xmm0, %xmm7
-; SSE42-NEXT: psllw $2, %xmm7
-; SSE42-NEXT: movdqa {{.*#+}} xmm8 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; SSE42-NEXT: pand %xmm8, %xmm7
-; SSE42-NEXT: movdqa %xmm5, %xmm0
-; SSE42-NEXT: pblendvb %xmm0, %xmm7, %xmm2
-; SSE42-NEXT: movdqa %xmm2, %xmm5
-; SSE42-NEXT: paddb %xmm2, %xmm5
-; SSE42-NEXT: movdqa %xmm6, %xmm0
+; SSE42-NEXT: movdqa %xmm0, %xmm5
+; SSE42-NEXT: paddb %xmm0, %xmm5
+; SSE42-NEXT: paddb %xmm5, %xmm5
+; SSE42-NEXT: movdqa %xmm4, %xmm0
; SSE42-NEXT: pblendvb %xmm0, %xmm5, %xmm2
-; SSE42-NEXT: pand %xmm4, %xmm3
-; SSE42-NEXT: movdqa %xmm1, %xmm5
-; SSE42-NEXT: psllw $2, %xmm5
-; SSE42-NEXT: pand %xmm8, %xmm5
+; SSE42-NEXT: movdqa %xmm2, %xmm6
+; SSE42-NEXT: paddb %xmm2, %xmm6
+; SSE42-NEXT: movdqa {{.*#+}} xmm5 = [49344,49344,49344,49344,49344,49344,49344,49344]
+; SSE42-NEXT: pand %xmm5, %xmm4
+; SSE42-NEXT: paddb %xmm4, %xmm4
; SSE42-NEXT: movdqa %xmm4, %xmm0
-; SSE42-NEXT: pblendvb %xmm0, %xmm5, %xmm1
-; SSE42-NEXT: paddb %xmm3, %xmm3
+; SSE42-NEXT: pblendvb %xmm0, %xmm6, %xmm2
; SSE42-NEXT: movdqa %xmm1, %xmm4
; SSE42-NEXT: paddb %xmm1, %xmm4
+; SSE42-NEXT: paddb %xmm4, %xmm4
; SSE42-NEXT: movdqa %xmm3, %xmm0
; SSE42-NEXT: pblendvb %xmm0, %xmm4, %xmm1
+; SSE42-NEXT: movdqa %xmm1, %xmm4
+; SSE42-NEXT: paddb %xmm1, %xmm4
+; SSE42-NEXT: pand %xmm3, %xmm5
+; SSE42-NEXT: paddb %xmm5, %xmm5
+; SSE42-NEXT: movdqa %xmm5, %xmm0
+; SSE42-NEXT: pblendvb %xmm0, %xmm4, %xmm1
; SSE42-NEXT: movdqa %xmm2, %xmm0
; SSE42-NEXT: retq
;
; AVX2-LABEL: shl2_v32i8:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpsllw $2, %ymm0, %ymm2
-; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
+; AVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm2
+; AVX2-NEXT: vpaddb %ymm2, %ymm2, %ymm2
; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
; AVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm2
@@ -318,8 +314,8 @@ define <32 x i8> @shl2_v32i8(<32 x i8> %a, <32 x i8> %mask) {
;
; AVX512-LABEL: shl2_v32i8:
; AVX512: # %bb.0:
-; AVX512-NEXT: vpsllw $2, %ymm0, %ymm2
-; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm2
+; AVX512-NEXT: vpaddb %ymm0, %ymm0, %ymm2
+; AVX512-NEXT: vpaddb %ymm2, %ymm2, %ymm2
; AVX512-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; AVX512-NEXT: vpaddb %ymm0, %ymm0, %ymm2
; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm1, %ymm1
diff --git a/llvm/test/CodeGen/X86/prefer-avx256-shift.ll b/llvm/test/CodeGen/X86/prefer-avx256-shift.ll
index 63bbac12c6255..09d6ecf9bf229 100644
--- a/llvm/test/CodeGen/X86/prefer-avx256-shift.ll
+++ b/llvm/test/CodeGen/X86/prefer-avx256-shift.ll
@@ -13,8 +13,8 @@ define <32 x i8> @var_shl_v32i8(<32 x i8> %a, <32 x i8> %b) {
; AVX256-NEXT: vpsllw $4, %ymm0, %ymm2
; AVX256-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm2
; AVX256-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
-; AVX256-NEXT: vpsllw $2, %ymm0, %ymm2
-; AVX256-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm2
+; AVX256-NEXT: vpaddb %ymm0, %ymm0, %ymm2
+; AVX256-NEXT: vpaddb %ymm2, %ymm2, %ymm2
; AVX256-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; AVX256-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; AVX256-NEXT: vpaddb %ymm0, %ymm0, %ymm2
@@ -36,8 +36,8 @@ define <32 x i8> @var_shl_v32i8(<32 x i8> %a, <32 x i8> %b) {
; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm2
; AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm2
; AVX512VL-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
-; AVX512VL-NEXT: vpsllw $2, %ymm0, %ymm2
-; AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm2
+; AVX512VL-NEXT: vpaddb %ymm0, %ymm0, %ymm2
+; AVX512VL-NEXT: vpaddb %ymm2, %ymm2, %ymm2
; AVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; AVX512VL-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; AVX512VL-NEXT: vpaddb %ymm0, %ymm0, %ymm2
@@ -117,8 +117,8 @@ define <16 x i8> @var_shl_v16i8(<16 x i8> %a, <16 x i8> %b) {
; AVX256VL-NEXT: vpsllw $4, %xmm0, %xmm2
; AVX256VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm2, %xmm2
; AVX256VL-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0
-; AVX256VL-NEXT: vpsllw $2, %xmm0, %xmm2
-; AVX256VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm2, %xmm2
+; AVX256VL-NEXT: vpaddb %xmm0, %xmm0, %xmm2
+; AVX256VL-NEXT: vpaddb %xmm2, %xmm2, %xmm2
; AVX256VL-NEXT: vpaddb %xmm1, %xmm1, %xmm1
; AVX256VL-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0
; AVX256VL-NEXT: vpaddb %xmm0, %xmm0, %xmm2
diff --git a/llvm/test/CodeGen/X86/sshl_sat_vec.ll b/llvm/test/CodeGen/X86/sshl_sat_vec.ll
index 15069e558b08d..bbacbc2bbe9e6 100644
--- a/llvm/test/CodeGen/X86/sshl_sat_vec.ll
+++ b/llvm/test/CodeGen/X86/sshl_sat_vec.ll
@@ -507,9 +507,9 @@ define <16 x i8> @vec_v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
; X64-NEXT: pcmpgtb %xmm1, %xmm6
; X64-NEXT: movdqa %xmm6, %xmm7
; X64-NEXT: pandn %xmm2, %xmm7
-; X64-NEXT: psllw $2, %xmm2
+; X64-NEXT: paddb %xmm2, %xmm2
+; X64-NEXT: paddb %xmm2, %xmm2
; X64-NEXT: pand %xmm6, %xmm2
-; X64-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; X64-NEXT: por %xmm7, %xmm2
; X64-NEXT: paddb %xmm1, %xmm1
; X64-NEXT: pxor %xmm6, %xmm6
@@ -587,8 +587,8 @@ define <16 x i8> @vec_v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
; X64-AVX2-NEXT: vpsllw $4, %xmm0, %xmm2
; X64-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; X64-AVX2-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm2
-; X64-AVX2-NEXT: vpsllw $2, %xmm2, %xmm3
-; X64-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
+; X64-AVX2-NEXT: vpaddb %xmm2, %xmm2, %xmm3
+; X64-AVX2-NEXT: vpaddb %xmm3, %xmm3, %xmm3
; X64-AVX2-NEXT: vpaddb %xmm1, %xmm1, %xmm4
; X64-AVX2-NEXT: vpblendvb %xmm4, %xmm3, %xmm2, %xmm2
; X64-AVX2-NEXT: vpaddb %xmm2, %xmm2, %xmm3
diff --git a/llvm/test/CodeGen/X86/undo-mul-and.ll b/llvm/test/CodeGen/X86/undo-mul-and.ll
index 7308b1d30e951..a3a2fcc19cac9 100644
--- a/llvm/test/CodeGen/X86/undo-mul-and.ll
+++ b/llvm/test/CodeGen/X86/undo-mul-and.ll
@@ -208,20 +208,31 @@ define <4 x i32> @mul_and_to_neg_shl_and_vec_with_undef_and(<4 x i32> %x) {
define <16 x i8> @mul_and_to_neg_shl_and_vec_with_undef_mul_and(<16 x i8> %x) {
; CHECK-SSE-LABEL: mul_and_to_neg_shl_and_vec_with_undef_mul_and:
; CHECK-SSE: # %bb.0:
+; CHECK-SSE-NEXT: paddb %xmm0, %xmm0
+; CHECK-SSE-NEXT: paddb %xmm0, %xmm0
; CHECK-SSE-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE-NEXT: psubb %xmm0, %xmm1
-; CHECK-SSE-NEXT: psllw $2, %xmm1
; CHECK-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE-NEXT: movdqa %xmm1, %xmm0
; CHECK-SSE-NEXT: retq
;
-; CHECK-AVX-LABEL: mul_and_to_neg_shl_and_vec_with_undef_mul_and:
-; CHECK-AVX: # %bb.0:
-; CHECK-AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; CHECK-AVX-NEXT: vpsubb %xmm0, %xmm1, %xmm0
-; CHECK-AVX-NEXT: vpsllw $2, %xmm0, %xmm0
-; CHECK-AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; CHECK-AVX-NEXT: retq
+; CHECK-AVX1-LABEL: mul_and_to_neg_shl_and_vec_with_undef_mul_and:
+; CHECK-AVX1: # %bb.0:
+; CHECK-AVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm0
+; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; CHECK-AVX1-NEXT: vpsubb %xmm0, %xmm1, %xmm0
+; CHECK-AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; CHECK-AVX1-NEXT: retq
+;
+; CHECK-AVX512-LABEL: mul_and_to_neg_shl_and_vec_with_undef_mul_and:
+; CHECK-AVX512: # %bb.0:
+; CHECK-AVX512-NEXT: vpaddb %xmm0, %xmm0, %xmm0
+; CHECK-AVX512-NEXT: vpaddb %xmm0, %xmm0, %xmm0
+; CHECK-AVX512-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; CHECK-AVX512-NEXT: vpsubb %xmm0, %xmm1, %xmm0
+; CHECK-AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; CHECK-AVX512-NEXT: retq
%mul = mul <16 x i8> %x, <i8 12, i8 12, i8 12, i8 12, i8 undef, i8 12, i8 12, i8 12, i8 12, i8 12, i8 12, i8 12, i8 12, i8 12, i8 12, i8 12>
%and = and <16 x i8> %mul, <i8 11, i8 undef, i8 11, i8 11, i8 11, i8 11, i8 11, i8 11, i...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/186095
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