[llvm] [AArch64][llvm] Some instructions should be `HINT` aliases (NFC) (PR #189926)
Jonathan Thackray via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 2 01:47:01 PDT 2026
https://github.com/jthackray updated https://github.com/llvm/llvm-project/pull/189926
>From ca2cb819305a03f8f321cada5e02f5c90976779a Mon Sep 17 00:00:00 2001
From: Jonathan Thackray <jonathan.thackray at arm.com>
Date: Tue, 31 Mar 2026 01:18:43 +0100
Subject: [PATCH] [AArch64][llvm] Some instructions should be `HINT` aliases
(NFC)
Implement the following instructions as a `HINT` alias instead of a
dedicated instruction in separate classes:
* `stshh`
* `stcph`
* `shuh`
* `tsb`
Updated all their helper methods too, and updated the `stshh` pseudo
expansion for the intrinsic to emit `HINT #0x30 | policy`.
Code in AArch64AsmPrinter::emitInstruction identified an initial BTI using a
broad bitmask on the HINT immediate, which also matched shuh/stcph (50..52)
This could move the patchable entry label after a non-BTI instruction.
Replaced it with an exact BTI check using the BTI HINT range (32..63) and
AArch64BTIHint::lookupBTIByEncoding(Imm ^ 32).
A following change will remove duplicated code and simplify.
No test changes.
---
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp | 6 +-
.../AArch64/AArch64ExpandPseudoInsts.cpp | 4 +-
.../lib/Target/AArch64/AArch64InstrFormats.td | 80 ++++++------
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 19 +--
.../Target/AArch64/AArch64SystemOperands.td | 15 +--
.../AArch64/AsmParser/AArch64AsmParser.cpp | 115 ++++++++++++++++++
.../MCTargetDesc/AArch64InstPrinter.cpp | 25 +++-
.../AArch64/MCTargetDesc/AArch64InstPrinter.h | 6 +
.../Target/AArch64/Utils/AArch64BaseInfo.h | 2 +-
9 files changed, 201 insertions(+), 71 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index 87fbe9be14a22..6b81ae318876c 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -3186,8 +3186,10 @@ void AArch64AsmPrinter::emitInstruction(const MachineInstr *MI) {
if (CurrentPatchableFunctionEntrySym &&
CurrentPatchableFunctionEntrySym == CurrentFnBegin &&
MI == &MF->front().front()) {
- int64_t Imm = MI->getOperand(0).getImm();
- if ((Imm & 32) && (Imm & 6)) {
+ uint64_t Imm = MI->getOperand(0).getImm();
+ // Match only exact BTI encodings in HINT space.
+ if (Imm >= 32 && Imm < 64 &&
+ AArch64BTIHint::lookupBTIByEncoding(Imm ^ 32)) {
MCInst Inst;
MCInstLowering.Lower(MI, Inst);
EmitToStreamer(*OutStreamer, Inst);
diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
index 4ab8adeb2c9bc..82e6822d49437 100644
--- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
@@ -1092,8 +1092,8 @@ bool AArch64ExpandPseudoImpl::expandSTSHHAtomicStore(
}
// Emit the hint with the retention policy immediate.
- MachineInstr *Hint = BuildMI(MBB, MBBI, DL, TII->get(AArch64::STSHH))
- .addImm(Policy)
+ MachineInstr *Hint = BuildMI(MBB, MBBI, DL, TII->get(AArch64::HINT))
+ .addImm(AArch64PHint::keep + Policy)
.getInstr();
// Emit the associated store instruction.
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 1774927e9297d..160c7b1d6e8bd 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1867,18 +1867,51 @@ def PHintInstOperand : AsmOperandClass {
def phint_op : Operand<i32> {
let ParserMatchClass = PHintInstOperand;
let PrintMethod = "printPHintOp";
+ let MCOperandPredicate = [{
+ if (!MCOp.isImm())
+ return false;
+ return AArch64PHint::lookupPHintByEncoding(MCOp.getImm()) != nullptr;
+ }];
let OperandType = "OPERAND_IMMEDIATE";
let MIOperandInfo = (ops i32imm: $policy);
- let DecoderMethod = "DecodeUImm<3>";
+ let DecoderMethod = "DecodeUImm<7>";
}
-class STSHHI
- : SimpleSystemI<0, (ins phint_op:$policy), "stshh", "\t$policy", []>,
- Sched<[WriteHint]> {
- bits<3> policy;
- let Inst{20-12} = 0b000110010;
- let Inst{11-8} = 0b0110;
- let Inst{7-5} = policy;
+def TSBHintOperand : AsmOperandClass {
+ let Name = "TSBHint";
+ let ParserMethod = "tryParseTSBHintOperand";
+}
+
+def tsbhint_op : Operand<i32> {
+ let ParserMatchClass = TSBHintOperand;
+ let PrintMethod = "printTSBHintOp";
+ let MCOperandPredicate = [{
+ if (!MCOp.isImm() || MCOp.getImm() < 16)
+ return false;
+ return AArch64TSB::lookupTSBByEncoding(MCOp.getImm() - 16) != nullptr;
+ }];
+ let OperandType = "OPERAND_IMMEDIATE";
+ let MIOperandInfo = (ops i32imm: $policy);
+ let DecoderMethod = "DecodeUImm<7>";
+}
+
+def SHUHintOperand : AsmOperandClass {
+ let Name = "SHUHint";
+ let ParserMethod = "tryParseSHUHintOperand";
+}
+
+def shuhint_op : Operand<i32> {
+ let ParserMatchClass = SHUHintOperand;
+ let PrintMethod = "printSHUHintOp";
+ let MCOperandPredicate = [{
+ if (!MCOp.isImm() || MCOp.getImm() < 50)
+ return false;
+ return AArch64CMHPriorityHint::lookupCMHPriorityHintByEncoding(
+ MCOp.getImm() - 50) != nullptr;
+ }];
+ let OperandType = "OPERAND_IMMEDIATE";
+ let MIOperandInfo = (ops i32imm: $priority);
+ let DecoderMethod = "DecodeUImm<7>";
}
// System instructions taking a single literal operand which encodes into
@@ -13581,37 +13614,6 @@ multiclass SIMDThreeSameVectorFP8MatrixMul<string asm, SDPatternOperator OpNode>
}
}
-//----------------------------------------------------------------------------
-// Contention Management Hints - FEAT_CMH
-//----------------------------------------------------------------------------
-
-class SHUHInst<string asm> : I<
- (outs),
- (ins CMHPriorityHint_op:$priority),
- asm, "\t$priority", "", []>, Sched<[]> {
- bits<1> priority;
- let Inst{31-12} = 0b11010101000000110010;
- let Inst{11-8} = 0b0110;
- let Inst{7-6} = 0b01;
- let Inst{5} = priority;
- let Inst{4-0} = 0b11111;
-}
-
-multiclass SHUH<string asm> {
- def NAME : SHUHInst<asm>;
- def : InstAlias<asm, (!cast<Instruction>(NAME) 0), 1>;
-}
-
-class STCPHInst<string asm> : I<
- (outs),
- (ins),
- asm, "", "", []>, Sched<[]> {
- let Inst{31-12} = 0b11010101000000110010;
- let Inst{11-8} = 0b0110;
- let Inst{7-5} = 0b100;
- let Inst{4-0} = 0b11111;
-}
-
//---
// Permission Overlays Extension 2 (FEAT_S1POE2)
//---
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 08512f6ed8df1..9fa9fcb44425c 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -1566,7 +1566,10 @@ def NOP : SystemNoOperands<0b000, "hint\t#0">;
def : InstAlias<"nop", (NOP)>;
-def STSHH: STSHHI;
+def : InstAlias<"stshh $policy", (HINT phint_op:$policy)>;
+def : InstAlias<"shuh", (HINT 50)>;
+def : InstAlias<"shuh $op", (HINT shuhint_op:$op)>;
+def : InstAlias<"stcph", (HINT 52)>;
let hasSideEffects = 1, mayStore = 1, isCodeGenOnly = 1 in {
let Size = 8 in
@@ -1610,12 +1613,6 @@ def DSB : CRmSystemI<barrier_op, 0b100, "dsb",
def ISB : CRmSystemI<barrier_op, 0b110, "isb",
[(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
-def TSB : CRmSystemI<barrier_op, 0b010, "tsb", []> {
- let CRm = 0b0010;
- let Inst{12} = 0;
- let Predicates = [HasTRACEV8_4];
-}
-
def DSBnXS : CRmSystemI<barrier_nxs_op, 0b001, "dsb"> {
let CRm{1-0} = 0b11;
let Inst{9-8} = 0b10;
@@ -1695,6 +1692,7 @@ def GCSPOPM_NoOp : InstAlias<"gcspopm", (GCSPOPM XZR)>, Requires<[HasGCS]>; // R
def GCSB_DSYNC_disable : InstAlias<"gcsb\tdsync", (HINT 19), 0>;
def GCSB_DSYNC : InstAlias<"gcsb\tdsync", (HINT 19), 1>, Requires<[HasGCS]>;
+def : InstAlias<"tsb\t$op", (HINT tsbhint_op:$op)>, Requires<[HasTRACEV8_4]>;
def : TokenAlias<"DSYNC", "dsync">;
@@ -11896,13 +11894,6 @@ let Predicates = [HasF16F32MM] in
let Uses = [FPMR, FPCR] in
defm FMMLA : SIMDThreeSameVectorFP8MatrixMul<"fmmla", int_aarch64_neon_fmmla>;
-//===----------------------------------------------------------------------===//
-// Contention Management Hints (FEAT_CMH)
-//===----------------------------------------------------------------------===//
-
-defm SHUH : SHUH<"shuh">; // Shared Update Hint instruction
-def STCPH : STCPHInst<"stcph">; // Store Concurrent Priority Hint instruction
-
//===----------------------------------------------------------------------===//
// Permission Overlays Extension 2 (FEAT_S1POE2)
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index e5a8844f078f4..73ad5fef0bf90 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -2453,15 +2453,10 @@ def : RWSysReg<"ACTLRALIAS_EL1", 0b11, 0b000, 0b0001, 0b0100, 0b101>;
// v9.6a PCDPHINT instruction options.
//===----------------------------------------------------------------------===//
-class PHint<bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
- bits<3> op2, string name> {
+class PHint<string name, bits<7> encoding> {
string Name = name;
- bits<16> Encoding;
- let Encoding{15-14} = op0;
- let Encoding{13-11} = op1;
- let Encoding{10-7} = crn;
- let Encoding{6-3} = crm;
- let Encoding{2-0} = op2;
+ bits<7> Encoding;
+ let Encoding = encoding;
code Requires = [{ {} }];
}
@@ -2484,8 +2479,8 @@ def lookupPHintByName : SearchIndex {
let Key = ["Name"];
}
-def KEEP : PHint<0b00, 0b000, 0b0000, 0b0000, 0b000, "keep">;
-def STRM : PHint<0b00, 0b000, 0b0000, 0b0000, 0b001, "strm">;
+def KEEP : PHint<"keep", 0b0110000>;
+def STRM : PHint<"strm", 0b0110001>;
// v9.6a Realm management extension enhancements
def : RWSysReg<"GPCBW_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b101>;
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 921e5446a3ad5..5d2c96848de9c 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -268,6 +268,8 @@ class AArch64AsmParser : public MCTargetAsmParser {
ParseStatus tryParseRPRFMOperand(OperandVector &Operands);
ParseStatus tryParsePSBHint(OperandVector &Operands);
ParseStatus tryParseBTIHint(OperandVector &Operands);
+ ParseStatus tryParseSHUHintOperand(OperandVector &Operands);
+ ParseStatus tryParseTSBHintOperand(OperandVector &Operands);
ParseStatus tryParseCMHPriorityHint(OperandVector &Operands);
ParseStatus tryParseTIndexHint(OperandVector &Operands);
ParseStatus tryParseAdrpLabel(OperandVector &Operands);
@@ -374,6 +376,8 @@ class AArch64Operand : public MCParsedAsmOperand {
k_PSBHint,
k_PHint,
k_BTIHint,
+ k_SHUHint,
+ k_TSBHint,
k_CMHPriorityHint,
k_TIndexHint,
} Kind;
@@ -505,6 +509,16 @@ class AArch64Operand : public MCParsedAsmOperand {
unsigned Length;
unsigned Val;
};
+ struct SHUHintOp {
+ const char *Data;
+ unsigned Length;
+ unsigned Val;
+ };
+ struct TSBHintOp {
+ const char *Data;
+ unsigned Length;
+ unsigned Val;
+ };
struct CMHPriorityHintOp {
const char *Data;
unsigned Length;
@@ -541,6 +555,8 @@ class AArch64Operand : public MCParsedAsmOperand {
struct PSBHintOp PSBHint;
struct PHintOp PHint;
struct BTIHintOp BTIHint;
+ struct SHUHintOp SHUHint;
+ struct TSBHintOp TSBHint;
struct CMHPriorityHintOp CMHPriorityHint;
struct TIndexHintOp TIndexHint;
struct ShiftExtendOp ShiftExtend;
@@ -613,6 +629,12 @@ class AArch64Operand : public MCParsedAsmOperand {
case k_BTIHint:
BTIHint = o.BTIHint;
break;
+ case k_SHUHint:
+ SHUHint = o.SHUHint;
+ break;
+ case k_TSBHint:
+ TSBHint = o.TSBHint;
+ break;
case k_CMHPriorityHint:
CMHPriorityHint = o.CMHPriorityHint;
break;
@@ -788,11 +810,31 @@ class AArch64Operand : public MCParsedAsmOperand {
return BTIHint.Val;
}
+ unsigned getSHUHint() const {
+ assert(Kind == k_SHUHint && "Invalid access!");
+ return SHUHint.Val;
+ }
+
+ unsigned getTSBHint() const {
+ assert(Kind == k_TSBHint && "Invalid access!");
+ return TSBHint.Val;
+ }
+
StringRef getBTIHintName() const {
assert(Kind == k_BTIHint && "Invalid access!");
return StringRef(BTIHint.Data, BTIHint.Length);
}
+ StringRef getSHUHintName() const {
+ assert(Kind == k_SHUHint && "Invalid access!");
+ return StringRef(SHUHint.Data, SHUHint.Length);
+ }
+
+ StringRef getTSBHintName() const {
+ assert(Kind == k_TSBHint && "Invalid access!");
+ return StringRef(TSBHint.Data, TSBHint.Length);
+ }
+
unsigned getCMHPriorityHint() const {
assert(Kind == k_CMHPriorityHint && "Invalid access!");
return CMHPriorityHint.Val;
@@ -1555,6 +1597,8 @@ class AArch64Operand : public MCParsedAsmOperand {
bool isPSBHint() const { return Kind == k_PSBHint; }
bool isPHint() const { return Kind == k_PHint; }
bool isBTIHint() const { return Kind == k_BTIHint; }
+ bool isSHUHint() const { return Kind == k_SHUHint; }
+ bool isTSBHint() const { return Kind == k_TSBHint; }
bool isCMHPriorityHint() const { return Kind == k_CMHPriorityHint; }
bool isTIndexHint() const { return Kind == k_TIndexHint; }
bool isShiftExtend() const { return Kind == k_ShiftExtend; }
@@ -2242,6 +2286,16 @@ class AArch64Operand : public MCParsedAsmOperand {
Inst.addOperand(MCOperand::createImm(getBTIHint()));
}
+ void addSHUHintOperands(MCInst &Inst, unsigned N) const {
+ assert(N == 1 && "Invalid number of operands!");
+ Inst.addOperand(MCOperand::createImm(getSHUHint()));
+ }
+
+ void addTSBHintOperands(MCInst &Inst, unsigned N) const {
+ assert(N == 1 && "Invalid number of operands!");
+ Inst.addOperand(MCOperand::createImm(getTSBHint()));
+ }
+
void addCMHPriorityHintOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createImm(getCMHPriorityHint()));
@@ -2599,6 +2653,28 @@ class AArch64Operand : public MCParsedAsmOperand {
return Op;
}
+ static std::unique_ptr<AArch64Operand>
+ CreateSHUHint(unsigned Val, StringRef Str, SMLoc S, MCContext &Ctx) {
+ auto Op = std::make_unique<AArch64Operand>(k_SHUHint, Ctx);
+ Op->SHUHint.Val = Val + 50;
+ Op->SHUHint.Data = Str.data();
+ Op->SHUHint.Length = Str.size();
+ Op->StartLoc = S;
+ Op->EndLoc = S;
+ return Op;
+ }
+
+ static std::unique_ptr<AArch64Operand>
+ CreateTSBHint(unsigned Val, StringRef Str, SMLoc S, MCContext &Ctx) {
+ auto Op = std::make_unique<AArch64Operand>(k_TSBHint, Ctx);
+ Op->TSBHint.Val = Val | 16;
+ Op->TSBHint.Data = Str.data();
+ Op->TSBHint.Length = Str.size();
+ Op->StartLoc = S;
+ Op->EndLoc = S;
+ return Op;
+ }
+
static std::unique_ptr<AArch64Operand>
CreateCMHPriorityHint(unsigned Val, StringRef Str, SMLoc S, MCContext &Ctx) {
auto Op = std::make_unique<AArch64Operand>(k_CMHPriorityHint, Ctx);
@@ -2731,6 +2807,12 @@ void AArch64Operand::print(raw_ostream &OS, const MCAsmInfo &MAI) const {
case k_BTIHint:
OS << getBTIHintName();
break;
+ case k_SHUHint:
+ OS << getSHUHintName();
+ break;
+ case k_TSBHint:
+ OS << getTSBHintName();
+ break;
case k_CMHPriorityHint:
OS << getCMHPriorityHintName();
break;
@@ -4450,6 +4532,39 @@ AArch64AsmParser::tryParsePHintInstOperand(OperandVector &Operands) {
return ParseStatus::Success;
}
+ParseStatus AArch64AsmParser::tryParseSHUHintOperand(OperandVector &Operands) {
+ SMLoc S = getLoc();
+ const AsmToken &Tok = getTok();
+ if (Tok.isNot(AsmToken::Identifier))
+ return TokError("invalid operand for instruction");
+
+ auto SHU =
+ AArch64CMHPriorityHint::lookupCMHPriorityHintByName(Tok.getString());
+ if (!SHU)
+ return TokError("invalid operand for instruction");
+
+ Operands.push_back(AArch64Operand::CreateSHUHint(
+ SHU->Encoding, Tok.getString(), S, getContext()));
+ Lex(); // Eat identifier token.
+ return ParseStatus::Success;
+}
+
+ParseStatus AArch64AsmParser::tryParseTSBHintOperand(OperandVector &Operands) {
+ SMLoc S = getLoc();
+ const AsmToken &Tok = getTok();
+ if (Tok.isNot(AsmToken::Identifier))
+ return TokError("'csync' operand expected");
+
+ auto TSB = AArch64TSB::lookupTSBByName(Tok.getString());
+ if (!TSB || TSB->Encoding != AArch64TSB::csync)
+ return TokError("'csync' operand expected");
+
+ Operands.push_back(AArch64Operand::CreateTSBHint(
+ TSB->Encoding, Tok.getString(), S, getContext()));
+ Lex(); // Eat identifier token.
+ return ParseStatus::Success;
+}
+
/// tryParseNeonVectorRegister - Parse a vector register operand.
bool AArch64AsmParser::tryParseNeonVectorRegister(OperandVector &Operands) {
if (getTok().isNot(AsmToken::Identifier))
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
index 2f4b3fa016336..779ef8e589346 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
@@ -1603,6 +1603,28 @@ void AArch64InstPrinter::printBTIHintOp(const MCInst *MI, unsigned OpNum,
markup(O, Markup::Immediate) << '#' << formatImm(btihintop);
}
+void AArch64InstPrinter::printSHUHintOp(const MCInst *MI, unsigned OpNum,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
+ unsigned shuhintop = MI->getOperand(OpNum).getImm() - 50;
+ auto SHU = AArch64CMHPriorityHint::lookupCMHPriorityHintByEncoding(shuhintop);
+ if (SHU)
+ O << SHU->Name;
+ else
+ markup(O, Markup::Immediate) << '#' << formatImm(shuhintop);
+}
+
+void AArch64InstPrinter::printTSBHintOp(const MCInst *MI, unsigned OpNum,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
+ unsigned tsbhintop = MI->getOperand(OpNum).getImm() ^ 16;
+ auto TSB = AArch64TSB::lookupTSBByEncoding(tsbhintop);
+ if (TSB)
+ O << TSB->Name;
+ else
+ markup(O, Markup::Immediate) << '#' << formatImm(tsbhintop);
+}
+
void AArch64InstPrinter::printCMHPriorityHintOp(const MCInst *MI,
unsigned OpNum,
const MCSubtargetInfo &STI,
@@ -1976,9 +1998,6 @@ void AArch64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo,
if (Opcode == AArch64::ISB) {
auto ISB = AArch64ISB::lookupISBByEncoding(Val);
Name = ISB ? ISB->Name : "";
- } else if (Opcode == AArch64::TSB) {
- auto TSB = AArch64TSB::lookupTSBByEncoding(Val);
- Name = TSB ? TSB->Name : "";
} else {
auto DB = AArch64DB::lookupDBByEncoding(Val);
Name = DB ? DB->Name : "";
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
index 3f7a3b4b0667b..ff4d7fef83b2e 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
@@ -153,6 +153,12 @@ class AArch64InstPrinter : public MCInstPrinter {
void printBTIHintOp(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
+ void printSHUHintOp(const MCInst *MI, unsigned OpNum,
+ const MCSubtargetInfo &STI, raw_ostream &O);
+
+ void printTSBHintOp(const MCInst *MI, unsigned OpNum,
+ const MCSubtargetInfo &STI, raw_ostream &O);
+
void printCMHPriorityHintOp(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
diff --git a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
index 3411b28d616d9..39f219c3787c8 100644
--- a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+++ b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
@@ -726,7 +726,7 @@ struct PHint {
#include "AArch64GenSystemOperands.inc"
const PHint *lookupPHintByName(StringRef);
-const PHint *lookupPHintByEncoding(uint16_t);
+const PHint *lookupPHintByEncoding(uint8_t);
} // namespace AArch64PHint
namespace AArch64BTIHint {
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